fix Simulator panicking when you use PhantomConst
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SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
11 changed files with 756 additions and 55 deletions
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@ -2244,3 +2244,41 @@ fn test_sim_resettable_counter_async_immediate_reset() {
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panic!();
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}
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}
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#[hdl_module(outline_generated)]
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pub fn phantom_const() {
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#[hdl]
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let out: Array<PhantomConst<Vec<String>>, 2> =
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m.output(Array::new_static(PhantomConst::new_sized(vec![
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"a".into(),
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"b".into(),
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])));
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let _ = out;
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#[hdl]
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let mut mem = memory(PhantomConst::new("mem_element"));
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mem.depth(1);
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let port = mem.new_read_port();
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connect_any(port.addr, 0u8);
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connect(port.clk, false.to_clock());
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connect(port.en, false);
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}
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#[test]
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fn test_phantom_const() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut sim = Simulation::new(phantom_const());
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let mut writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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sim.advance_time(SimDuration::from_micros(1));
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sim.flush_traces().unwrap();
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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if vcd != include_str!("sim/expected/phantom_const.vcd") {
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panic!();
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}
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let sim_debug = format!("{sim:#?}");
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println!("#######\n{sim_debug}\n#######");
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if sim_debug != include_str!("sim/expected/phantom_const.txt") {
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panic!();
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}
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}
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514
crates/fayalite/tests/sim/expected/phantom_const.txt
Normal file
514
crates/fayalite/tests/sim/expected/phantom_const.txt
Normal file
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@ -0,0 +1,514 @@
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Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 5,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<0>,
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},
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],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 7,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.addr",
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ty: UInt<0>,
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},
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SlotDebugData {
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name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<0>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Clock,
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},
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],
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..
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},
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sim_only_slots: StatePartLayout<SimOnlySlots> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 1,
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debug_data: [
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(),
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],
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layout_data: [
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MemoryData {
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array_type: Array<PhantomConst("mem_element"), 1>,
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data: [
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// len = 0x1
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[0x0]: 0x0,
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],
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},
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],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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0: Const {
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dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "", ty: Bool },
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value: 0x0,
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},
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1: Copy {
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dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Clock },
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src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:6:1
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2: Copy {
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dest: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.clk", ty: Clock },
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src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Clock },
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},
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// at: module-XXXXXXXXXX.rs:7:1
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3: Copy {
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dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.en", ty: Bool },
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src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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4: Const {
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dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
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value: 0x0,
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},
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5: CastToUInt {
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dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "", ty: UInt<0> },
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src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
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dest_width: 0,
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},
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// at: module-XXXXXXXXXX.rs:5:1
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6: Copy {
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dest: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.addr", ty: UInt<0> },
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src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "", ty: UInt<0> },
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},
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// at: module-XXXXXXXXXX.rs:3:1
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7: CastBigToArrayIndex {
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dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> },
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src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.addr", ty: UInt<0> },
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},
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8: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.en", ty: Bool },
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},
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9: BranchIfSmallZero {
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target: 11,
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value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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10: Branch {
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target: 11,
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},
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11: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.clk", ty: Clock },
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},
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12: AndSmall {
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dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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rhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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},
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13: BranchIfSmallZero {
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target: 14,
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value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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14: XorSmallImmediate {
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dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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rhs: 0x1,
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},
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// at: module-XXXXXXXXXX.rs:1:1
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15: Return,
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],
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..
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},
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pc: 15,
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memory_write_log: [],
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memories: StatePart {
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value: [
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MemoryData {
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array_type: Array<PhantomConst("mem_element"), 1>,
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data: [
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// len = 0x1
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[0x0]: 0x0,
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],
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},
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],
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},
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small_slots: StatePart {
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value: [
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1,
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0,
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0,
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0,
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0,
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],
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},
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big_slots: StatePart {
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value: [
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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],
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},
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sim_only_slots: StatePart {
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value: [],
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},
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},
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io: Instance {
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name: <simulator>::phantom_const,
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instantiated: Module {
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name: phantom_const,
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..
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},
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},
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main_module: SimulationModuleState {
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base_targets: [
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Instance {
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name: <simulator>::phantom_const,
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instantiated: Module {
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name: phantom_const,
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..
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},
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}.out,
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],
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uninitialized_ios: {},
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io_targets: {
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Instance {
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name: <simulator>::phantom_const,
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instantiated: Module {
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name: phantom_const,
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..
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},
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}.out,
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Instance {
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name: <simulator>::phantom_const,
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instantiated: Module {
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name: phantom_const,
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..
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},
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}.out[0],
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Instance {
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name: <simulator>::phantom_const,
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instantiated: Module {
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name: phantom_const,
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..
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},
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}.out[1],
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},
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did_initial_settle: true,
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},
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extern_modules: [],
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trace_decls: TraceModule {
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name: "phantom_const",
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children: [
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TraceModuleIO {
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name: "out",
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child: TraceArray {
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name: "out",
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elements: [
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TracePhantomConst {
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location: TraceScalarId(0),
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name: "[0]",
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ty: PhantomConst(
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["a","b"],
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),
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flow: Sink,
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},
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TracePhantomConst {
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location: TraceScalarId(1),
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name: "[1]",
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ty: PhantomConst(
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["a","b"],
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),
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flow: Sink,
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},
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],
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ty: Array<PhantomConst(["a","b"]), 2>,
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flow: Sink,
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},
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ty: Array<PhantomConst(["a","b"]), 2>,
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flow: Sink,
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},
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TraceMem {
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id: TraceMemoryId(0),
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name: "mem",
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stride: 0,
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element_type: TracePhantomConst {
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location: TraceMemoryLocation {
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id: TraceMemoryId(0),
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depth: 1,
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stride: 0,
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start: 0,
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len: 0,
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},
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name: "mem",
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ty: PhantomConst(
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"mem_element",
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),
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flow: Duplex,
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},
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ports: [
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TraceMemPort {
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name: "r0",
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bundle: TraceBundle {
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name: "r0",
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fields: [
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TraceUInt {
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location: TraceScalarId(2),
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name: "addr",
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ty: UInt<0>,
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flow: Sink,
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},
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TraceBool {
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location: TraceScalarId(3),
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name: "en",
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flow: Sink,
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},
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TraceClock {
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location: TraceScalarId(4),
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name: "clk",
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flow: Sink,
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},
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TracePhantomConst {
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location: TraceScalarId(5),
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name: "data",
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ty: PhantomConst(
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"mem_element",
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),
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flow: Source,
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},
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],
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ty: Bundle {
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/* offset = 0 */
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addr: UInt<0>,
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/* offset = 0 */
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en: Bool,
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/* offset = 1 */
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clk: Clock,
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#[hdl(flip)] /* offset = 2 */
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data: PhantomConst(
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"mem_element",
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),
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},
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flow: Sink,
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},
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ty: Bundle {
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/* offset = 0 */
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addr: UInt<0>,
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/* offset = 0 */
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en: Bool,
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/* offset = 1 */
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clk: Clock,
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#[hdl(flip)] /* offset = 2 */
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data: PhantomConst(
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"mem_element",
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),
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},
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},
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],
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array_type: Array<PhantomConst("mem_element"), 1>,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: PhantomConst {
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ty: PhantomConst(
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["a","b"],
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),
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},
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state: PhantomConst,
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last_state: PhantomConst,
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},
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SimTrace {
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id: TraceScalarId(1),
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kind: PhantomConst {
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ty: PhantomConst(
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["a","b"],
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),
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},
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state: PhantomConst,
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last_state: PhantomConst,
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},
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SimTrace {
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id: TraceScalarId(2),
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kind: BigUInt {
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index: StatePartIndex<BigSlots>(0),
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ty: UInt<0>,
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},
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state: 0x0,
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last_state: 0x0,
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},
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SimTrace {
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id: TraceScalarId(3),
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kind: BigBool {
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index: StatePartIndex<BigSlots>(1),
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},
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state: 0x0,
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last_state: 0x0,
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},
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SimTrace {
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id: TraceScalarId(4),
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kind: BigClock {
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index: StatePartIndex<BigSlots>(2),
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},
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state: 0x0,
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last_state: 0x0,
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},
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SimTrace {
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id: TraceScalarId(5),
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kind: PhantomConst {
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ty: PhantomConst(
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"mem_element",
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),
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},
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state: PhantomConst,
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last_state: PhantomConst,
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},
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],
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trace_memories: {
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StatePartIndex<Memories>(0): TraceMem {
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id: TraceMemoryId(0),
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name: "mem",
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stride: 0,
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element_type: TracePhantomConst {
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location: TraceMemoryLocation {
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id: TraceMemoryId(0),
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depth: 1,
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stride: 0,
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start: 0,
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len: 0,
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},
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name: "mem",
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ty: PhantomConst(
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"mem_element",
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),
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flow: Duplex,
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},
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ports: [
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TraceMemPort {
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name: "r0",
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bundle: TraceBundle {
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name: "r0",
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fields: [
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TraceUInt {
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location: TraceScalarId(2),
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name: "addr",
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ty: UInt<0>,
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flow: Sink,
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},
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TraceBool {
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location: TraceScalarId(3),
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name: "en",
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flow: Sink,
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},
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TraceClock {
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location: TraceScalarId(4),
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name: "clk",
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flow: Sink,
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},
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TracePhantomConst {
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location: TraceScalarId(5),
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name: "data",
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ty: PhantomConst(
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"mem_element",
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),
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flow: Source,
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},
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],
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ty: Bundle {
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/* offset = 0 */
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addr: UInt<0>,
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/* offset = 0 */
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en: Bool,
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/* offset = 1 */
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clk: Clock,
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#[hdl(flip)] /* offset = 2 */
|
||||
data: PhantomConst(
|
||||
"mem_element",
|
||||
),
|
||||
},
|
||||
flow: Sink,
|
||||
},
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
addr: UInt<0>,
|
||||
/* offset = 0 */
|
||||
en: Bool,
|
||||
/* offset = 1 */
|
||||
clk: Clock,
|
||||
#[hdl(flip)] /* offset = 2 */
|
||||
data: PhantomConst(
|
||||
"mem_element",
|
||||
),
|
||||
},
|
||||
},
|
||||
],
|
||||
array_type: Array<PhantomConst("mem_element"), 1>,
|
||||
},
|
||||
},
|
||||
trace_writers: [
|
||||
Running(
|
||||
VcdWriter {
|
||||
finished_init: true,
|
||||
timescale: 1 ps,
|
||||
..
|
||||
},
|
||||
),
|
||||
],
|
||||
clocks_triggered: [
|
||||
StatePartIndex<SmallSlots>(1),
|
||||
],
|
||||
event_queue: EventQueue(EventQueueData {
|
||||
instant: 1 μs,
|
||||
events: {},
|
||||
}),
|
||||
waiting_sensitivity_sets_by_address: {},
|
||||
waiting_sensitivity_sets_by_compiled_value: {},
|
||||
..
|
||||
}
|
||||
31
crates/fayalite/tests/sim/expected/phantom_const.vcd
Normal file
31
crates/fayalite/tests/sim/expected/phantom_const.vcd
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
$timescale 1 ps $end
|
||||
$scope module phantom_const $end
|
||||
$scope struct out $end
|
||||
$var string 1 ! \[0] $end
|
||||
$var string 1 " \[1] $end
|
||||
$upscope $end
|
||||
$scope struct mem $end
|
||||
$scope struct contents $end
|
||||
$scope struct \[0] $end
|
||||
$var string 1 ' mem $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope struct r0 $end
|
||||
$var string 0 # addr $end
|
||||
$var wire 1 $ en $end
|
||||
$var wire 1 % clk $end
|
||||
$var string 1 & data $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
s0 '
|
||||
sPhantomConst([\"a\",\"b\"]) !
|
||||
sPhantomConst([\"a\",\"b\"]) "
|
||||
s0 #
|
||||
0$
|
||||
0%
|
||||
sPhantomConst(\"mem_element\") &
|
||||
$end
|
||||
#1000000
|
||||
Loading…
Add table
Add a link
Reference in a new issue