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wire up simulator trace writing interface

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This commit is contained in:
Jacob Lifshay 2024-11-17 21:02:44 -08:00
parent 288a6b71b9
commit 09aa9fbc78
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
6 changed files with 1046 additions and 184 deletions
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10
crates/fayalite/src/expr/target.rs
View file

@ -14,7 +14,7 @@ use crate::{
}; };
use std::fmt; use std::fmt;
#[derive(Debug, Clone, PartialEq, Eq, Hash)] #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
pub struct TargetPathBundleField { pub struct TargetPathBundleField {
pub name: Interned<str>, pub name: Interned<str>,
} }
@ -25,7 +25,7 @@ impl fmt::Display for TargetPathBundleField {
} }
} }
#[derive(Debug, Clone, PartialEq, Eq, Hash)] #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
pub struct TargetPathArrayElement { pub struct TargetPathArrayElement {
pub index: usize, pub index: usize,
} }
@ -36,7 +36,7 @@ impl fmt::Display for TargetPathArrayElement {
} }
} }
#[derive(Debug, Clone, PartialEq, Eq, Hash)] #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
pub struct TargetPathDynArrayElement {} pub struct TargetPathDynArrayElement {}
impl fmt::Display for TargetPathDynArrayElement { impl fmt::Display for TargetPathDynArrayElement {
@ -45,7 +45,7 @@ impl fmt::Display for TargetPathDynArrayElement {
} }
} }
#[derive(Debug, Clone, PartialEq, Eq, Hash)] #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
pub enum TargetPathElement { pub enum TargetPathElement {
BundleField(TargetPathBundleField), BundleField(TargetPathBundleField),
ArrayElement(TargetPathArrayElement), ArrayElement(TargetPathArrayElement),
@ -197,7 +197,7 @@ macro_rules! impl_target_base {
} }
impl_target_base! { impl_target_base! {
#[derive(Clone, PartialEq, Eq, Hash)] #[derive(Copy, Clone, PartialEq, Eq, Hash)]
pub enum TargetBase { pub enum TargetBase {
#[is = is_module_io] #[is = is_module_io]
#[to = module_io] #[to = module_io]

832
crates/fayalite/src/sim.rs
View file

File diff suppressed because it is too large Load diff

28
crates/fayalite/src/sim/interpreter.rs
View file

@ -477,10 +477,10 @@ pub(crate) struct Labels {
#[derive(Clone, PartialEq, Eq, Hash)] #[derive(Clone, PartialEq, Eq, Hash)]
pub(crate) struct Insns<BK: InsnsBuildingKind> { pub(crate) struct Insns<BK: InsnsBuildingKind> {
insns: BK::Vec<Insn>, pub(crate) insns: BK::Vec<Insn>,
insn_source_locations: BK::Vec<SourceLocation>, pub(crate) insn_source_locations: BK::Vec<SourceLocation>,
labels: BK::Labels, pub(crate) labels: BK::Labels,
state_layout: StateLayout<BK>, pub(crate) state_layout: StateLayout<BK>,
} }
impl<BK: InsnsBuildingKind> Insns<BK> { impl<BK: InsnsBuildingKind> Insns<BK> {
@ -1228,6 +1228,26 @@ impl TypeLen {
}; };
Some(small_slots) Some(small_slots)
} }
pub(crate) const A_SMALL_SLOT: Self = TypeLen {
small_slots: StatePartLen {
value: 1,
_phantom: PhantomData,
},
big_slots: StatePartLen {
value: 0,
_phantom: PhantomData,
},
};
pub(crate) const A_BIG_SLOT: Self = TypeLen {
small_slots: StatePartLen {
value: 0,
_phantom: PhantomData,
},
big_slots: StatePartLen {
value: 1,
_phantom: PhantomData,
},
};
} }
#[derive(Debug, Clone)] #[derive(Debug, Clone)]

54
crates/fayalite/src/sim/time.rs
View file

@ -1,12 +1,45 @@
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information // See Notices.txt for copyright information
use std::{fmt, time::Duration}; use std::{
fmt,
ops::{Add, AddAssign},
time::Duration,
};
#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Default)] #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
pub struct SimInstant { pub struct SimInstant {
time_since_start: SimDuration, time_since_start: SimDuration,
} }
impl Add<SimDuration> for SimInstant {
type Output = SimInstant;
fn add(mut self, rhs: SimDuration) -> Self::Output {
self += rhs;
self
}
}
impl AddAssign<SimDuration> for SimInstant {
fn add_assign(&mut self, rhs: SimDuration) {
self.time_since_start += rhs;
}
}
impl Add<SimInstant> for SimDuration {
type Output = SimInstant;
fn add(self, rhs: SimInstant) -> Self::Output {
rhs.add(self)
}
}
impl SimInstant {
pub const START: SimInstant = SimInstant {
time_since_start: SimDuration::ZERO,
};
}
impl fmt::Debug for SimInstant { impl fmt::Debug for SimInstant {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
self.time_since_start.fmt(f) self.time_since_start.fmt(f)
@ -18,6 +51,25 @@ pub struct SimDuration {
attos: u128, attos: u128,
} }
impl AddAssign for SimDuration {
fn add_assign(&mut self, rhs: SimDuration) {
*self = *self + rhs;
}
}
impl Add for SimDuration {
type Output = SimDuration;
fn add(self, rhs: SimDuration) -> Self::Output {
SimDuration {
attos: self
.attos
.checked_add(rhs.attos)
.expect("overflow adding durations"),
}
}
}
#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)] #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)]
pub struct SimDurationParts { pub struct SimDurationParts {
pub attos: u16, pub attos: u16,

8
crates/fayalite/src/util/misc.rs
View file

@ -94,9 +94,15 @@ pub fn interned_bit(v: bool) -> Interned<BitSlice> {
RETVAL.get_or_init(|| [bits![0; 1].intern(), bits![1; 1].intern()])[v as usize] RETVAL.get_or_init(|| [bits![0; 1].intern(), bits![1; 1].intern()])[v as usize]
} }
#[derive(Copy, Clone, Debug)] #[derive(Copy, Clone)]
pub struct BitSliceWriteWithBase<'a>(pub &'a BitSlice); pub struct BitSliceWriteWithBase<'a>(pub &'a BitSlice);
impl<'a> Debug for BitSliceWriteWithBase<'a> {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
write!(f, "{self:#x}")
}
}
impl BitSliceWriteWithBase<'_> { impl BitSliceWriteWithBase<'_> {
fn fmt_with_base<const BITS_PER_DIGIT: usize, const UPPER_CASE: bool>( fn fmt_with_base<const BITS_PER_DIGIT: usize, const UPPER_CASE: bool>(
self, self,

298
crates/fayalite/tests/sim.rs
View file

@ -117,10 +117,33 @@ fn test_connect_const() {
made_initial_step: true, made_initial_step: true,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "connect_const", name: "connect_const",
children: [], children: [
TraceModuleIO {
name: "o",
child: TraceUInt {
id: TraceScalarId(0),
name: "o",
ty: UInt<8>,
flow: Sink,
},
ty: UInt<8>,
flow: Sink,
},
],
}, },
traces: [], traces: [
SimTrace {
id: TraceScalarId(0),
kind: BigUInt {
index: StatePartIndex<BigSlots>(0),
ty: UInt<8>,
},
state: 0x05,
last_state: 0x05,
},
],
trace_writers: [], trace_writers: [],
instant: 0 s,
}"# { }"# {
panic!(); panic!();
} }
@ -681,10 +704,277 @@ fn test_mod1() {
made_initial_step: true, made_initial_step: true,
trace_decls: TraceModule { trace_decls: TraceModule {
name: "mod1", name: "mod1",
children: [], children: [
TraceModuleIO {
name: "o",
child: TraceBundle {
name: "o",
fields: [
TraceUInt {
id: TraceScalarId(0),
name: "i",
ty: UInt<4>,
flow: Source,
},
TraceSInt {
id: TraceScalarId(1),
name: "o",
ty: SInt<2>,
flow: Sink,
},
TraceSInt {
id: TraceScalarId(2),
name: "i2",
ty: SInt<2>,
flow: Source,
},
TraceUInt {
id: TraceScalarId(3),
name: "o2",
ty: UInt<4>,
flow: Sink,
},
],
ty: Bundle {
#[hdl(flip)] /* offset = 0 */
i: UInt<4>,
/* offset = 4 */
o: SInt<2>,
#[hdl(flip)] /* offset = 6 */
i2: SInt<2>,
/* offset = 8 */
o2: UInt<4>,
},
flow: Sink,
},
ty: Bundle {
#[hdl(flip)] /* offset = 0 */
i: UInt<4>,
/* offset = 4 */
o: SInt<2>,
#[hdl(flip)] /* offset = 6 */
i2: SInt<2>,
/* offset = 8 */
o2: UInt<4>,
},
flow: Sink,
},
TraceInstance {
name: "child",
instance_io: TraceBundle {
name: "child",
fields: [
TraceUInt {
id: TraceScalarId(8),
name: "i",
ty: UInt<4>,
flow: Sink,
},
TraceSInt {
id: TraceScalarId(9),
name: "o",
ty: SInt<2>,
flow: Source,
},
TraceSInt {
id: TraceScalarId(10),
name: "i2",
ty: SInt<2>,
flow: Sink,
},
TraceUInt {
id: TraceScalarId(11),
name: "o2",
ty: UInt<4>,
flow: Source,
},
],
ty: Bundle {
#[hdl(flip)] /* offset = 0 */
i: UInt<4>,
/* offset = 4 */
o: SInt<2>,
#[hdl(flip)] /* offset = 6 */
i2: SInt<2>,
/* offset = 8 */
o2: UInt<4>,
},
flow: Source,
},
module: TraceModule {
name: "mod1_child",
children: [
TraceModuleIO {
name: "i",
child: TraceUInt {
id: TraceScalarId(4),
name: "i",
ty: UInt<4>,
flow: Source,
},
ty: UInt<4>,
flow: Source,
},
TraceModuleIO {
name: "o",
child: TraceSInt {
id: TraceScalarId(5),
name: "o",
ty: SInt<2>,
flow: Sink,
},
ty: SInt<2>,
flow: Sink,
},
TraceModuleIO {
name: "i2",
child: TraceSInt {
id: TraceScalarId(6),
name: "i2",
ty: SInt<2>,
flow: Source,
},
ty: SInt<2>,
flow: Source,
},
TraceModuleIO {
name: "o2",
child: TraceUInt {
id: TraceScalarId(7),
name: "o2",
ty: UInt<4>,
flow: Sink,
},
ty: UInt<4>,
flow: Sink,
},
],
},
ty: Bundle {
#[hdl(flip)] /* offset = 0 */
i: UInt<4>,
/* offset = 4 */
o: SInt<2>,
#[hdl(flip)] /* offset = 6 */
i2: SInt<2>,
/* offset = 8 */
o2: UInt<4>,
},
},
],
}, },
traces: [], traces: [
SimTrace {
id: TraceScalarId(0),
kind: BigUInt {
index: StatePartIndex<BigSlots>(0),
ty: UInt<4>,
},
state: 0xa,
last_state: 0xa,
},
SimTrace {
id: TraceScalarId(1),
kind: BigSInt {
index: StatePartIndex<BigSlots>(1),
ty: SInt<2>,
},
state: 0x2,
last_state: 0x2,
},
SimTrace {
id: TraceScalarId(2),
kind: BigSInt {
index: StatePartIndex<BigSlots>(2),
ty: SInt<2>,
},
state: 0x2,
last_state: 0x2,
},
SimTrace {
id: TraceScalarId(3),
kind: BigUInt {
index: StatePartIndex<BigSlots>(3),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(4),
kind: BigUInt {
index: StatePartIndex<BigSlots>(8),
ty: UInt<4>,
},
state: 0xa,
last_state: 0xa,
},
SimTrace {
id: TraceScalarId(5),
kind: BigSInt {
index: StatePartIndex<BigSlots>(9),
ty: SInt<2>,
},
state: 0x2,
last_state: 0x2,
},
SimTrace {
id: TraceScalarId(6),
kind: BigSInt {
index: StatePartIndex<BigSlots>(10),
ty: SInt<2>,
},
state: 0x2,
last_state: 0x2,
},
SimTrace {
id: TraceScalarId(7),
kind: BigUInt {
index: StatePartIndex<BigSlots>(11),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(8),
kind: BigUInt {
index: StatePartIndex<BigSlots>(4),
ty: UInt<4>,
},
state: 0xa,
last_state: 0xa,
},
SimTrace {
id: TraceScalarId(9),
kind: BigSInt {
index: StatePartIndex<BigSlots>(5),
ty: SInt<2>,
},
state: 0x2,
last_state: 0x2,
},
SimTrace {
id: TraceScalarId(10),
kind: BigSInt {
index: StatePartIndex<BigSlots>(6),
ty: SInt<2>,
},
state: 0x2,
last_state: 0x2,
},
SimTrace {
id: TraceScalarId(11),
kind: BigUInt {
index: StatePartIndex<BigSlots>(7),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
],
trace_writers: [], trace_writers: [],
instant: 0 s,
}"# { }"# {
panic!(); panic!();
} }