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implement "Create the next-instruction logic" and "Create a model of the instruction fetch/decode control system" #5

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programmerjake merged 19 commits from programmerjake/cpu:next-pc into master 2025-12-17 07:55:08 +00:00
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crates/cpu/src/next_pc.rs
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// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
//! [Next-Instruction Logic](https://git.libre-chip.org/libre-chip/grant-tracking/issues/10)
//! Next-Instruction Logic and Instruction Fetch/Decode Control System
//! [#10](https://git.libre-chip.org/libre-chip/grant-tracking/issues/10)
//! and [#13](https://git.libre-chip.org/libre-chip/grant-tracking/issues/13).
//!
//! This could use a lot more optimization, but it works AFAIK.
//!
//! The basic idea here is that there's a `next_pc` stage that sends predicted fetch PCs to the `fetch` stage,
//! the `fetch` stage's outputs eventually end up in the `decode` stage,