libre-chip/cpu
3
0
Fork 2
Code Issues 1 Pull requests 1 Projects Releases Packages Wiki Activity Actions

WIP: add cpu::test::decode_and_run_single_insn and some formal tests of running PowerISA instructions #15

Draft
programmerjake wants to merge 7 commits from programmerjake/cpu:decode-and-test-harness into master
pull from: programmerjake/cpu:decode-and-test-harness
merge into: libre-chip:master
Conversation 0 Commits 7 Files changed 23 +4
1 changed files with 4 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files
Showing only changes of commit 7fc205e583 - Show all commits

4
crates/cpu/src/util/array_vec.rs
View file

@ -226,6 +226,10 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
#[hdl]
let mapped_array_vec = wire(this.ty().mapped_ty(new_element_ty));
connect(mapped_array_vec.len, this.len);
connect(
mapped_array_vec.elements,
mapped_array_vec.ty().elements.uninit(),
);
Self::for_each(this, |index, element| {
connect(mapped_array_vec[index], f(index, element));
});