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WIP: add cpu::test::decode_and_run_single_insn and some formal tests of running PowerISA instructions #15

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programmerjake wants to merge 7 commits from programmerjake/cpu:decode-and-test-harness into master
pull from: programmerjake/cpu:decode-and-test-harness
merge into: libre-chip:master
Conversation 0 Commits 7 Files changed 23 +16 -6
1 changed files with 16 additions and 6 deletions
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22
crates/cpu/tests/units_formal.rs
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@ -28,9 +28,7 @@ use std::num::NonZero;
#[hdl_module]
fn formal_harness(config: PhantomConst<CpuConfig>) {
#[hdl]
let cd: ClockDomain = m.output();
connect(cd.clk, fayalite::formal::formal_global_clock());
connect(cd.rst, fayalite::formal::formal_reset().to_reset());
let cd: ClockDomain = m.input();
#[hdl]
let input: DecodeAndRunSingleInsnInput<
@ -99,9 +97,21 @@ fn formal_harness(config: PhantomConst<CpuConfig>) {
#[hdl_module]
fn check_power_isa_add_formal(config: PhantomConst<CpuConfig>) {
#[hdl]
let clk: Clock = m.input();
#[hdl]
let cd = wire();
connect(
cd,
#[hdl]
ClockDomain {
clk,
rst: formal_reset().to_reset(),
},
);
#[hdl]
let harness = instance(formal_harness(config));
let cd = harness.cd;
connect(harness.cd, cd);
#[hdl]
let DecodeAndRunSingleInsnInput::<_, _> {
decoder_input,
@ -208,11 +218,11 @@ fn test_power_isa_add_formal() {
vec![UnitConfig::new(UnitKind::AluBranch)],
NonZero::new(20).unwrap(),
));
let dut = check_power_isa_add_formal(config);
let m = check_power_isa_add_formal(config);
println!("starting assert formal");
assert_formal(
"test_power_isa_add_formal",
dut,
m,
FormalMode::Prove,
10,
None,