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17 commits

Author SHA1 Message Date
Jacob Lifshay 3f6e5cc600
WIP implementing unit_base
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2025-02-19 23:54:41 -08:00
Jacob Lifshay 2b7e7e4946
WIP adding unit input/output values and insn tracking
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2025-02-13 20:55:43 -08:00
Jacob Lifshay 1084278f34
reg_alloc: add writes to rename table
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2025-02-11 19:19:06 -08:00
Jacob Lifshay 294e979848
tests/reg_alloc: remove simulator debug output
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2025-02-06 21:31:05 -08:00
Jacob Lifshay 7efcd872b5
working on reg_alloc
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2025-02-06 21:28:30 -08:00
Jacob Lifshay 88eff5952b
working on reg_alloc -- wire up free_regs_tracker.alloc_out
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2025-01-15 19:47:00 -08:00
Jacob Lifshay 5f7766777a
working on reg_alloc -- selected_unit_nums should be correct now
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2025-01-12 22:12:58 -08:00
Jacob Lifshay 89717f8916
update to latest version of fayalite
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2025-01-09 23:36:23 -08:00
Jacob Lifshay 12481cfab3
start debugging reg_alloc with simulator
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2024-12-20 00:28:22 -08:00
Jacob Lifshay b51109f4f6
WIP implementing reg_alloc
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2024-11-05 17:34:31 -08:00
Jacob Lifshay a305ad51b2
reduce formal proof depth to avoid z3 eating all our memory 2024-10-15 23:50:51 -07:00
Jacob Lifshay aaa2cb193e
add formal proof for unit_free_regs_tracker
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2024-10-15 02:39:56 -07:00
Jacob Lifshay cb5855589f
WIP adding register allocator
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2024-10-14 21:20:42 -07:00
Jacob Lifshay d7f62737f2
add license headers 2024-10-14 16:29:20 -07:00
Jacob Lifshay f65fc1d616
add more register stuff 2024-10-13 01:41:45 -07:00
Jacob Lifshay 4c3dd128a3
WIP: adding micro ops 2024-10-10 22:57:11 -07:00
Jacob Lifshay 0f4f067996
start adding cpu data types 2024-10-08 20:22:15 -07:00