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simplify tests/simple_power_isa_decoder::test_cases somewhat

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This commit is contained in:
Jacob Lifshay 2026-01-19 14:16:00 -08:00
parent 62a330ed4d
commit aa85ecab01
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
2 changed files with 91 additions and 134 deletions
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7
crates/cpu/src/instruction/power_isa.rs
View file

@ -122,6 +122,13 @@ impl MOpRegNum {
} }
} }
#[hdl] #[hdl]
pub fn power_isa_gpr_reg_imm(index: usize) -> Expr<Self> {
#[hdl]
Self {
value: Self::power_isa_gpr_reg_num(index).cast_to_static::<UInt<_>>(),
}
}
#[hdl]
pub fn power_isa_gpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> { pub fn power_isa_gpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
#[hdl(sim)] #[hdl(sim)]
Self { Self {

218
crates/cpu/tests/simple_power_isa_decoder.rs
View file

@ -49,7 +49,6 @@ impl fmt::Debug for TestCase {
} }
} }
#[hdl]
fn test_cases() -> Vec<TestCase> { fn test_cases() -> Vec<TestCase> {
let mut retval = Vec::new(); let mut retval = Vec::new();
#[track_caller] #[track_caller]
@ -93,12 +92,11 @@ fn test_cases() -> Vec<TestCase> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
false, false,
false, false,
@ -112,12 +110,11 @@ fn test_cases() -> Vec<TestCase> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0x123456789i64.cast_to_static::<SInt<_>>(), 0x123456789i64.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
false, false,
false, false,
@ -132,8 +129,7 @@ fn test_cases() -> Vec<TestCase> {
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero().value, MOpRegNum::const_zero().value], [MOpRegNum::const_zero().value, MOpRegNum::const_zero().value],
0x123456789i64.cast_to_static::<SInt<_>>(), 0x123456789i64.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
false, false,
false, false,
@ -147,12 +143,11 @@ fn test_cases() -> Vec<TestCase> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0x12340000.cast_to_static::<SInt<_>>(), 0x12340000.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
false, false,
false, false,
@ -167,8 +162,7 @@ fn test_cases() -> Vec<TestCase> {
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero().value; _], [MOpRegNum::const_zero().value; _],
0x12340004.cast_to_static::<SInt<_>>(), 0x12340004.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
false, false,
false, false,
@ -185,13 +179,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
false, false,
false, false,
@ -211,12 +204,11 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
false, false,
false, false,
@ -233,13 +225,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
true, true,
false, false,
true, true,
@ -259,12 +250,11 @@ fn test_cases() -> Vec<TestCase> {
&[], &[],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
true, true,
false, false,
true, true,
@ -284,13 +274,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
false, false,
false, false,
@ -310,13 +299,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
true, true,
false, false,
true, true,
@ -336,13 +324,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
true, true,
false, false,
@ -362,13 +349,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
true, true,
true, true,
false, false,
@ -388,13 +374,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
(-1i8).cast_to_static::<SInt<_>>(), (-1i8).cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
true, true,
false, false,
@ -414,13 +399,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
(-1i8).cast_to_static::<SInt<_>>(), (-1i8).cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
true, true,
true, true,
false, false,
@ -440,13 +424,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
false, false,
true, true,
false, false,
@ -466,13 +449,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
true, true,
true, true,
false, false,
@ -489,13 +471,12 @@ fn test_cases() -> Vec<TestCase> {
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
MOpRegNum::const_zero().value, MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(),
true, true,
false, false,
true, true,
@ -508,12 +489,10 @@ fn test_cases() -> Vec<TestCase> {
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value], [MOpRegNum::power_isa_gpr_reg_imm(4).value],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.S32(),
#[hdl(sim)]
CompareMode::S32(),
), ),
)); ));
retval.push(insn_single( retval.push(insn_single(
@ -522,12 +501,10 @@ fn test_cases() -> Vec<TestCase> {
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value], [MOpRegNum::power_isa_gpr_reg_imm(4).value],
(0x89abu16 as i16).cast_to_static::<SInt<_>>(), (0x89abu16 as i16).cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.S64(),
#[hdl(sim)]
CompareMode::S64(),
), ),
)); ));
retval.push(insn_single( retval.push(insn_single(
@ -537,14 +514,12 @@ fn test_cases() -> Vec<TestCase> {
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.S32(),
#[hdl(sim)]
CompareMode::S32(),
), ),
)); ));
retval.push(insn_single( retval.push(insn_single(
@ -554,14 +529,12 @@ fn test_cases() -> Vec<TestCase> {
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.S64(),
#[hdl(sim)]
CompareMode::S64(),
), ),
)); ));
retval.push(insn_single( retval.push(insn_single(
@ -570,12 +543,10 @@ fn test_cases() -> Vec<TestCase> {
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value], [MOpRegNum::power_isa_gpr_reg_imm(4).value],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.U32(),
#[hdl(sim)]
CompareMode::U32(),
), ),
)); ));
retval.push(insn_single( retval.push(insn_single(
@ -584,12 +555,10 @@ fn test_cases() -> Vec<TestCase> {
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value], [MOpRegNum::power_isa_gpr_reg_imm(4).value],
0x89ab.cast_to_static::<SInt<_>>(), 0x89ab.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.U64(),
#[hdl(sim)]
CompareMode::U64(),
), ),
)); ));
retval.push(insn_single( retval.push(insn_single(
@ -599,14 +568,12 @@ fn test_cases() -> Vec<TestCase> {
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.U32(),
#[hdl(sim)]
CompareMode::U32(),
), ),
)); ));
retval.push(insn_single( retval.push(insn_single(
@ -616,14 +583,12 @@ fn test_cases() -> Vec<TestCase> {
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.U64(),
#[hdl(sim)]
CompareMode::U64(),
), ),
)); ));
retval.push(insn_single( retval.push(insn_single(
@ -633,14 +598,12 @@ fn test_cases() -> Vec<TestCase> {
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.CmpRBOne(),
#[hdl(sim)]
CompareMode::CmpRBOne(),
), ),
)); ));
retval.push(insn_single( retval.push(insn_single(
@ -650,14 +613,12 @@ fn test_cases() -> Vec<TestCase> {
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.CmpRBTwo(),
#[hdl(sim)]
CompareMode::CmpRBTwo(),
), ),
)); ));
retval.push(insn_single( retval.push(insn_single(
@ -667,14 +628,12 @@ fn test_cases() -> Vec<TestCase> {
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
#[hdl(sim)] OutputIntegerMode.Full64(),
OutputIntegerMode::Full64(), CompareMode.CmpEqB(),
#[hdl(sim)]
CompareMode::CmpEqB(),
), ),
)); ));
macro_rules! insn_logic_i { macro_rules! insn_logic_i {
@ -704,10 +663,7 @@ fn test_cases() -> Vec<TestCase> {
&[] &[]
}, },
), ),
[MOpRegNum::power_isa_gpr_reg( [MOpRegNum::power_isa_gpr_reg_imm($src).value],
($src as u8).cast_to_static::<UInt<_>>().to_expr(),
)
.value],
(($imm as u32) << if $mnemonic.contains('s') { 16 } else { 0 }) (($imm as u32) << if $mnemonic.contains('s') { 16 } else { 0 })
.cast_to_static::<SInt<_>>(), .cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -781,14 +737,8 @@ fn test_cases() -> Vec<TestCase> {
}, },
), ),
[ [
MOpRegNum::power_isa_gpr_reg( MOpRegNum::power_isa_gpr_reg_imm($src0).value,
($src0 as u8).cast_to_static::<UInt<_>>().to_expr(), MOpRegNum::power_isa_gpr_reg_imm($src1).value,
)
.value,
MOpRegNum::power_isa_gpr_reg(
($src1 as u8).cast_to_static::<UInt<_>>().to_expr(),
)
.value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -838,7 +788,7 @@ fn test_cases() -> Vec<TestCase> {
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value], [MOpRegNum::power_isa_gpr_reg_imm(4).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));