diff --git a/crates/cpu/src/instruction/power_isa.rs b/crates/cpu/src/instruction/power_isa.rs
index cd105c3..edf4637 100644
--- a/crates/cpu/src/instruction/power_isa.rs
+++ b/crates/cpu/src/instruction/power_isa.rs
@@ -122,6 +122,13 @@ impl MOpRegNum {
         }
     }
     #[hdl]
+    pub fn power_isa_gpr_reg_imm(index: usize) -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::power_isa_gpr_reg_num(index).cast_to_static::<UInt<_>>(),
+        }
+    }
+    #[hdl]
     pub fn power_isa_gpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
         #[hdl(sim)]
         Self {
diff --git a/crates/cpu/tests/simple_power_isa_decoder.rs b/crates/cpu/tests/simple_power_isa_decoder.rs
index aa73b3a..02b677c 100644
--- a/crates/cpu/tests/simple_power_isa_decoder.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder.rs
@@ -49,7 +49,6 @@ impl fmt::Debug for TestCase {
     }
 }
 
-#[hdl]
 fn test_cases() -> Vec<TestCase> {
     let mut retval = Vec::new();
     #[track_caller]
@@ -93,12 +92,11 @@ fn test_cases() -> Vec<TestCase> {
         AddSubMOp::add_sub_i(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::const_zero().value,
             ],
             0x1234.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             false,
             false,
@@ -112,12 +110,11 @@ fn test_cases() -> Vec<TestCase> {
         AddSubMOp::add_sub_i(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::const_zero().value,
             ],
             0x123456789i64.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             false,
             false,
@@ -132,8 +129,7 @@ fn test_cases() -> Vec<TestCase> {
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
             [MOpRegNum::const_zero().value, MOpRegNum::const_zero().value],
             0x123456789i64.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             false,
             false,
@@ -147,12 +143,11 @@ fn test_cases() -> Vec<TestCase> {
         AddSubMOp::add_sub_i(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::const_zero().value,
             ],
             0x12340000.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             false,
             false,
@@ -167,8 +162,7 @@ fn test_cases() -> Vec<TestCase> {
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
             [MOpRegNum::const_zero().value; _],
             0x12340004.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             false,
             false,
@@ -185,13 +179,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
                 MOpRegNum::const_zero().value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             false,
             false,
@@ -211,12 +204,11 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::const_zero().value,
             ],
             0x1234.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             false,
             false,
@@ -233,13 +225,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
                 MOpRegNum::const_zero().value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             true,
             false,
             true,
@@ -259,12 +250,11 @@ fn test_cases() -> Vec<TestCase> {
                 &[],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::const_zero().value,
             ],
             0x1234.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             true,
             false,
             true,
@@ -284,13 +274,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
                 MOpRegNum::const_zero().value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             false,
             false,
@@ -310,13 +299,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
                 MOpRegNum::const_zero().value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             true,
             false,
             true,
@@ -336,13 +324,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::power_isa_xer_ca_ca32_reg().value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             true,
             false,
@@ -362,13 +349,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::power_isa_xer_ca_ca32_reg().value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             true,
             true,
             false,
@@ -388,13 +374,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::power_isa_xer_ca_ca32_reg().value,
                 MOpRegNum::const_zero().value,
             ],
             (-1i8).cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             true,
             false,
@@ -414,13 +399,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::power_isa_xer_ca_ca32_reg().value,
                 MOpRegNum::const_zero().value,
             ],
             (-1i8).cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             true,
             true,
             false,
@@ -440,13 +424,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::power_isa_xer_ca_ca32_reg().value,
                 MOpRegNum::const_zero().value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             false,
             true,
             false,
@@ -466,13 +449,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::power_isa_xer_ca_ca32_reg().value,
                 MOpRegNum::const_zero().value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             true,
             true,
             false,
@@ -489,13 +471,12 @@ fn test_cases() -> Vec<TestCase> {
                 &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
             ),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
                 MOpRegNum::const_zero().value,
                 MOpRegNum::const_zero().value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
+            OutputIntegerMode.Full64(),
             true,
             false,
             true,
@@ -508,12 +489,10 @@ fn test_cases() -> Vec<TestCase> {
         None,
         CompareMOp::compare_i(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
-            [MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value],
+            [MOpRegNum::power_isa_gpr_reg_imm(4).value],
             0x1234.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::S32(),
+            OutputIntegerMode.Full64(),
+            CompareMode.S32(),
         ),
     ));
     retval.push(insn_single(
@@ -522,12 +501,10 @@ fn test_cases() -> Vec<TestCase> {
         None,
         CompareMOp::compare_i(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
-            [MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value],
+            [MOpRegNum::power_isa_gpr_reg_imm(4).value],
             (0x89abu16 as i16).cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::S64(),
+            OutputIntegerMode.Full64(),
+            CompareMode.S64(),
         ),
     ));
     retval.push(insn_single(
@@ -537,14 +514,12 @@ fn test_cases() -> Vec<TestCase> {
         CompareMOp::compare(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::S32(),
+            OutputIntegerMode.Full64(),
+            CompareMode.S32(),
         ),
     ));
     retval.push(insn_single(
@@ -554,14 +529,12 @@ fn test_cases() -> Vec<TestCase> {
         CompareMOp::compare(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::S64(),
+            OutputIntegerMode.Full64(),
+            CompareMode.S64(),
         ),
     ));
     retval.push(insn_single(
@@ -570,12 +543,10 @@ fn test_cases() -> Vec<TestCase> {
         None,
         CompareMOp::compare_i(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
-            [MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value],
+            [MOpRegNum::power_isa_gpr_reg_imm(4).value],
             0x1234.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::U32(),
+            OutputIntegerMode.Full64(),
+            CompareMode.U32(),
         ),
     ));
     retval.push(insn_single(
@@ -584,12 +555,10 @@ fn test_cases() -> Vec<TestCase> {
         None,
         CompareMOp::compare_i(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
-            [MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value],
+            [MOpRegNum::power_isa_gpr_reg_imm(4).value],
             0x89ab.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::U64(),
+            OutputIntegerMode.Full64(),
+            CompareMode.U64(),
         ),
     ));
     retval.push(insn_single(
@@ -599,14 +568,12 @@ fn test_cases() -> Vec<TestCase> {
         CompareMOp::compare(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::U32(),
+            OutputIntegerMode.Full64(),
+            CompareMode.U32(),
         ),
     ));
     retval.push(insn_single(
@@ -616,14 +583,12 @@ fn test_cases() -> Vec<TestCase> {
         CompareMOp::compare(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::U64(),
+            OutputIntegerMode.Full64(),
+            CompareMode.U64(),
         ),
     ));
     retval.push(insn_single(
@@ -633,14 +598,12 @@ fn test_cases() -> Vec<TestCase> {
         CompareMOp::compare(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::CmpRBOne(),
+            OutputIntegerMode.Full64(),
+            CompareMode.CmpRBOne(),
         ),
     ));
     retval.push(insn_single(
@@ -650,14 +613,12 @@ fn test_cases() -> Vec<TestCase> {
         CompareMOp::compare(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::CmpRBTwo(),
+            OutputIntegerMode.Full64(),
+            CompareMode.CmpRBTwo(),
         ),
     ));
     retval.push(insn_single(
@@ -667,14 +628,12 @@ fn test_cases() -> Vec<TestCase> {
         CompareMOp::compare(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
             [
-                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
-                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg_imm(4).value,
+                MOpRegNum::power_isa_gpr_reg_imm(5).value,
             ],
             0.cast_to_static::<SInt<_>>(),
-            #[hdl(sim)]
-            OutputIntegerMode::Full64(),
-            #[hdl(sim)]
-            CompareMode::CmpEqB(),
+            OutputIntegerMode.Full64(),
+            CompareMode.CmpEqB(),
         ),
     ));
     macro_rules! insn_logic_i {
@@ -704,10 +663,7 @@ fn test_cases() -> Vec<TestCase> {
                             &[]
                         },
                     ),
-                    [MOpRegNum::power_isa_gpr_reg(
-                        ($src as u8).cast_to_static::<UInt<_>>().to_expr(),
-                    )
-                    .value],
+                    [MOpRegNum::power_isa_gpr_reg_imm($src).value],
                     (($imm as u32) << if $mnemonic.contains('s') { 16 } else { 0 })
                         .cast_to_static::<SInt<_>>(),
                     OutputIntegerMode.Full64(),
@@ -781,14 +737,8 @@ fn test_cases() -> Vec<TestCase> {
                         },
                     ),
                     [
-                        MOpRegNum::power_isa_gpr_reg(
-                            ($src0 as u8).cast_to_static::<UInt<_>>().to_expr(),
-                        )
-                        .value,
-                        MOpRegNum::power_isa_gpr_reg(
-                            ($src1 as u8).cast_to_static::<UInt<_>>().to_expr(),
-                        )
-                        .value,
+                        MOpRegNum::power_isa_gpr_reg_imm($src0).value,
+                        MOpRegNum::power_isa_gpr_reg_imm($src1).value,
                     ],
                     0.cast_to_static::<SInt<_>>(),
                     OutputIntegerMode.Full64(),
@@ -838,7 +788,7 @@ fn test_cases() -> Vec<TestCase> {
         None,
         MoveRegMOp::move_reg(
             MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
-            [MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value],
+            [MOpRegNum::power_isa_gpr_reg_imm(4).value],
             0.cast_to_static::<SInt<_>>(),
         ),
     ));