working on reg_alloc -- selected_unit_nums should be correct now

crates/cpu/src/reg_alloc.rs

@@ -6,7 +6,11 @@ use crate::{
     unit::{TrapData, UnitTrait},
     util::tree_reduce::tree_reduce_with_state,
 };
-use fayalite::{module::instance_with_loc, prelude::*, util::ready_valid::ReadyValid};
+use fayalite::{
+    module::{instance_with_loc, wire_with_loc},
+    prelude::*,
+    util::ready_valid::ReadyValid,
+};
 use std::num::NonZeroUsize;
 
 pub mod unit_free_regs_tracker;
@@ -73,13 +77,19 @@ pub fn reg_alloc(config: &CpuConfig) {
             selected_unit_nums[fetch_index],
             tree_reduce_with_state(
                 0..config.unit_kinds.len(),
-                &mut (),
+                &mut 0usize,
                 |_state, unit_index| {
-                    #[hdl]
+                    let selected_unit_leaf = wire_with_loc(
-                    let selected_unit_leaf = wire(HdlOption[config.unit_num()]);
+                        &format!("selected_unit_leaf_{fetch_index}_{unit_index}"),
+                        SourceLocation::caller(),
+                        HdlOption[config.unit_num()],
+                    );
                     connect(selected_unit_leaf, HdlOption[config.unit_num()].HdlNone());
-                    #[hdl]
+                    let unit_num = wire_with_loc(
-                    let unit_num = wire(config.unit_num());
+                        &format!("unit_num_{fetch_index}_{unit_index}"),
+                        SourceLocation::caller(),
+                        config.unit_num(),
+                    );
                     connect_any(unit_num.value, unit_index);
                     #[hdl]
                     if available_units[fetch_index][unit_index] {
@@ -87,9 +97,13 @@ pub fn reg_alloc(config: &CpuConfig) {
                     }
                     selected_unit_leaf
                 },
-                |_state, l, r| {
+                |state, l, r| {
-                    #[hdl]
+                    let selected_unit_node = wire_with_loc(
-                    let selected_unit_node = wire(Expr::ty(l));
+                        &format!("selected_unit_node_{fetch_index}_{state}"),
+                        SourceLocation::caller(),
+                        Expr::ty(l),
+                    );
+                    *state += 1;
                     connect(selected_unit_node, l);
                     #[hdl]
                     if let HdlNone = l {
@@ -101,6 +115,19 @@ pub fn reg_alloc(config: &CpuConfig) {
             .expect("expected at least one unit"),
         );
     }
+    // must come after to override connects in loop above
+    for fetch_index in 0..config.fetch_width.get() {
+        // TODO: handle assigning multiple instructions to a unit at a time
+        for later_fetch_index in fetch_index + 1..config.fetch_width.get() {
+            #[hdl]
+            if let HdlSome(selected_unit_num) = selected_unit_nums[fetch_index] {
+                connect(
+                    available_units[later_fetch_index][selected_unit_num.value],
+                    false,
+                );
+            }
+        }
+    }
     for (unit_index, &unit_kind) in config.unit_kinds.iter().enumerate() {
         let dyn_unit = unit_kind.unit(config);
         let unit = instance_with_loc(

crates/cpu/tests/expected/reg_alloc.vcd

@@ -327,26 +327,26 @@ $var string 1 X" unit_kind $end
 $scope struct available_units_for_kind $end
 $var wire 1 Y" \[0] $end
 $upscope $end
-$scope struct selected_unit_leaf $end
+$scope struct selected_unit_leaf_0_0 $end
 $var string 1 Z" \$tag $end
 $scope struct HdlSome $end
 $var wire 1 [" value $end
 $upscope $end
 $upscope $end
-$scope struct unit_num $end
+$scope struct unit_num_0_0 $end
 $var wire 1 \" value $end
 $upscope $end
 $var string 1 ]" unit_kind_2 $end
 $scope struct available_units_for_kind_2 $end
 $var wire 1 ^" \[0] $end
 $upscope $end
-$scope struct selected_unit_leaf_2 $end
+$scope struct selected_unit_leaf_1_0 $end
 $var string 1 _" \$tag $end
 $scope struct HdlSome $end
 $var wire 1 `" value $end
 $upscope $end
 $upscope $end
-$scope struct unit_num_2 $end
+$scope struct unit_num_1_0 $end
 $var wire 1 a" value $end
 $upscope $end
 $scope struct unit_0 $end
@@ -657,10 +657,10 @@ sHdlNone\x20(0) O"
 sTrap\x20(0) P"
 1Q"
 1R"
-1S"
+0S"
 sHdlSome\x20(1) T"
 0U"
-sHdlSome\x20(1) V"
+sHdlNone\x20(0) V"
 0W"
 sAluBranch\x20(0) X"
 1Y"
@@ -669,7 +669,7 @@ sHdlSome\x20(1) Z"
 0\"
 sAluBranch\x20(0) ]"
 1^"
-sHdlSome\x20(1) _"
+sHdlNone\x20(0) _"
 0`"
 0a"
 0b"

crates/cpu/tests/reg_alloc.rs

@@ -11,6 +11,8 @@ use cpu::{
     unit::UnitKind,
 };
 use fayalite::{
+    assert_export_firrtl,
+    firrtl::ExportOptions,
     prelude::*,
     sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
     util::RcWriter,
@@ -23,7 +25,8 @@ fn test_reg_alloc() {
     let _n = SourceLocation::normalize_files_for_tests();
     let mut config = CpuConfig::new(vec![UnitKind::AluBranch]);
     config.fetch_width = NonZeroUsize::new(2).unwrap();
-    let mut sim = Simulation::new(reg_alloc(&config));
+    let m = reg_alloc(&config);
+    let mut sim = Simulation::new(m);
     let mut writer = RcWriter::default();
     sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
     let fetch_decode_interface = sim.io().fetch_decode_interface;
@@ -98,4 +101,487 @@ fn test_reg_alloc() {
     if vcd != include_str!("expected/reg_alloc.vcd") {
         panic!();
     }
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/reg_alloc.fir": r"FIRRTL version 3.2.0
+circuit reg_alloc:
+    type Ty0 = {clk: Clock, rst: Reset}
+    type Ty1 = {}
+    type Ty2 = {prefix_pad: UInt<0>, dest: UInt<8>, src: UInt<8>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty1}
+    type Ty3 = {|Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8|}
+    type Ty4 = {common: Ty2, output_integer_mode: Ty3}
+    type Ty5 = {alu_common: Ty4, invert_src0: UInt<1>, invert_carry_in: UInt<1>, invert_carry_out: UInt<1>, add_pc: UInt<1>}
+    type Ty6 = {alu_common: Ty4, lut: UInt<4>}
+    type Ty7 = {|AddSub: Ty5, AddSubI: Ty5, Logical: Ty6|}
+    type Ty8 = {prefix_pad: UInt<1>, dest: UInt<8>, src: UInt<8>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty1}
+    type Ty9 = {common: Ty8}
+    type Ty10 = {|ReadL2Reg: Ty9, WriteL2Reg: Ty9|}
+    type Ty11 = {|Load: Ty8, Store: Ty8|}
+    type Ty12 = {|AluBranch: Ty7, L2RegisterFile: Ty10, LoadStore: Ty11|}
+    type Ty13 = {uop: Ty12, is_unrelated_pc: UInt<1>, pc: UInt<64>}
+    type Ty14 = {|HdlNone, HdlSome: Ty13|}
+    type Ty15 = {data: Ty14, flip ready: UInt<1>}
+    type Ty16 = {|Trap: Ty1, ICacheFlush|}
+    type Ty17 = {|HdlNone, HdlSome: Ty16|}
+    type Ty18 = {data: Ty17, flip ready: UInt<1>}
+    type Ty19 = {decoded_insns: Ty15[2], flip fetch_decode_special_op: Ty18}
+    type Ty20 = {value: UInt<1>}
+    type Ty21 = {|HdlNone, HdlSome: Ty20|}
+    type Ty22 = {|AluBranch, L2RegisterFile, LoadStore|}
+    type Ty23 = {flip cd: Ty0}
+    type Ty24 = {|HdlNone, HdlSome: UInt<4>|}
+    type Ty25 = {data: Ty24, flip ready: UInt<1>}
+    type Ty26 = {flip cd: Ty0, flip free_in: Ty25[1], alloc_out: Ty25[1]}
+    module reg_alloc: @[reg_alloc.rs 41:1]
+        input cd: Ty0 @[reg_alloc.rs 45:29]
+        input fetch_decode_interface: Ty19 @[reg_alloc.rs 48:11]
+        connect fetch_decode_interface.fetch_decode_special_op.data, {|HdlNone, HdlSome: Ty16|}(HdlNone) @[reg_alloc.rs 50:5]
+        wire available_units: UInt<1>[1][2] @[reg_alloc.rs 57:9]
+        wire selected_unit_nums: Ty21[2] @[reg_alloc.rs 59:30]
+        connect fetch_decode_interface.decoded_insns[0].ready, UInt<1>(0h1) @[reg_alloc.rs 61:9]
+        wire _array_literal_expr: UInt<1>[1]
+        connect _array_literal_expr[0], UInt<1>(0h0)
+        connect available_units[0], _array_literal_expr @[reg_alloc.rs 65:9]
+        match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 70:9]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value):
+                wire unit_kind: Ty22 @[unit.rs 107:1]
+                match _match_arm_value.uop: @[unit.rs 107:1]
+                    AluBranch(_match_arm_value_1):
+                        connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 107:1]
+                    L2RegisterFile(_match_arm_value_2):
+                        connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 107:1]
+                    LoadStore(_match_arm_value_3):
+                        connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 107:1]
+                wire available_units_for_kind: UInt<1>[1] @[unit.rs 107:1]
+                match unit_kind: @[unit.rs 107:1]
+                    AluBranch:
+                        connect available_units_for_kind[0], UInt<1>(0h1) @[unit.rs 107:1]
+                    L2RegisterFile:
+                        connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 107:1]
+                    LoadStore:
+                        connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 107:1]
+                connect available_units[0], available_units_for_kind @[reg_alloc.rs 71:13]
+        wire selected_unit_leaf_0_0: Ty21 @[reg_alloc.rs 84:25]
+        connect selected_unit_leaf_0_0, {|HdlNone, HdlSome: Ty20|}(HdlNone) @[reg_alloc.rs 87:21]
+        wire unit_num_0_0: Ty20 @[reg_alloc.rs 90:25]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<64>
+        connect unit_num_0_0.value, UInt<64>(0h0) @[reg_alloc.rs 93:21]
+        when available_units[0][0]: @[reg_alloc.rs 95:21]
+            connect selected_unit_leaf_0_0, {|HdlNone, HdlSome: Ty20|}(HdlSome, unit_num_0_0) @[reg_alloc.rs 96:25]
+        connect selected_unit_nums[0], selected_unit_leaf_0_0 @[reg_alloc.rs 76:9]
+        connect fetch_decode_interface.decoded_insns[1].ready, UInt<1>(0h1) @[reg_alloc.rs 61:9]
+        wire _array_literal_expr_1: UInt<1>[1]
+        connect _array_literal_expr_1[0], UInt<1>(0h0)
+        connect available_units[1], _array_literal_expr_1 @[reg_alloc.rs 65:9]
+        match fetch_decode_interface.decoded_insns[1].data: @[reg_alloc.rs 70:9]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value_4):
+                wire unit_kind_1: Ty22 @[unit.rs 107:1]
+                match _match_arm_value_4.uop: @[unit.rs 107:1]
+                    AluBranch(_match_arm_value_5):
+                        connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 107:1]
+                    L2RegisterFile(_match_arm_value_6):
+                        connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 107:1]
+                    LoadStore(_match_arm_value_7):
+                        connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 107:1]
+                wire available_units_for_kind_1: UInt<1>[1] @[unit.rs 107:1]
+                match unit_kind_1: @[unit.rs 107:1]
+                    AluBranch:
+                        connect available_units_for_kind_1[0], UInt<1>(0h1) @[unit.rs 107:1]
+                    L2RegisterFile:
+                        connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 107:1]
+                    LoadStore:
+                        connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 107:1]
+                connect available_units[1], available_units_for_kind_1 @[reg_alloc.rs 71:13]
+        wire selected_unit_leaf_1_0: Ty21 @[reg_alloc.rs 84:25]
+        connect selected_unit_leaf_1_0, {|HdlNone, HdlSome: Ty20|}(HdlNone) @[reg_alloc.rs 87:21]
+        wire unit_num_1_0: Ty20 @[reg_alloc.rs 90:25]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<64>
+        connect unit_num_1_0.value, UInt<64>(0h0) @[reg_alloc.rs 93:21]
+        when available_units[1][0]: @[reg_alloc.rs 95:21]
+            connect selected_unit_leaf_1_0, {|HdlNone, HdlSome: Ty20|}(HdlSome, unit_num_1_0) @[reg_alloc.rs 96:25]
+        connect selected_unit_nums[1], selected_unit_leaf_1_0 @[reg_alloc.rs 76:9]
+        match selected_unit_nums[0]: @[reg_alloc.rs 123:13]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value_8):
+                connect available_units[1][_match_arm_value_8.value], UInt<1>(0h0) @[reg_alloc.rs 124:17]
+        inst unit_0 of alu_branch @[reg_alloc.rs 136:13]
+        connect unit_0.cd, cd @[reg_alloc.rs 138:9]
+        inst unit_0_free_regs_tracker of unit_free_regs_tracker @[reg_alloc.rs 150:13]
+        connect unit_0_free_regs_tracker.cd, cd @[reg_alloc.rs 152:9]
+        wire _uninit_expr: Ty24
+        invalidate _uninit_expr
+        connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr @[reg_alloc.rs 154:9]
+        wire _uninit_expr_1: UInt<1>
+        invalidate _uninit_expr_1
+        connect unit_0_free_regs_tracker.alloc_out[0].ready, _uninit_expr_1 @[reg_alloc.rs 158:9]
+    module alu_branch: @[alu_branch.rs 15:1]
+        input cd: Ty0 @[alu_branch.rs 18:29]
+    module unit_free_regs_tracker: @[unit_free_regs_tracker.rs 7:1]
+        input cd: Ty0 @[unit_free_regs_tracker.rs 14:29]
+        input free_in: Ty25[1] @[unit_free_regs_tracker.rs 17:11]
+        output alloc_out: Ty25[1] @[unit_free_regs_tracker.rs 20:11]
+        wire _array_literal_expr: UInt<1>[16]
+        connect _array_literal_expr[0], UInt<1>(0h0)
+        connect _array_literal_expr[1], UInt<1>(0h0)
+        connect _array_literal_expr[2], UInt<1>(0h0)
+        connect _array_literal_expr[3], UInt<1>(0h0)
+        connect _array_literal_expr[4], UInt<1>(0h0)
+        connect _array_literal_expr[5], UInt<1>(0h0)
+        connect _array_literal_expr[6], UInt<1>(0h0)
+        connect _array_literal_expr[7], UInt<1>(0h0)
+        connect _array_literal_expr[8], UInt<1>(0h0)
+        connect _array_literal_expr[9], UInt<1>(0h0)
+        connect _array_literal_expr[10], UInt<1>(0h0)
+        connect _array_literal_expr[11], UInt<1>(0h0)
+        connect _array_literal_expr[12], UInt<1>(0h0)
+        connect _array_literal_expr[13], UInt<1>(0h0)
+        connect _array_literal_expr[14], UInt<1>(0h0)
+        connect _array_literal_expr[15], UInt<1>(0h0)
+        regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25]
+        connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9]
+        wire firing_data: Ty24 @[ready_valid.rs 30:27]
+        connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9]
+        when free_in[0].ready: @[ready_valid.rs 33:9]
+            connect firing_data, free_in[0].data @[ready_valid.rs 34:13]
+        match firing_data: @[unit_free_regs_tracker.rs 31:9]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value):
+                connect allocated_reg[_match_arm_value], UInt<1>(0h0) @[unit_free_regs_tracker.rs 32:13]
+        wire reduced_count_0_2: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_0_2, add(not(allocated_reg[0]), not(allocated_reg[1])) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_0_2: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_0_2, or(or(neq(add(not(allocated_reg[0]), not(allocated_reg[1])), reduced_count_0_2), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_0_2: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(UInt<1>(0h0), gt(not(allocated_reg[0]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            wire _array_literal_expr_1: UInt<0>[1]
+            connect _array_literal_expr_1[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<0>
+            connect reduced_alloc_nums_0_2[0], _array_literal_expr_1[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            wire _array_literal_expr_2: UInt<0>[1]
+            connect _array_literal_expr_2[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_0_2[0], add(_array_literal_expr_2[sub(UInt<64>(0h0), not(allocated_reg[0]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_2_4: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_2_4, add(not(allocated_reg[2]), not(allocated_reg[3])) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_2_4: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_2_4, or(or(neq(add(not(allocated_reg[2]), not(allocated_reg[3])), reduced_count_2_4), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_2_4: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(UInt<1>(0h0), gt(not(allocated_reg[2]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            wire _array_literal_expr_3: UInt<0>[1]
+            connect _array_literal_expr_3[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<0>
+            connect reduced_alloc_nums_2_4[0], _array_literal_expr_3[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            wire _array_literal_expr_4: UInt<0>[1]
+            connect _array_literal_expr_4[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_2_4[0], add(_array_literal_expr_4[sub(UInt<64>(0h0), not(allocated_reg[2]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_0_4: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_0_4, add(reduced_count_0_2, reduced_count_2_4) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_0_4: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_0_4, or(or(neq(add(reduced_count_0_2, reduced_count_2_4), reduced_count_0_4), reduced_count_overflowed_0_2), reduced_count_overflowed_2_4) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_0_4: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(reduced_count_overflowed_0_2, gt(reduced_count_0_2, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            ; connect different types:
+            ; lhs: UInt<2>
+            ; rhs: UInt<1>
+            connect reduced_alloc_nums_0_4[0], reduced_alloc_nums_0_2[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            ; connect different types:
+            ; lhs: UInt<2>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_0_4[0], add(reduced_alloc_nums_2_4[sub(UInt<64>(0h0), reduced_count_0_2)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_4_6: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_4_6, add(not(allocated_reg[4]), not(allocated_reg[5])) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_4_6: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_4_6, or(or(neq(add(not(allocated_reg[4]), not(allocated_reg[5])), reduced_count_4_6), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_4_6: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(UInt<1>(0h0), gt(not(allocated_reg[4]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            wire _array_literal_expr_5: UInt<0>[1]
+            connect _array_literal_expr_5[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<0>
+            connect reduced_alloc_nums_4_6[0], _array_literal_expr_5[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            wire _array_literal_expr_6: UInt<0>[1]
+            connect _array_literal_expr_6[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_4_6[0], add(_array_literal_expr_6[sub(UInt<64>(0h0), not(allocated_reg[4]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_6_8: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_6_8, add(not(allocated_reg[6]), not(allocated_reg[7])) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_6_8: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_6_8, or(or(neq(add(not(allocated_reg[6]), not(allocated_reg[7])), reduced_count_6_8), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_6_8: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(UInt<1>(0h0), gt(not(allocated_reg[6]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            wire _array_literal_expr_7: UInt<0>[1]
+            connect _array_literal_expr_7[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<0>
+            connect reduced_alloc_nums_6_8[0], _array_literal_expr_7[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            wire _array_literal_expr_8: UInt<0>[1]
+            connect _array_literal_expr_8[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_6_8[0], add(_array_literal_expr_8[sub(UInt<64>(0h0), not(allocated_reg[6]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_4_8: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_4_8, add(reduced_count_4_6, reduced_count_6_8) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_4_8: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_4_8, or(or(neq(add(reduced_count_4_6, reduced_count_6_8), reduced_count_4_8), reduced_count_overflowed_4_6), reduced_count_overflowed_6_8) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_4_8: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(reduced_count_overflowed_4_6, gt(reduced_count_4_6, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            ; connect different types:
+            ; lhs: UInt<2>
+            ; rhs: UInt<1>
+            connect reduced_alloc_nums_4_8[0], reduced_alloc_nums_4_6[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            ; connect different types:
+            ; lhs: UInt<2>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_4_8[0], add(reduced_alloc_nums_6_8[sub(UInt<64>(0h0), reduced_count_4_6)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_0_8: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_0_8, add(reduced_count_0_4, reduced_count_4_8) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_0_8: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_0_8, or(or(neq(add(reduced_count_0_4, reduced_count_4_8), reduced_count_0_8), reduced_count_overflowed_0_4), reduced_count_overflowed_4_8) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_0_8: UInt<3>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(reduced_count_overflowed_0_4, gt(reduced_count_0_4, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            ; connect different types:
+            ; lhs: UInt<3>
+            ; rhs: UInt<2>
+            connect reduced_alloc_nums_0_8[0], reduced_alloc_nums_0_4[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            ; connect different types:
+            ; lhs: UInt<3>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_0_8[0], add(reduced_alloc_nums_4_8[sub(UInt<64>(0h0), reduced_count_0_4)], UInt<64>(0h4)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_8_10: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_8_10, add(not(allocated_reg[8]), not(allocated_reg[9])) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_8_10: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_8_10, or(or(neq(add(not(allocated_reg[8]), not(allocated_reg[9])), reduced_count_8_10), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_8_10: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(UInt<1>(0h0), gt(not(allocated_reg[8]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            wire _array_literal_expr_9: UInt<0>[1]
+            connect _array_literal_expr_9[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<0>
+            connect reduced_alloc_nums_8_10[0], _array_literal_expr_9[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            wire _array_literal_expr_10: UInt<0>[1]
+            connect _array_literal_expr_10[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_8_10[0], add(_array_literal_expr_10[sub(UInt<64>(0h0), not(allocated_reg[8]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_10_12: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_10_12, add(not(allocated_reg[10]), not(allocated_reg[11])) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_10_12: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_10_12, or(or(neq(add(not(allocated_reg[10]), not(allocated_reg[11])), reduced_count_10_12), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_10_12: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(UInt<1>(0h0), gt(not(allocated_reg[10]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            wire _array_literal_expr_11: UInt<0>[1]
+            connect _array_literal_expr_11[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<0>
+            connect reduced_alloc_nums_10_12[0], _array_literal_expr_11[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            wire _array_literal_expr_12: UInt<0>[1]
+            connect _array_literal_expr_12[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_10_12[0], add(_array_literal_expr_12[sub(UInt<64>(0h0), not(allocated_reg[10]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_8_12: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_8_12, add(reduced_count_8_10, reduced_count_10_12) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_8_12: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_8_12, or(or(neq(add(reduced_count_8_10, reduced_count_10_12), reduced_count_8_12), reduced_count_overflowed_8_10), reduced_count_overflowed_10_12) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_8_12: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(reduced_count_overflowed_8_10, gt(reduced_count_8_10, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            ; connect different types:
+            ; lhs: UInt<2>
+            ; rhs: UInt<1>
+            connect reduced_alloc_nums_8_12[0], reduced_alloc_nums_8_10[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            ; connect different types:
+            ; lhs: UInt<2>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_8_12[0], add(reduced_alloc_nums_10_12[sub(UInt<64>(0h0), reduced_count_8_10)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_12_14: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_12_14, add(not(allocated_reg[12]), not(allocated_reg[13])) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_12_14: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_12_14, or(or(neq(add(not(allocated_reg[12]), not(allocated_reg[13])), reduced_count_12_14), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_12_14: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(UInt<1>(0h0), gt(not(allocated_reg[12]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            wire _array_literal_expr_13: UInt<0>[1]
+            connect _array_literal_expr_13[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<0>
+            connect reduced_alloc_nums_12_14[0], _array_literal_expr_13[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            wire _array_literal_expr_14: UInt<0>[1]
+            connect _array_literal_expr_14[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_12_14[0], add(_array_literal_expr_14[sub(UInt<64>(0h0), not(allocated_reg[12]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_14_16: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_14_16, add(not(allocated_reg[14]), not(allocated_reg[15])) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_14_16: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_14_16, or(or(neq(add(not(allocated_reg[14]), not(allocated_reg[15])), reduced_count_14_16), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_14_16: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(UInt<1>(0h0), gt(not(allocated_reg[14]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            wire _array_literal_expr_15: UInt<0>[1]
+            connect _array_literal_expr_15[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<0>
+            connect reduced_alloc_nums_14_16[0], _array_literal_expr_15[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            wire _array_literal_expr_16: UInt<0>[1]
+            connect _array_literal_expr_16[0], UInt<0>(0h0)
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_14_16[0], add(_array_literal_expr_16[sub(UInt<64>(0h0), not(allocated_reg[14]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_12_16: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_12_16, add(reduced_count_12_14, reduced_count_14_16) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_12_16: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_12_16, or(or(neq(add(reduced_count_12_14, reduced_count_14_16), reduced_count_12_16), reduced_count_overflowed_12_14), reduced_count_overflowed_14_16) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_12_16: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(reduced_count_overflowed_12_14, gt(reduced_count_12_14, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            ; connect different types:
+            ; lhs: UInt<2>
+            ; rhs: UInt<1>
+            connect reduced_alloc_nums_12_16[0], reduced_alloc_nums_12_14[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            ; connect different types:
+            ; lhs: UInt<2>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_12_16[0], add(reduced_alloc_nums_14_16[sub(UInt<64>(0h0), reduced_count_12_14)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_8_16: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_8_16, add(reduced_count_8_12, reduced_count_12_16) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_8_16: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_8_16, or(or(neq(add(reduced_count_8_12, reduced_count_12_16), reduced_count_8_16), reduced_count_overflowed_8_12), reduced_count_overflowed_12_16) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_8_16: UInt<3>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(reduced_count_overflowed_8_12, gt(reduced_count_8_12, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            ; connect different types:
+            ; lhs: UInt<3>
+            ; rhs: UInt<2>
+            connect reduced_alloc_nums_8_16[0], reduced_alloc_nums_8_12[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            ; connect different types:
+            ; lhs: UInt<3>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_8_16[0], add(reduced_alloc_nums_12_16[sub(UInt<64>(0h0), reduced_count_8_12)], UInt<64>(0h4)) @[unit_free_regs_tracker.rs 83:21]
+        wire reduced_count_0_16: UInt<1> @[unit_free_regs_tracker.rs 60:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<2>
+        connect reduced_count_0_16, add(reduced_count_0_8, reduced_count_8_16) @[unit_free_regs_tracker.rs 63:13]
+        wire reduced_count_overflowed_0_16: UInt<1> @[unit_free_regs_tracker.rs 66:17]
+        connect reduced_count_overflowed_0_16, or(or(neq(add(reduced_count_0_8, reduced_count_8_16), reduced_count_0_16), reduced_count_overflowed_0_8), reduced_count_overflowed_8_16) @[unit_free_regs_tracker.rs 69:13]
+        wire reduced_alloc_nums_0_16: UInt<4>[1] @[unit_free_regs_tracker.rs 75:17]
+        when or(reduced_count_overflowed_0_8, gt(reduced_count_0_8, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17]
+            ; connect different types:
+            ; lhs: UInt<4>
+            ; rhs: UInt<3>
+            connect reduced_alloc_nums_0_16[0], reduced_alloc_nums_0_8[0] @[unit_free_regs_tracker.rs 81:21]
+        else:
+            ; connect different types:
+            ; lhs: UInt<4>
+            ; rhs: UInt<65>
+            connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21]
+        wire firing_data_1: Ty24 @[ready_valid.rs 30:27]
+        connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9]
+        when alloc_out[0].ready: @[ready_valid.rs 33:9]
+            connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13]
+        match firing_data_1: @[unit_free_regs_tracker.rs 102:9]
+            HdlNone:
+                skip
+            HdlSome(_match_arm_value_1):
+                connect allocated_reg[_match_arm_value_1], UInt<1>(0h1) @[unit_free_regs_tracker.rs 103:13]
+        when or(reduced_count_overflowed_0_16, gt(reduced_count_0_16, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 106:9]
+            connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlSome, reduced_alloc_nums_0_16[0]) @[unit_free_regs_tracker.rs 107:13]
+        else:
+            connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[unit_free_regs_tracker.rs 112:13]
+",
+    };
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("expected/reg_alloc.txt") {
+        panic!();
+    }
 }

scripts/check-copyright.sh

@@ -45,7 +45,7 @@ function main()
         */LICENSE.md|*/Notices.txt)
             # copyright file
             ;;
-        /crates/cpu/tests/expected/*.vcd)
+        /crates/cpu/tests/expected/*.vcd|/crates/cpu/tests/expected/*.txt)
             # file that can't contain copyright header
             ;;
         /.forgejo/workflows/*.yml|*/.gitignore|*.toml)