From 5f7766777acd9555bce0957d30d7446f9b0ac261 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 12 Jan 2025 22:11:44 -0800 Subject: [PATCH] working on reg_alloc -- selected_unit_nums should be correct now --- crates/cpu/src/reg_alloc.rs | 45 +- crates/cpu/tests/expected/reg_alloc.txt | 15140 ++++++++++++++++++++++ crates/cpu/tests/expected/reg_alloc.vcd | 14 +- crates/cpu/tests/reg_alloc.rs | 488 +- scripts/check-copyright.sh | 2 +- 5 files changed, 15671 insertions(+), 18 deletions(-) create mode 100644 crates/cpu/tests/expected/reg_alloc.txt diff --git a/crates/cpu/src/reg_alloc.rs b/crates/cpu/src/reg_alloc.rs index 61c5188..de23e45 100644 --- a/crates/cpu/src/reg_alloc.rs +++ b/crates/cpu/src/reg_alloc.rs @@ -6,7 +6,11 @@ use crate::{ unit::{TrapData, UnitTrait}, util::tree_reduce::tree_reduce_with_state, }; -use fayalite::{module::instance_with_loc, prelude::*, util::ready_valid::ReadyValid}; +use fayalite::{ + module::{instance_with_loc, wire_with_loc}, + prelude::*, + util::ready_valid::ReadyValid, +}; use std::num::NonZeroUsize; pub mod unit_free_regs_tracker; @@ -73,13 +77,19 @@ pub fn reg_alloc(config: &CpuConfig) { selected_unit_nums[fetch_index], tree_reduce_with_state( 0..config.unit_kinds.len(), - &mut (), + &mut 0usize, |_state, unit_index| { - #[hdl] - let selected_unit_leaf = wire(HdlOption[config.unit_num()]); + let selected_unit_leaf = wire_with_loc( + &format!("selected_unit_leaf_{fetch_index}_{unit_index}"), + SourceLocation::caller(), + HdlOption[config.unit_num()], + ); connect(selected_unit_leaf, HdlOption[config.unit_num()].HdlNone()); - #[hdl] - let unit_num = wire(config.unit_num()); + let unit_num = wire_with_loc( + &format!("unit_num_{fetch_index}_{unit_index}"), + SourceLocation::caller(), + config.unit_num(), + ); connect_any(unit_num.value, unit_index); #[hdl] if available_units[fetch_index][unit_index] { @@ -87,9 +97,13 @@ pub fn reg_alloc(config: &CpuConfig) { } selected_unit_leaf }, - |_state, l, r| { - #[hdl] - let selected_unit_node = wire(Expr::ty(l)); + |state, l, r| { + let selected_unit_node = wire_with_loc( + &format!("selected_unit_node_{fetch_index}_{state}"), + SourceLocation::caller(), + Expr::ty(l), + ); + *state += 1; connect(selected_unit_node, l); #[hdl] if let HdlNone = l { @@ -101,6 +115,19 @@ pub fn reg_alloc(config: &CpuConfig) { .expect("expected at least one unit"), ); } + // must come after to override connects in loop above + for fetch_index in 0..config.fetch_width.get() { + // TODO: handle assigning multiple instructions to a unit at a time + for later_fetch_index in fetch_index + 1..config.fetch_width.get() { + #[hdl] + if let HdlSome(selected_unit_num) = selected_unit_nums[fetch_index] { + connect( + available_units[later_fetch_index][selected_unit_num.value], + false, + ); + } + } + } for (unit_index, &unit_kind) in config.unit_kinds.iter().enumerate() { let dyn_unit = unit_kind.unit(config); let unit = instance_with_loc( diff --git a/crates/cpu/tests/expected/reg_alloc.txt b/crates/cpu/tests/expected/reg_alloc.txt new file mode 100644 index 0000000..0c3c3f8 --- /dev/null +++ b/crates/cpu/tests/expected/reg_alloc.txt @@ -0,0 +1,15140 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 50, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg, + WriteL2Reg, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Load, + Store, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub, + AddSubI, + Logical, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg, + WriteL2Reg, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Load, + Store, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + Trap, + ICacheFlush, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 685, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].ready", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.ready", + ty: Bool, + }, + SlotDebugData { + name: ".uop", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: ".is_unrelated_pc", + ty: Bool, + }, + SlotDebugData { + name: ".pc", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<135>, + }, + SlotDebugData { + name: "", + ty: UInt<134>, + }, + SlotDebugData { + name: "", + ty: UInt<69>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<69>, + }, + SlotDebugData { + name: "", + ty: UInt<67>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<67>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<61>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<24>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<24>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<24>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: ".uop", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: ".is_unrelated_pc", + ty: Bool, + }, + SlotDebugData { + name: ".pc", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<135>, + }, + SlotDebugData { + name: "", + ty: UInt<134>, + }, + SlotDebugData { + name: "", + ty: UInt<69>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<69>, + }, + SlotDebugData { + name: "", + ty: UInt<67>, + }, + SlotDebugData { + name: "", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".invert_src0", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_in", + ty: Bool, + }, + SlotDebugData { + name: ".invert_carry_out", + ty: Bool, + }, + SlotDebugData { + name: ".add_pc", + ty: Bool, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".common.dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<67>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<61>, + }, + SlotDebugData { + name: "", + ty: UInt<58>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<24>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".alu_common.common.prefix_pad", + ty: UInt<0>, + }, + SlotDebugData { + name: ".alu_common.common.dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".alu_common.common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".alu_common.common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".alu_common.output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + SlotDebugData { + name: ".lut", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + SlotDebugData { + name: ".common.prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".common.dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".common.imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".common.imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<24>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + SlotDebugData { + name: ".prefix_pad", + ty: UInt<1>, + }, + SlotDebugData { + name: ".dest", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".src[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: ".imm_low", + ty: UInt<25>, + }, + SlotDebugData { + name: ".imm_sign", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<60>, + }, + SlotDebugData { + name: "", + ty: UInt<59>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<24>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<25>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: SInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + Trap(Bundle {}), + ICacheFlush, + }, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[0]", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[1]", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + SlotDebugData { + name: ".value", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".value", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + SlotDebugData { + name: ".value", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_0_0.value", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.value", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + SlotDebugData { + name: ".value", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_1_0.value", + ty: UInt<1>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1.value", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[2]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[3]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[4]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[5]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[6]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[7]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[8]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[9]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[10]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[11]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[12]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[13]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[14]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[15]", + ty: Bool, + }, + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "[2]", + ty: Bool, + }, + SlotDebugData { + name: "[3]", + ty: Bool, + }, + SlotDebugData { + name: "[4]", + ty: Bool, + }, + SlotDebugData { + name: "[5]", + ty: Bool, + }, + SlotDebugData { + name: "[6]", + ty: Bool, + }, + SlotDebugData { + name: "[7]", + ty: Bool, + }, + SlotDebugData { + name: "[8]", + ty: Bool, + }, + SlotDebugData { + name: "[9]", + ty: Bool, + }, + SlotDebugData { + name: "[10]", + ty: Bool, + }, + SlotDebugData { + name: "[11]", + ty: Bool, + }, + SlotDebugData { + name: "[12]", + ty: Bool, + }, + SlotDebugData { + name: "[13]", + ty: Bool, + }, + SlotDebugData { + name: "[14]", + ty: Bool, + }, + SlotDebugData { + name: "[15]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "[0]", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_2_4", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_6_8", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_8", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_10_12", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_14_16", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_16", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_16", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_16", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: reg_alloc.rs:41:1 + 0: Const { + dest: StatePartIndex(683), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + 1: Copy { + dest: StatePartIndex(684), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(683), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:158:9 + 2: Copy { + dest: StatePartIndex(332), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + src: StatePartIndex(684), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:152:9 + 3: Copy { + dest: StatePartIndex(327), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, + }, + 4: Copy { + dest: StatePartIndex(328), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.rst", ty: SyncReset }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.rst", ty: SyncReset }, + }, + // at: reg_alloc.rs:150:13 + 5: Copy { + dest: StatePartIndex(340), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].ready", ty: Bool }, + src: StatePartIndex(332), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].ready", ty: Bool }, + }, + 6: Copy { + dest: StatePartIndex(333), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.clk", ty: Clock }, + src: StatePartIndex(327), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.clk", ty: Clock }, + }, + 7: Copy { + dest: StatePartIndex(334), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.rst", ty: SyncReset }, + src: StatePartIndex(328), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.cd.rst", ty: SyncReset }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 8: Const { + dest: StatePartIndex(665), // (0x8) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x8, + }, + 9: NotU { + dest: StatePartIndex(606), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(358), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, + width: 1, + }, + 10: Copy { + dest: StatePartIndex(607), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(606), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 11: CastToUInt { + dest: StatePartIndex(608), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(607), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 12: NotU { + dest: StatePartIndex(603), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(357), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, + width: 1, + }, + 13: Copy { + dest: StatePartIndex(604), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(603), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 14: CastToUInt { + dest: StatePartIndex(605), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(604), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 15: Add { + dest: StatePartIndex(609), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(605), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(608), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(610), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(609), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 17: Copy { + dest: StatePartIndex(602), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, + src: StatePartIndex(610), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 18: CmpNe { + dest: StatePartIndex(612), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(609), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(602), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, + }, + 19: NotU { + dest: StatePartIndex(586), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(356), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, + width: 1, + }, + 20: Copy { + dest: StatePartIndex(587), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(586), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 21: CastToUInt { + dest: StatePartIndex(588), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(587), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 22: NotU { + dest: StatePartIndex(583), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(355), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, + width: 1, + }, + 23: Copy { + dest: StatePartIndex(584), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(583), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 24: CastToUInt { + dest: StatePartIndex(585), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(584), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 25: Add { + dest: StatePartIndex(589), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(585), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(588), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 26: CastToUInt { + dest: StatePartIndex(590), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(589), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 27: Copy { + dest: StatePartIndex(582), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + src: StatePartIndex(590), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 28: Add { + dest: StatePartIndex(623), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(582), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + rhs: StatePartIndex(602), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_14_16", ty: UInt<1> }, + }, + 29: CastToUInt { + dest: StatePartIndex(624), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(623), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 30: Copy { + dest: StatePartIndex(622), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, + src: StatePartIndex(624), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 31: CmpNe { + dest: StatePartIndex(626), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(623), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(622), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, + }, + 32: CmpNe { + dest: StatePartIndex(592), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(589), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(582), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + }, + 33: NotU { + dest: StatePartIndex(551), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(354), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, + width: 1, + }, + 34: Copy { + dest: StatePartIndex(552), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(551), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 35: CastToUInt { + dest: StatePartIndex(553), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(552), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 36: NotU { + dest: StatePartIndex(548), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(353), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, + width: 1, + }, + 37: Copy { + dest: StatePartIndex(549), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(548), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 38: CastToUInt { + dest: StatePartIndex(550), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(549), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 39: Add { + dest: StatePartIndex(554), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(550), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(553), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 40: CastToUInt { + dest: StatePartIndex(555), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(554), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 41: Copy { + dest: StatePartIndex(547), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, + src: StatePartIndex(555), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 42: CmpNe { + dest: StatePartIndex(557), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(554), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(547), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, + }, + 43: NotU { + dest: StatePartIndex(531), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(352), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, + width: 1, + }, + 44: Copy { + dest: StatePartIndex(532), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(531), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 45: CastToUInt { + dest: StatePartIndex(533), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(532), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 46: NotU { + dest: StatePartIndex(528), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(351), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, + width: 1, + }, + 47: Copy { + dest: StatePartIndex(529), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(528), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 48: CastToUInt { + dest: StatePartIndex(530), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(529), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 49: Add { + dest: StatePartIndex(534), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(530), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(533), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 50: CastToUInt { + dest: StatePartIndex(535), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(534), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 51: Copy { + dest: StatePartIndex(527), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + src: StatePartIndex(535), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 52: Add { + dest: StatePartIndex(568), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(527), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + rhs: StatePartIndex(547), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_10_12", ty: UInt<1> }, + }, + 53: CastToUInt { + dest: StatePartIndex(569), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(568), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 54: Copy { + dest: StatePartIndex(567), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + src: StatePartIndex(569), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 55: Add { + dest: StatePartIndex(638), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(567), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + rhs: StatePartIndex(622), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_16", ty: UInt<1> }, + }, + 56: CastToUInt { + dest: StatePartIndex(639), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(638), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 57: Copy { + dest: StatePartIndex(637), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, + src: StatePartIndex(639), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 58: CmpNe { + dest: StatePartIndex(641), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(638), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(637), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, + }, + 59: CmpNe { + dest: StatePartIndex(571), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(568), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(567), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + }, + 60: CmpNe { + dest: StatePartIndex(537), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(534), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(527), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + }, + 61: Const { + dest: StatePartIndex(524), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 62: NotU { + dest: StatePartIndex(480), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(350), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, + width: 1, + }, + 63: Copy { + dest: StatePartIndex(481), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(480), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 64: CastToUInt { + dest: StatePartIndex(482), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(481), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 65: NotU { + dest: StatePartIndex(477), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(349), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, + width: 1, + }, + 66: Copy { + dest: StatePartIndex(478), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(477), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 67: CastToUInt { + dest: StatePartIndex(479), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(478), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 68: Add { + dest: StatePartIndex(483), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(479), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(482), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 69: CastToUInt { + dest: StatePartIndex(484), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(483), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 70: Copy { + dest: StatePartIndex(476), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, + src: StatePartIndex(484), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 71: CmpNe { + dest: StatePartIndex(486), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(483), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(476), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, + }, + 72: NotU { + dest: StatePartIndex(460), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(348), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, + width: 1, + }, + 73: Copy { + dest: StatePartIndex(461), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(460), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 74: CastToUInt { + dest: StatePartIndex(462), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(461), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 75: NotU { + dest: StatePartIndex(457), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(347), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, + width: 1, + }, + 76: Copy { + dest: StatePartIndex(458), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(457), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 77: CastToUInt { + dest: StatePartIndex(459), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(458), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 78: Add { + dest: StatePartIndex(463), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(459), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(462), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 79: CastToUInt { + dest: StatePartIndex(464), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(463), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 80: Copy { + dest: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + src: StatePartIndex(464), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 81: Add { + dest: StatePartIndex(497), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + rhs: StatePartIndex(476), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_6_8", ty: UInt<1> }, + }, + 82: CastToUInt { + dest: StatePartIndex(498), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(497), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 83: Copy { + dest: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, + src: StatePartIndex(498), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 84: CmpNe { + dest: StatePartIndex(500), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(497), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, + }, + 85: CmpNe { + dest: StatePartIndex(466), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(463), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + }, + 86: Const { + dest: StatePartIndex(453), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 87: NotU { + dest: StatePartIndex(424), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(346), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, + width: 1, + }, + 88: Copy { + dest: StatePartIndex(425), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(424), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 89: CastToUInt { + dest: StatePartIndex(426), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(425), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 90: NotU { + dest: StatePartIndex(421), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(345), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, + width: 1, + }, + 91: Copy { + dest: StatePartIndex(422), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(421), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 92: CastToUInt { + dest: StatePartIndex(423), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(422), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 93: Add { + dest: StatePartIndex(427), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(423), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(426), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 94: CastToUInt { + dest: StatePartIndex(428), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(427), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 95: Copy { + dest: StatePartIndex(420), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, + src: StatePartIndex(428), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 96: CmpNe { + dest: StatePartIndex(430), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(427), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(420), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, + }, + 97: Const { + dest: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 98: Const { + dest: StatePartIndex(413), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 99: Copy { + dest: StatePartIndex(412), // (0x0) SlotDebugData { name: "[0]", ty: UInt<0> }, + src: StatePartIndex(413), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 100: CastToUInt { + dest: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(412), // (0x0) SlotDebugData { name: "[0]", ty: UInt<0> }, + dest_width: 1, + }, + 101: NotU { + dest: StatePartIndex(400), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(344), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, + width: 1, + }, + 102: Copy { + dest: StatePartIndex(401), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(400), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 103: CastToUInt { + dest: StatePartIndex(402), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(401), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 104: NotU { + dest: StatePartIndex(397), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(343), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, + width: 1, + }, + 105: Copy { + dest: StatePartIndex(398), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(397), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 106: CastToUInt { + dest: StatePartIndex(399), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(398), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 107: Add { + dest: StatePartIndex(403), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(399), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(402), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 108: CastToUInt { + dest: StatePartIndex(404), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(403), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 109: Copy { + dest: StatePartIndex(396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + src: StatePartIndex(404), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 110: Add { + dest: StatePartIndex(441), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + rhs: StatePartIndex(420), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_2_4", ty: UInt<1> }, + }, + 111: CastToUInt { + dest: StatePartIndex(442), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(441), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 112: Copy { + dest: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + src: StatePartIndex(442), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 113: Add { + dest: StatePartIndex(512), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + rhs: StatePartIndex(496), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_8", ty: UInt<1> }, + }, + 114: CastToUInt { + dest: StatePartIndex(513), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(512), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 115: Copy { + dest: StatePartIndex(511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + src: StatePartIndex(513), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 116: Add { + dest: StatePartIndex(653), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + rhs: StatePartIndex(637), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_16", ty: UInt<1> }, + }, + 117: CastToUInt { + dest: StatePartIndex(654), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(653), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: unit_free_regs_tracker.rs:63:13 + 118: Copy { + dest: StatePartIndex(652), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, + src: StatePartIndex(654), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 119: CmpNe { + dest: StatePartIndex(656), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(653), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(652), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, + }, + 120: CmpNe { + dest: StatePartIndex(515), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(512), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + }, + 121: CmpNe { + dest: StatePartIndex(444), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(441), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + }, + 122: CmpNe { + dest: StatePartIndex(406), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(403), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + }, + 123: Const { + dest: StatePartIndex(394), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + value: 0x0, + }, + 124: Copy { + dest: StatePartIndex(395), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(394), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + // at: ready_valid.rs:31:9 + 125: Copy { + dest: StatePartIndex(391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(395), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 126: Copy { + dest: StatePartIndex(668), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(395), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: reg_alloc.rs:154:9 + 127: Copy { + dest: StatePartIndex(329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(395), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: reg_alloc.rs:150:13 + 128: Copy { + dest: StatePartIndex(335), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 129: AndBigWithSmallImmediate { + dest: StatePartIndex(48), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 130: Copy { + dest: StatePartIndex(679), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(329), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 131: SliceInt { + dest: StatePartIndex(680), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(679), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + // at: unit_free_regs_tracker.rs:27:25 + 132: IsNonZeroDestIsSmall { + dest: StatePartIndex(28), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(334), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.rst", ty: SyncReset }, + }, + 133: IsNonZeroDestIsSmall { + dest: StatePartIndex(27), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(333), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::cd.clk", ty: Clock }, + }, + 134: AndSmall { + dest: StatePartIndex(26), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(27), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(25), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 135: Copy { + dest: StatePartIndex(337), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(335), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 136: SliceInt { + dest: StatePartIndex(338), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(337), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + // at: unit_free_regs_tracker.rs:17:11 + 137: AndBigWithSmallImmediate { + dest: StatePartIndex(23), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(335), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:138:9 + 138: Copy { + dest: StatePartIndex(323), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", ty: Clock }, + }, + 139: Copy { + dest: StatePartIndex(324), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.rst", ty: SyncReset }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.rst", ty: SyncReset }, + }, + // at: reg_alloc.rs:136:13 + 140: Copy { + dest: StatePartIndex(325), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::cd.clk", ty: Clock }, + src: StatePartIndex(323), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.clk", ty: Clock }, + }, + 141: Copy { + dest: StatePartIndex(326), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0: alu_branch).alu_branch::cd.rst", ty: SyncReset }, + src: StatePartIndex(324), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0.cd.rst", ty: SyncReset }, + }, + // at: reg_alloc.rs:41:1 + 142: Const { + dest: StatePartIndex(304), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 143: Const { + dest: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 144: CastToUInt { + dest: StatePartIndex(301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + // at: reg_alloc.rs:93:21 + 145: Copy { + dest: StatePartIndex(299), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_0_0.value", ty: UInt<1> }, + src: StatePartIndex(301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:41:1 + 146: Copy { + dest: StatePartIndex(302), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(304), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 147: Copy { + dest: StatePartIndex(303), // (0x0) SlotDebugData { name: ".1.value", ty: UInt<1> }, + src: StatePartIndex(299), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_0_0.value", ty: UInt<1> }, + }, + 148: Shl { + dest: StatePartIndex(305), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(303), // (0x0) SlotDebugData { name: ".1.value", ty: UInt<1> }, + rhs: 1, + }, + 149: Or { + dest: StatePartIndex(306), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(302), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(305), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 150: CastToUInt { + dest: StatePartIndex(307), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(306), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 2, + }, + 151: Copy { + dest: StatePartIndex(308), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + src: StatePartIndex(307), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: reg_alloc.rs:93:21 + 152: Copy { + dest: StatePartIndex(316), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_1_0.value", ty: UInt<1> }, + src: StatePartIndex(301), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:41:1 + 153: Copy { + dest: StatePartIndex(317), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(304), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 154: Copy { + dest: StatePartIndex(318), // (0x0) SlotDebugData { name: ".1.value", ty: UInt<1> }, + src: StatePartIndex(316), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_num_1_0.value", ty: UInt<1> }, + }, + 155: Shl { + dest: StatePartIndex(319), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(318), // (0x0) SlotDebugData { name: ".1.value", ty: UInt<1> }, + rhs: 1, + }, + 156: Or { + dest: StatePartIndex(320), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(317), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(319), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 157: CastToUInt { + dest: StatePartIndex(321), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(320), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 2, + }, + 158: Copy { + dest: StatePartIndex(322), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + src: StatePartIndex(321), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 159: CmpLt { + dest: StatePartIndex(410), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(399), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 160: SubU { + dest: StatePartIndex(415), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(399), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 161: CastBigToArrayIndex { + dest: StatePartIndex(31), // (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(415), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + }, + 162: ReadIndexed { + dest: StatePartIndex(416), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(31) /* (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 163: Add { + dest: StatePartIndex(418), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(416), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 164: CastToUInt { + dest: StatePartIndex(419), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(418), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 165: CmpLt { + dest: StatePartIndex(434), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(423), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 166: SubU { + dest: StatePartIndex(436), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(423), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 167: CastBigToArrayIndex { + dest: StatePartIndex(32), // (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(436), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + }, + 168: ReadIndexed { + dest: StatePartIndex(437), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(32) /* (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 169: Add { + dest: StatePartIndex(438), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(437), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 170: CastToUInt { + dest: StatePartIndex(439), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(438), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 171: CmpLt { + dest: StatePartIndex(448), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + }, + 172: SubU { + dest: StatePartIndex(451), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(396), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_2", ty: UInt<1> }, + dest_width: 65, + }, + 173: CastBigToArrayIndex { + dest: StatePartIndex(33), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(451), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 174: CmpLt { + dest: StatePartIndex(470), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(459), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 175: SubU { + dest: StatePartIndex(472), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(459), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 176: CastBigToArrayIndex { + dest: StatePartIndex(34), // (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(472), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + }, + 177: ReadIndexed { + dest: StatePartIndex(473), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(34) /* (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 178: Add { + dest: StatePartIndex(474), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(473), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 179: CastToUInt { + dest: StatePartIndex(475), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(474), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 180: CmpLt { + dest: StatePartIndex(490), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(479), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 181: SubU { + dest: StatePartIndex(492), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(479), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 182: CastBigToArrayIndex { + dest: StatePartIndex(35), // (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(492), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + }, + 183: ReadIndexed { + dest: StatePartIndex(493), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(35) /* (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 184: Add { + dest: StatePartIndex(494), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(493), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 185: CastToUInt { + dest: StatePartIndex(495), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(494), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 186: CmpLt { + dest: StatePartIndex(504), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + }, + 187: SubU { + dest: StatePartIndex(507), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(456), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_4_6", ty: UInt<1> }, + dest_width: 65, + }, + 188: CastBigToArrayIndex { + dest: StatePartIndex(36), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(507), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 189: CmpLt { + dest: StatePartIndex(519), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + }, + 190: SubU { + dest: StatePartIndex(522), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(440), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_4", ty: UInt<1> }, + dest_width: 65, + }, + 191: CastBigToArrayIndex { + dest: StatePartIndex(37), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(522), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 192: CmpLt { + dest: StatePartIndex(541), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(530), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 193: SubU { + dest: StatePartIndex(543), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(530), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 194: CastBigToArrayIndex { + dest: StatePartIndex(38), // (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(543), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + }, + 195: ReadIndexed { + dest: StatePartIndex(544), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(38) /* (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 196: Add { + dest: StatePartIndex(545), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(544), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 197: CastToUInt { + dest: StatePartIndex(546), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(545), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 198: CmpLt { + dest: StatePartIndex(561), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(550), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 199: SubU { + dest: StatePartIndex(563), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(550), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 200: CastBigToArrayIndex { + dest: StatePartIndex(39), // (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(563), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + }, + 201: ReadIndexed { + dest: StatePartIndex(564), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(39) /* (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 202: Add { + dest: StatePartIndex(565), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(564), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 203: CastToUInt { + dest: StatePartIndex(566), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(565), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 204: CmpLt { + dest: StatePartIndex(575), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(527), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + }, + 205: SubU { + dest: StatePartIndex(578), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(527), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_10", ty: UInt<1> }, + dest_width: 65, + }, + 206: CastBigToArrayIndex { + dest: StatePartIndex(40), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(578), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 207: CmpLt { + dest: StatePartIndex(596), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(585), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 208: SubU { + dest: StatePartIndex(598), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(585), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 209: CastBigToArrayIndex { + dest: StatePartIndex(41), // (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(598), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + }, + 210: ReadIndexed { + dest: StatePartIndex(599), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(41) /* (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 211: Add { + dest: StatePartIndex(600), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(599), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 212: CastToUInt { + dest: StatePartIndex(601), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(600), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 213: CmpLt { + dest: StatePartIndex(616), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(605), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 214: SubU { + dest: StatePartIndex(618), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(605), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 65, + }, + 215: CastBigToArrayIndex { + dest: StatePartIndex(42), // (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(618), // (0x1ffffffffffffffff) SlotDebugData { name: "", ty: UInt<65> }, + }, + 216: ReadIndexed { + dest: StatePartIndex(619), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(412) /* (0x0) SlotDebugData { name: "[0]", ty: UInt<0> } */ [StatePartIndex(42) /* (0xffffffffffffffff -1) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 217: Add { + dest: StatePartIndex(620), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(619), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + rhs: StatePartIndex(417), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 218: CastToUInt { + dest: StatePartIndex(621), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(620), // (0x1) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 1, + }, + 219: CmpLt { + dest: StatePartIndex(630), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(582), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + }, + 220: SubU { + dest: StatePartIndex(633), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(582), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_12_14", ty: UInt<1> }, + dest_width: 65, + }, + 221: CastBigToArrayIndex { + dest: StatePartIndex(43), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(633), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 222: CmpLt { + dest: StatePartIndex(645), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(567), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + }, + 223: SubU { + dest: StatePartIndex(648), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(567), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_8_12", ty: UInt<1> }, + dest_width: 65, + }, + 224: CastBigToArrayIndex { + dest: StatePartIndex(44), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(648), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 225: CmpLt { + dest: StatePartIndex(660), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + }, + 226: SubU { + dest: StatePartIndex(663), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(511), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_8", ty: UInt<1> }, + dest_width: 65, + }, + 227: CastBigToArrayIndex { + dest: StatePartIndex(45), // (0x0 0) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(663), // (0x0) SlotDebugData { name: "", ty: UInt<65> }, + }, + 228: CmpLt { + dest: StatePartIndex(671), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(300), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + rhs: StatePartIndex(652), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_0_16", ty: UInt<1> }, + }, + // at: reg_alloc.rs:41:1 + 229: Const { + dest: StatePartIndex(290), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x2, + }, + 230: Copy { + dest: StatePartIndex(291), // (0x2) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(290), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 231: Const { + dest: StatePartIndex(288), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x1, + }, + 232: Copy { + dest: StatePartIndex(289), // (0x1) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(288), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 233: Const { + dest: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + 234: Copy { + dest: StatePartIndex(284), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:65:9 + 235: Copy { + dest: StatePartIndex(271), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, + src: StatePartIndex(284), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + }, + 236: Copy { + dest: StatePartIndex(272), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, + src: StatePartIndex(284), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 237: Copy { + dest: StatePartIndex(375), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 238: Copy { + dest: StatePartIndex(376), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 239: Copy { + dest: StatePartIndex(377), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 240: Copy { + dest: StatePartIndex(378), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 241: Copy { + dest: StatePartIndex(379), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 242: Copy { + dest: StatePartIndex(380), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 243: Copy { + dest: StatePartIndex(381), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 244: Copy { + dest: StatePartIndex(382), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 245: Copy { + dest: StatePartIndex(383), // (0x0) SlotDebugData { name: "[8]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 246: Copy { + dest: StatePartIndex(384), // (0x0) SlotDebugData { name: "[9]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 247: Copy { + dest: StatePartIndex(385), // (0x0) SlotDebugData { name: "[10]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 248: Copy { + dest: StatePartIndex(386), // (0x0) SlotDebugData { name: "[11]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 249: Copy { + dest: StatePartIndex(387), // (0x0) SlotDebugData { name: "[12]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 250: Copy { + dest: StatePartIndex(388), // (0x0) SlotDebugData { name: "[13]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 251: Copy { + dest: StatePartIndex(389), // (0x0) SlotDebugData { name: "[14]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 252: Copy { + dest: StatePartIndex(390), // (0x0) SlotDebugData { name: "[15]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 253: Or { + dest: StatePartIndex(407), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(406), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 254: Or { + dest: StatePartIndex(408), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(407), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 255: Copy { + dest: StatePartIndex(405), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, + src: StatePartIndex(408), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 256: Or { + dest: StatePartIndex(445), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(444), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(405), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, + }, + 257: Or { + dest: StatePartIndex(449), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(405), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_2", ty: Bool }, + rhs: StatePartIndex(448), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 258: Or { + dest: StatePartIndex(411), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(410), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 259: BranchIfZero { + target: 261, + value: StatePartIndex(411), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 260: Copy { + dest: StatePartIndex(409), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, + src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 261: BranchIfNonZero { + target: 263, + value: StatePartIndex(411), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 262: Copy { + dest: StatePartIndex(409), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, + src: StatePartIndex(419), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 263: CastToUInt { + dest: StatePartIndex(450), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(409), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_2[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 264: BranchIfZero { + target: 266, + value: StatePartIndex(449), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 265: Copy { + dest: StatePartIndex(447), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, + src: StatePartIndex(450), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 266: Or { + dest: StatePartIndex(431), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(430), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 267: Or { + dest: StatePartIndex(432), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(431), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 268: Copy { + dest: StatePartIndex(429), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_2_4", ty: Bool }, + src: StatePartIndex(432), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 269: Or { + dest: StatePartIndex(446), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(445), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(429), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_2_4", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 270: Copy { + dest: StatePartIndex(443), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, + src: StatePartIndex(446), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 271: Or { + dest: StatePartIndex(516), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(515), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(443), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, + }, + 272: Or { + dest: StatePartIndex(520), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(443), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_4", ty: Bool }, + rhs: StatePartIndex(519), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 273: Or { + dest: StatePartIndex(435), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(434), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 274: BranchIfZero { + target: 276, + value: StatePartIndex(435), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 275: Copy { + dest: StatePartIndex(433), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> }, + src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 276: BranchIfNonZero { + target: 278, + value: StatePartIndex(435), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 277: Copy { + dest: StatePartIndex(433), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> }, + src: StatePartIndex(439), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 278: ReadIndexed { + dest: StatePartIndex(452), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(433) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_2_4[0]", ty: UInt<1> } */ [StatePartIndex(33) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 279: Add { + dest: StatePartIndex(454), // (0x2) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(452), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(453), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 280: CastToUInt { + dest: StatePartIndex(455), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(454), // (0x2) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 281: BranchIfNonZero { + target: 283, + value: StatePartIndex(449), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 282: Copy { + dest: StatePartIndex(447), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, + src: StatePartIndex(455), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 283: CastToUInt { + dest: StatePartIndex(521), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(447), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_4[0]", ty: UInt<2> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 284: BranchIfZero { + target: 286, + value: StatePartIndex(520), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 285: Copy { + dest: StatePartIndex(518), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, + src: StatePartIndex(521), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 286: Or { + dest: StatePartIndex(467), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(466), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 287: Or { + dest: StatePartIndex(468), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(467), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 288: Copy { + dest: StatePartIndex(465), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, + src: StatePartIndex(468), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 289: Or { + dest: StatePartIndex(501), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(500), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(465), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, + }, + 290: Or { + dest: StatePartIndex(505), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(465), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_6", ty: Bool }, + rhs: StatePartIndex(504), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 291: Or { + dest: StatePartIndex(471), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(470), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 292: BranchIfZero { + target: 294, + value: StatePartIndex(471), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 293: Copy { + dest: StatePartIndex(469), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, + src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 294: BranchIfNonZero { + target: 296, + value: StatePartIndex(471), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 295: Copy { + dest: StatePartIndex(469), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, + src: StatePartIndex(475), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 296: CastToUInt { + dest: StatePartIndex(506), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(469), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_6[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 297: BranchIfZero { + target: 299, + value: StatePartIndex(505), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 298: Copy { + dest: StatePartIndex(503), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> }, + src: StatePartIndex(506), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 299: Or { + dest: StatePartIndex(487), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(486), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 300: Or { + dest: StatePartIndex(488), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(487), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 301: Copy { + dest: StatePartIndex(485), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_6_8", ty: Bool }, + src: StatePartIndex(488), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 302: Or { + dest: StatePartIndex(502), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(501), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(485), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_6_8", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 303: Copy { + dest: StatePartIndex(499), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_8", ty: Bool }, + src: StatePartIndex(502), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 304: Or { + dest: StatePartIndex(517), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(516), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(499), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_4_8", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 305: Copy { + dest: StatePartIndex(514), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, + src: StatePartIndex(517), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 306: Or { + dest: StatePartIndex(657), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(656), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(514), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, + }, + 307: Or { + dest: StatePartIndex(661), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(514), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_8", ty: Bool }, + rhs: StatePartIndex(660), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 308: Or { + dest: StatePartIndex(491), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(490), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 309: BranchIfZero { + target: 311, + value: StatePartIndex(491), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 310: Copy { + dest: StatePartIndex(489), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> }, + src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 311: BranchIfNonZero { + target: 313, + value: StatePartIndex(491), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 312: Copy { + dest: StatePartIndex(489), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> }, + src: StatePartIndex(495), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 313: ReadIndexed { + dest: StatePartIndex(508), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(489) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_6_8[0]", ty: UInt<1> } */ [StatePartIndex(36) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 314: Add { + dest: StatePartIndex(509), // (0x2) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(508), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(453), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 315: CastToUInt { + dest: StatePartIndex(510), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(509), // (0x2) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 316: BranchIfNonZero { + target: 318, + value: StatePartIndex(505), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 317: Copy { + dest: StatePartIndex(503), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> }, + src: StatePartIndex(510), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 318: ReadIndexed { + dest: StatePartIndex(523), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(503) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_4_8[0]", ty: UInt<2> } */ [StatePartIndex(37) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 319: Add { + dest: StatePartIndex(525), // (0x4) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(523), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(524), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + }, + 320: CastToUInt { + dest: StatePartIndex(526), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(525), // (0x4) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 321: BranchIfNonZero { + target: 323, + value: StatePartIndex(520), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 322: Copy { + dest: StatePartIndex(518), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, + src: StatePartIndex(526), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 323: CastToUInt { + dest: StatePartIndex(662), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(518), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_8[0]", ty: UInt<3> }, + dest_width: 4, + }, + // at: unit_free_regs_tracker.rs:80:17 + 324: BranchIfZero { + target: 326, + value: StatePartIndex(661), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 325: Copy { + dest: StatePartIndex(659), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, + src: StatePartIndex(662), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 326: Or { + dest: StatePartIndex(538), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(537), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 327: Or { + dest: StatePartIndex(539), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(538), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 328: Copy { + dest: StatePartIndex(536), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, + src: StatePartIndex(539), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 329: Or { + dest: StatePartIndex(572), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(571), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(536), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, + }, + 330: Or { + dest: StatePartIndex(576), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(536), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_10", ty: Bool }, + rhs: StatePartIndex(575), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 331: Or { + dest: StatePartIndex(542), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(541), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 332: BranchIfZero { + target: 334, + value: StatePartIndex(542), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 333: Copy { + dest: StatePartIndex(540), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, + src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 334: BranchIfNonZero { + target: 336, + value: StatePartIndex(542), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 335: Copy { + dest: StatePartIndex(540), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, + src: StatePartIndex(546), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 336: CastToUInt { + dest: StatePartIndex(577), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(540), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_10[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 337: BranchIfZero { + target: 339, + value: StatePartIndex(576), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 338: Copy { + dest: StatePartIndex(574), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, + src: StatePartIndex(577), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 339: Or { + dest: StatePartIndex(558), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(557), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 340: Or { + dest: StatePartIndex(559), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(558), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 341: Copy { + dest: StatePartIndex(556), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_10_12", ty: Bool }, + src: StatePartIndex(559), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 342: Or { + dest: StatePartIndex(573), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(572), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(556), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_10_12", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 343: Copy { + dest: StatePartIndex(570), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, + src: StatePartIndex(573), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 344: Or { + dest: StatePartIndex(642), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(641), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(570), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, + }, + 345: Or { + dest: StatePartIndex(646), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(570), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_12", ty: Bool }, + rhs: StatePartIndex(645), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 346: Or { + dest: StatePartIndex(562), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(561), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 347: BranchIfZero { + target: 349, + value: StatePartIndex(562), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 348: Copy { + dest: StatePartIndex(560), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> }, + src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 349: BranchIfNonZero { + target: 351, + value: StatePartIndex(562), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 350: Copy { + dest: StatePartIndex(560), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> }, + src: StatePartIndex(566), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 351: ReadIndexed { + dest: StatePartIndex(579), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(560) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_10_12[0]", ty: UInt<1> } */ [StatePartIndex(40) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 352: Add { + dest: StatePartIndex(580), // (0x2) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(579), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(453), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 353: CastToUInt { + dest: StatePartIndex(581), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(580), // (0x2) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 354: BranchIfNonZero { + target: 356, + value: StatePartIndex(576), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 355: Copy { + dest: StatePartIndex(574), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, + src: StatePartIndex(581), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 356: CastToUInt { + dest: StatePartIndex(647), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(574), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_12[0]", ty: UInt<2> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 357: BranchIfZero { + target: 359, + value: StatePartIndex(646), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 358: Copy { + dest: StatePartIndex(644), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> }, + src: StatePartIndex(647), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 359: Or { + dest: StatePartIndex(593), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(592), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 360: Or { + dest: StatePartIndex(594), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(593), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 361: Copy { + dest: StatePartIndex(591), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, + src: StatePartIndex(594), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 362: Or { + dest: StatePartIndex(627), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(626), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(591), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, + }, + 363: Or { + dest: StatePartIndex(631), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(591), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_14", ty: Bool }, + rhs: StatePartIndex(630), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 364: Or { + dest: StatePartIndex(597), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(596), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 365: BranchIfZero { + target: 367, + value: StatePartIndex(597), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 366: Copy { + dest: StatePartIndex(595), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, + src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 367: BranchIfNonZero { + target: 369, + value: StatePartIndex(597), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 368: Copy { + dest: StatePartIndex(595), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, + src: StatePartIndex(601), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 369: CastToUInt { + dest: StatePartIndex(632), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(595), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_14[0]", ty: UInt<1> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 370: BranchIfZero { + target: 372, + value: StatePartIndex(631), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 371: Copy { + dest: StatePartIndex(629), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> }, + src: StatePartIndex(632), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 372: Or { + dest: StatePartIndex(613), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(612), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 373: Or { + dest: StatePartIndex(614), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(613), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 374: Copy { + dest: StatePartIndex(611), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_14_16", ty: Bool }, + src: StatePartIndex(614), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 375: Or { + dest: StatePartIndex(628), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(627), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(611), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_14_16", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 376: Copy { + dest: StatePartIndex(625), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_16", ty: Bool }, + src: StatePartIndex(628), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 377: Or { + dest: StatePartIndex(643), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(642), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(625), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_12_16", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 378: Copy { + dest: StatePartIndex(640), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_16", ty: Bool }, + src: StatePartIndex(643), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 379: Or { + dest: StatePartIndex(658), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(657), // (0x1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(640), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_8_16", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:69:13 + 380: Copy { + dest: StatePartIndex(655), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_16", ty: Bool }, + src: StatePartIndex(658), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 381: Or { + dest: StatePartIndex(672), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(655), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_count_overflowed_0_16", ty: Bool }, + rhs: StatePartIndex(671), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 382: Or { + dest: StatePartIndex(617), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(616), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 383: BranchIfZero { + target: 385, + value: StatePartIndex(617), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:81:21 + 384: Copy { + dest: StatePartIndex(615), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> }, + src: StatePartIndex(414), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:80:17 + 385: BranchIfNonZero { + target: 387, + value: StatePartIndex(617), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 386: Copy { + dest: StatePartIndex(615), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> }, + src: StatePartIndex(621), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 387: ReadIndexed { + dest: StatePartIndex(634), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(615) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_14_16[0]", ty: UInt<1> } */ [StatePartIndex(43) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 388: Add { + dest: StatePartIndex(635), // (0x2) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(634), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: StatePartIndex(453), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 389: CastToUInt { + dest: StatePartIndex(636), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(635), // (0x2) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 2, + }, + // at: unit_free_regs_tracker.rs:80:17 + 390: BranchIfNonZero { + target: 392, + value: StatePartIndex(631), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 391: Copy { + dest: StatePartIndex(629), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> }, + src: StatePartIndex(636), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 392: ReadIndexed { + dest: StatePartIndex(649), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(629) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_12_16[0]", ty: UInt<2> } */ [StatePartIndex(44) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 393: Add { + dest: StatePartIndex(650), // (0x4) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(649), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + rhs: StatePartIndex(524), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + }, + 394: CastToUInt { + dest: StatePartIndex(651), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(650), // (0x4) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 3, + }, + // at: unit_free_regs_tracker.rs:80:17 + 395: BranchIfNonZero { + target: 397, + value: StatePartIndex(646), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 396: Copy { + dest: StatePartIndex(644), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> }, + src: StatePartIndex(651), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 397: ReadIndexed { + dest: StatePartIndex(664), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(644) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_8_16[0]", ty: UInt<3> } */ [StatePartIndex(45) /* (0x0 0) SlotDebugData { name: "", ty: UInt<64> } */ , len=1, stride=1],, + }, + 398: Add { + dest: StatePartIndex(666), // (0x8) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(664), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + rhs: StatePartIndex(665), // (0x8) SlotDebugData { name: "", ty: UInt<64> }, + }, + 399: CastToUInt { + dest: StatePartIndex(667), // (0x8) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(666), // (0x8) SlotDebugData { name: "", ty: UInt<65> }, + dest_width: 4, + }, + // at: unit_free_regs_tracker.rs:80:17 + 400: BranchIfNonZero { + target: 402, + value: StatePartIndex(661), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:83:21 + 401: Copy { + dest: StatePartIndex(659), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, + src: StatePartIndex(667), // (0x8) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit_free_regs_tracker.rs:7:1 + 402: Copy { + dest: StatePartIndex(673), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(304), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 403: Copy { + dest: StatePartIndex(674), // (0x0) SlotDebugData { name: ".1", ty: UInt<4> }, + src: StatePartIndex(659), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::reduced_alloc_nums_0_16[0]", ty: UInt<4> }, + }, + 404: Shl { + dest: StatePartIndex(675), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(674), // (0x0) SlotDebugData { name: ".1", ty: UInt<4> }, + rhs: 1, + }, + 405: Or { + dest: StatePartIndex(676), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(673), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(675), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + }, + 406: CastToUInt { + dest: StatePartIndex(677), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(676), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + dest_width: 5, + }, + 407: Copy { + dest: StatePartIndex(678), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(677), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + }, + // at: unit_free_regs_tracker.rs:106:9 + 408: BranchIfZero { + target: 410, + value: StatePartIndex(672), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:107:13 + 409: Copy { + dest: StatePartIndex(339), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(678), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: unit_free_regs_tracker.rs:106:9 + 410: BranchIfNonZero { + target: 412, + value: StatePartIndex(672), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:112:13 + 411: Copy { + dest: StatePartIndex(339), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(395), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: unit_free_regs_tracker.rs:20:11 + 412: AndBigWithSmallImmediate { + dest: StatePartIndex(24), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(339), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:7:1 + 413: Copy { + dest: StatePartIndex(341), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(339), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 414: SliceInt { + dest: StatePartIndex(342), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(341), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + // at: ready_valid.rs:33:9 + 415: BranchIfZero { + target: 417, + value: StatePartIndex(340), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].ready", ty: Bool }, + }, + // at: ready_valid.rs:34:13 + 416: Copy { + dest: StatePartIndex(668), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(339), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: ready_valid.rs:30:27 + 417: AndBigWithSmallImmediate { + dest: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(668), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:7:1 + 418: Copy { + dest: StatePartIndex(669), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(668), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 419: SliceInt { + dest: StatePartIndex(670), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(669), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 420: CastBigToArrayIndex { + dest: StatePartIndex(47), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(670), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:150:13 + 421: Copy { + dest: StatePartIndex(331), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(339), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 422: AndBigWithSmallImmediate { + dest: StatePartIndex(49), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(331), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 423: Copy { + dest: StatePartIndex(681), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(331), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.alloc_out[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 424: SliceInt { + dest: StatePartIndex(682), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(681), // (0x1) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 425: Const { + dest: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: reg_alloc.rs:61:9 + 426: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].ready", ty: Bool }, + src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 427: Copy { + dest: StatePartIndex(5), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].ready", ty: Bool }, + src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:29:9 + 428: Copy { + dest: StatePartIndex(336), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, + src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:33:9 + 429: BranchIfZero { + target: 431, + value: StatePartIndex(336), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, + }, + // at: ready_valid.rs:34:13 + 430: Copy { + dest: StatePartIndex(391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + src: StatePartIndex(335), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + // at: ready_valid.rs:30:27 + 431: AndBigWithSmallImmediate { + dest: StatePartIndex(29), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:7:1 + 432: Copy { + dest: StatePartIndex(392), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(391), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::firing_data", ty: Enum {HdlNone, HdlSome(UInt<4>)} }, + }, + 433: SliceInt { + dest: StatePartIndex(393), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(392), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 434: CastBigToArrayIndex { + dest: StatePartIndex(30), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(393), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: unit_free_regs_tracker.rs:31:9 + 435: BranchIfSmallNeImmediate { + target: 437, + lhs: StatePartIndex(29), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:32:13 + 436: WriteIndexed { + dest: StatePartIndex(359) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool } */ [StatePartIndex(30) /* (0x0 0) SlotDebugData { name: "", ty: UInt<4> } */ , len=16, stride=1],, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:150:13 + 437: Copy { + dest: StatePartIndex(330), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_0_free_regs_tracker.free_in[0].ready", ty: Bool }, + src: StatePartIndex(336), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::free_in[0].ready", ty: Bool }, + }, + // at: unit_free_regs_tracker.rs:102:9 + 438: BranchIfSmallNeImmediate { + target: 440, + lhs: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: unit_free_regs_tracker.rs:103:13 + 439: WriteIndexed { + dest: StatePartIndex(359) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool } */ [StatePartIndex(47) /* (0x0 0) SlotDebugData { name: "", ty: UInt<4> } */ , len=16, stride=1],, + src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:41:1 + 440: Const { + dest: StatePartIndex(269), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + 441: Copy { + dest: StatePartIndex(270), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, + src: StatePartIndex(269), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: reg_alloc.rs:50:5 + 442: Copy { + dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, + src: StatePartIndex(270), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, + }, + // at: reg_alloc.rs:41:1 + 443: Copy { + dest: StatePartIndex(287), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(269), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 444: Copy { + dest: StatePartIndex(298), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + src: StatePartIndex(269), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: reg_alloc.rs:87:21 + 445: Copy { + dest: StatePartIndex(293), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + src: StatePartIndex(298), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + }, + 446: Copy { + dest: StatePartIndex(311), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + src: StatePartIndex(298), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + }, + // at: reg_alloc.rs:41:1 + 447: Copy { + dest: StatePartIndex(266), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, + }, + 448: SliceInt { + dest: StatePartIndex(267), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(266), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 449: Copy { + dest: StatePartIndex(268), // (0x0) SlotDebugData { name: "", ty: Enum {Trap(Bundle {}), ICacheFlush} }, + src: StatePartIndex(267), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:48:11 + 450: AndBigWithSmallImmediate { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Enum {Trap, ICacheFlush} }, + lhs: StatePartIndex(268), // (0x0) SlotDebugData { name: "", ty: Enum {Trap(Bundle {}), ICacheFlush} }, + rhs: 0x1, + }, + 451: AndBigWithSmallImmediate { + dest: StatePartIndex(14), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", ty: Enum {HdlNone, HdlSome(Enum {Trap(Bundle {}), ICacheFlush})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 452: Copy { + dest: StatePartIndex(140), // (0x802180000000000806051) SlotDebugData { name: "", ty: UInt<135> }, + src: StatePartIndex(4), // (0x802180000000000806051) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].data", ty: Enum {HdlNone, HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, + }, + 453: SliceInt { + dest: StatePartIndex(141), // (0x4010c0000000000403028) SlotDebugData { name: "", ty: UInt<134> }, + src: StatePartIndex(140), // (0x802180000000000806051) SlotDebugData { name: "", ty: UInt<135> }, + start: 1, + len: 134, + }, + 454: SliceInt { + dest: StatePartIndex(142), // (0xc0000000000403028) SlotDebugData { name: "", ty: UInt<69> }, + src: StatePartIndex(141), // (0x4010c0000000000403028) SlotDebugData { name: "", ty: UInt<134> }, + start: 0, + len: 69, + }, + 455: Copy { + dest: StatePartIndex(143), // (0xc0000000000403028) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(142), // (0xc0000000000403028) SlotDebugData { name: "", ty: UInt<69> }, + }, + 456: SliceInt { + dest: StatePartIndex(144), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(141), // (0x4010c0000000000403028) SlotDebugData { name: "", ty: UInt<134> }, + start: 69, + len: 1, + }, + 457: Copy { + dest: StatePartIndex(145), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(144), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 458: SliceInt { + dest: StatePartIndex(146), // (0x1004) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(141), // (0x4010c0000000000403028) SlotDebugData { name: "", ty: UInt<134> }, + start: 70, + len: 64, + }, + 459: Copy { + dest: StatePartIndex(137), // (0xc0000000000403028) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(143), // (0xc0000000000403028) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 460: Copy { + dest: StatePartIndex(138), // (0x0) SlotDebugData { name: ".is_unrelated_pc", ty: Bool }, + src: StatePartIndex(145), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 461: Copy { + dest: StatePartIndex(139), // (0x1004) SlotDebugData { name: ".pc", ty: UInt<64> }, + src: StatePartIndex(146), // (0x1004) SlotDebugData { name: "", ty: UInt<64> }, + }, + // at: reg_alloc.rs:48:11 + 462: AndBigWithSmallImmediate { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(137), // (0xc0000000000403028) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + rhs: 0x3, + }, + // at: unit.rs:107:1 + 463: BranchIfSmallNeImmediate { + target: 465, + lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 464: Copy { + dest: StatePartIndex(309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(287), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 465: BranchIfSmallNeImmediate { + target: 467, + lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 466: Copy { + dest: StatePartIndex(309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(289), // (0x1) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 467: BranchIfSmallNeImmediate { + target: 469, + lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 468: Copy { + dest: StatePartIndex(309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(291), // (0x2) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 469: AndBigWithSmallImmediate { + dest: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(309), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x3, + }, + 470: BranchIfSmallNeImmediate { + target: 472, + lhs: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 471: Copy { + dest: StatePartIndex(310), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 472: BranchIfSmallNeImmediate { + target: 474, + lhs: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 473: Copy { + dest: StatePartIndex(310), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 474: BranchIfSmallNeImmediate { + target: 476, + lhs: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 475: Copy { + dest: StatePartIndex(310), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:41:1 + 476: Copy { + dest: StatePartIndex(147), // (0xc0000000000403028) SlotDebugData { name: "", ty: UInt<69> }, + src: StatePartIndex(137), // (0xc0000000000403028) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 477: SliceInt { + dest: StatePartIndex(148), // (0x30000000000100c0a) SlotDebugData { name: "", ty: UInt<67> }, + src: StatePartIndex(147), // (0xc0000000000403028) SlotDebugData { name: "", ty: UInt<69> }, + start: 2, + len: 67, + }, + 478: Copy { + dest: StatePartIndex(149), // (0x30000000000100c0a) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(148), // (0x30000000000100c0a) SlotDebugData { name: "", ty: UInt<67> }, + }, + // at: reg_alloc.rs:48:11 + 479: AndBigWithSmallImmediate { + dest: StatePartIndex(9), // (0x2 2) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(149), // (0x30000000000100c0a) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:41:1 + 480: Copy { + dest: StatePartIndex(177), // (0x30000000000100c0a) SlotDebugData { name: "", ty: UInt<67> }, + src: StatePartIndex(149), // (0x30000000000100c0a) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 481: SliceInt { + dest: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, + src: StatePartIndex(177), // (0x30000000000100c0a) SlotDebugData { name: "", ty: UInt<67> }, + start: 2, + len: 65, + }, + 482: SliceInt { + dest: StatePartIndex(179), // (0x40302) SlotDebugData { name: "", ty: UInt<61> }, + src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, + start: 0, + len: 61, + }, + 483: SliceInt { + dest: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(179), // (0x40302) SlotDebugData { name: "", ty: UInt<61> }, + start: 0, + len: 58, + }, + 484: SliceInt { + dest: StatePartIndex(181), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, + start: 0, + len: 0, + }, + 485: SliceInt { + dest: StatePartIndex(182), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, + start: 0, + len: 8, + }, + 486: SliceInt { + dest: StatePartIndex(186), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, + start: 8, + len: 24, + }, + 487: SliceInt { + dest: StatePartIndex(187), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(186), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 488: SliceInt { + dest: StatePartIndex(188), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(186), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 489: SliceInt { + dest: StatePartIndex(189), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(186), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 490: Copy { + dest: StatePartIndex(183), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(187), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 491: Copy { + dest: StatePartIndex(184), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(188), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 492: Copy { + dest: StatePartIndex(185), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(189), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 493: SliceInt { + dest: StatePartIndex(190), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, + start: 32, + len: 25, + }, + 494: SliceInt { + dest: StatePartIndex(191), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(180), // (0x40302) SlotDebugData { name: "", ty: UInt<58> }, + start: 57, + len: 1, + }, + 495: CastToSInt { + dest: StatePartIndex(192), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(191), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 496: Copy { + dest: StatePartIndex(170), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(181), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 497: Copy { + dest: StatePartIndex(171), // (0x2) SlotDebugData { name: ".dest", ty: UInt<8> }, + src: StatePartIndex(182), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 498: Copy { + dest: StatePartIndex(172), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(183), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 499: Copy { + dest: StatePartIndex(173), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(184), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 500: Copy { + dest: StatePartIndex(174), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(185), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 501: Copy { + dest: StatePartIndex(175), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(190), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 502: Copy { + dest: StatePartIndex(176), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(192), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 503: SliceInt { + dest: StatePartIndex(193), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(179), // (0x40302) SlotDebugData { name: "", ty: UInt<61> }, + start: 58, + len: 3, + }, + 504: Copy { + dest: StatePartIndex(194), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(193), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 505: Copy { + dest: StatePartIndex(162), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(170), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 506: Copy { + dest: StatePartIndex(163), // (0x2) SlotDebugData { name: ".common.dest", ty: UInt<8> }, + src: StatePartIndex(171), // (0x2) SlotDebugData { name: ".dest", ty: UInt<8> }, + }, + 507: Copy { + dest: StatePartIndex(164), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + src: StatePartIndex(172), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + }, + 508: Copy { + dest: StatePartIndex(165), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + src: StatePartIndex(173), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + }, + 509: Copy { + dest: StatePartIndex(166), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + src: StatePartIndex(174), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + }, + 510: Copy { + dest: StatePartIndex(167), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(175), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 511: Copy { + dest: StatePartIndex(168), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(176), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 512: Copy { + dest: StatePartIndex(169), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(194), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 513: SliceInt { + dest: StatePartIndex(195), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, + start: 61, + len: 1, + }, + 514: Copy { + dest: StatePartIndex(196), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(195), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 515: SliceInt { + dest: StatePartIndex(197), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, + start: 62, + len: 1, + }, + 516: Copy { + dest: StatePartIndex(198), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(197), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 517: SliceInt { + dest: StatePartIndex(199), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, + start: 63, + len: 1, + }, + 518: Copy { + dest: StatePartIndex(200), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(199), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 519: SliceInt { + dest: StatePartIndex(201), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, + start: 64, + len: 1, + }, + 520: Copy { + dest: StatePartIndex(202), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(201), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 521: Copy { + dest: StatePartIndex(150), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(162), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 522: Copy { + dest: StatePartIndex(151), // (0x2) SlotDebugData { name: ".alu_common.common.dest", ty: UInt<8> }, + src: StatePartIndex(163), // (0x2) SlotDebugData { name: ".common.dest", ty: UInt<8> }, + }, + 523: Copy { + dest: StatePartIndex(152), // (0x3) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + src: StatePartIndex(164), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + }, + 524: Copy { + dest: StatePartIndex(153), // (0x4) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + src: StatePartIndex(165), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + }, + 525: Copy { + dest: StatePartIndex(154), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + src: StatePartIndex(166), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + }, + 526: Copy { + dest: StatePartIndex(155), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(167), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 527: Copy { + dest: StatePartIndex(156), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(168), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 528: Copy { + dest: StatePartIndex(157), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(169), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 529: Copy { + dest: StatePartIndex(158), // (0x0) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(196), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 530: Copy { + dest: StatePartIndex(159), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(198), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 531: Copy { + dest: StatePartIndex(160), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(200), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 532: Copy { + dest: StatePartIndex(161), // (0x0) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(202), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:48:11 + 533: AndBigWithSmallImmediate { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(157), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:41:1 + 534: SliceInt { + dest: StatePartIndex(212), // (0x6) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(178), // (0xc000000000040302) SlotDebugData { name: "", ty: UInt<65> }, + start: 61, + len: 4, + }, + 535: Copy { + dest: StatePartIndex(203), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(162), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 536: Copy { + dest: StatePartIndex(204), // (0x2) SlotDebugData { name: ".alu_common.common.dest", ty: UInt<8> }, + src: StatePartIndex(163), // (0x2) SlotDebugData { name: ".common.dest", ty: UInt<8> }, + }, + 537: Copy { + dest: StatePartIndex(205), // (0x3) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + src: StatePartIndex(164), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + }, + 538: Copy { + dest: StatePartIndex(206), // (0x4) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + src: StatePartIndex(165), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + }, + 539: Copy { + dest: StatePartIndex(207), // (0x0) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + src: StatePartIndex(166), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + }, + 540: Copy { + dest: StatePartIndex(208), // (0x0) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(167), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 541: Copy { + dest: StatePartIndex(209), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(168), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 542: Copy { + dest: StatePartIndex(210), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(169), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 543: Copy { + dest: StatePartIndex(211), // (0x6) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(212), // (0x6) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:48:11 + 544: AndBigWithSmallImmediate { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(210), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:41:1 + 545: SliceInt { + dest: StatePartIndex(213), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, + src: StatePartIndex(147), // (0xc0000000000403028) SlotDebugData { name: "", ty: UInt<69> }, + start: 2, + len: 60, + }, + 546: Copy { + dest: StatePartIndex(214), // (0x100c0a) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(213), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, + }, + // at: reg_alloc.rs:48:11 + 547: AndBigWithSmallImmediate { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + lhs: StatePartIndex(214), // (0x100c0a) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 548: Copy { + dest: StatePartIndex(229), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, + src: StatePartIndex(214), // (0x100c0a) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 549: SliceInt { + dest: StatePartIndex(230), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(229), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, + start: 1, + len: 59, + }, + 550: SliceInt { + dest: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(230), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 0, + len: 59, + }, + 551: SliceInt { + dest: StatePartIndex(232), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 0, + len: 1, + }, + 552: SliceInt { + dest: StatePartIndex(233), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 1, + len: 8, + }, + 553: SliceInt { + dest: StatePartIndex(237), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 9, + len: 24, + }, + 554: SliceInt { + dest: StatePartIndex(238), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(237), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 555: SliceInt { + dest: StatePartIndex(239), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(237), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 556: SliceInt { + dest: StatePartIndex(240), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(237), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 557: Copy { + dest: StatePartIndex(234), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(238), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 558: Copy { + dest: StatePartIndex(235), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(239), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 559: Copy { + dest: StatePartIndex(236), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(240), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 560: SliceInt { + dest: StatePartIndex(241), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 33, + len: 25, + }, + 561: SliceInt { + dest: StatePartIndex(242), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(231), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 58, + len: 1, + }, + 562: CastToSInt { + dest: StatePartIndex(243), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(242), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 563: Copy { + dest: StatePartIndex(222), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(232), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 564: Copy { + dest: StatePartIndex(223), // (0x2) SlotDebugData { name: ".dest", ty: UInt<8> }, + src: StatePartIndex(233), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 565: Copy { + dest: StatePartIndex(224), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(234), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 566: Copy { + dest: StatePartIndex(225), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(235), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 567: Copy { + dest: StatePartIndex(226), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(236), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 568: Copy { + dest: StatePartIndex(227), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(241), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 569: Copy { + dest: StatePartIndex(228), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(243), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 570: Copy { + dest: StatePartIndex(215), // (0x1) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(222), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 571: Copy { + dest: StatePartIndex(216), // (0x2) SlotDebugData { name: ".common.dest", ty: UInt<8> }, + src: StatePartIndex(223), // (0x2) SlotDebugData { name: ".dest", ty: UInt<8> }, + }, + 572: Copy { + dest: StatePartIndex(217), // (0x3) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + src: StatePartIndex(224), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + }, + 573: Copy { + dest: StatePartIndex(218), // (0x4) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + src: StatePartIndex(225), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + }, + 574: Copy { + dest: StatePartIndex(219), // (0x0) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + src: StatePartIndex(226), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + }, + 575: Copy { + dest: StatePartIndex(220), // (0x0) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(227), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 576: Copy { + dest: StatePartIndex(221), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(228), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 577: Copy { + dest: StatePartIndex(244), // (0x100c0a) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(213), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, + }, + // at: reg_alloc.rs:48:11 + 578: AndBigWithSmallImmediate { + dest: StatePartIndex(13), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + lhs: StatePartIndex(244), // (0x100c0a) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 579: Copy { + dest: StatePartIndex(252), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, + src: StatePartIndex(244), // (0x100c0a) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 580: SliceInt { + dest: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(252), // (0x100c0a) SlotDebugData { name: "", ty: UInt<60> }, + start: 1, + len: 59, + }, + 581: SliceInt { + dest: StatePartIndex(254), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 0, + len: 1, + }, + 582: SliceInt { + dest: StatePartIndex(255), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 1, + len: 8, + }, + 583: SliceInt { + dest: StatePartIndex(259), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 9, + len: 24, + }, + 584: SliceInt { + dest: StatePartIndex(260), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(259), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 585: SliceInt { + dest: StatePartIndex(261), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(259), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 586: SliceInt { + dest: StatePartIndex(262), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(259), // (0x403) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 587: Copy { + dest: StatePartIndex(256), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(260), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 588: Copy { + dest: StatePartIndex(257), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(261), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 589: Copy { + dest: StatePartIndex(258), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(262), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + 590: SliceInt { + dest: StatePartIndex(263), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 33, + len: 25, + }, + 591: SliceInt { + dest: StatePartIndex(264), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(253), // (0x80605) SlotDebugData { name: "", ty: UInt<59> }, + start: 58, + len: 1, + }, + 592: CastToSInt { + dest: StatePartIndex(265), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(264), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 593: Copy { + dest: StatePartIndex(245), // (0x1) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(254), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 594: Copy { + dest: StatePartIndex(246), // (0x2) SlotDebugData { name: ".dest", ty: UInt<8> }, + src: StatePartIndex(255), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 595: Copy { + dest: StatePartIndex(247), // (0x3) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(256), // (0x3) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 596: Copy { + dest: StatePartIndex(248), // (0x4) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(257), // (0x4) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 597: Copy { + dest: StatePartIndex(249), // (0x0) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(258), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 598: Copy { + dest: StatePartIndex(250), // (0x0) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(263), // (0x0) SlotDebugData { name: "", ty: UInt<25> }, + }, + 599: Copy { + dest: StatePartIndex(251), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(265), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + // at: reg_alloc.rs:48:11 + 600: AndBigWithSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(4), // (0x802180000000000806051) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].data", ty: Enum {HdlNone, HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:70:9 + 601: BranchIfSmallNeImmediate { + target: 603, + lhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:71:13 + 602: Copy { + dest: StatePartIndex(272), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, + src: StatePartIndex(310), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + }, + // at: reg_alloc.rs:41:1 + 603: Copy { + dest: StatePartIndex(11), // (0x8007c0002468080604021) SlotDebugData { name: "", ty: UInt<135> }, + src: StatePartIndex(2), // (0x8007c0002468080604021) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].data", ty: Enum {HdlNone, HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, + }, + 604: SliceInt { + dest: StatePartIndex(12), // (0x4003e0001234040302010) SlotDebugData { name: "", ty: UInt<134> }, + src: StatePartIndex(11), // (0x8007c0002468080604021) SlotDebugData { name: "", ty: UInt<135> }, + start: 1, + len: 134, + }, + 605: SliceInt { + dest: StatePartIndex(13), // (0x1e0001234040302010) SlotDebugData { name: "", ty: UInt<69> }, + src: StatePartIndex(12), // (0x4003e0001234040302010) SlotDebugData { name: "", ty: UInt<134> }, + start: 0, + len: 69, + }, + 606: Copy { + dest: StatePartIndex(14), // (0x1e0001234040302010) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(13), // (0x1e0001234040302010) SlotDebugData { name: "", ty: UInt<69> }, + }, + 607: SliceInt { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(12), // (0x4003e0001234040302010) SlotDebugData { name: "", ty: UInt<134> }, + start: 69, + len: 1, + }, + 608: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 609: SliceInt { + dest: StatePartIndex(17), // (0x1000) SlotDebugData { name: "", ty: UInt<64> }, + src: StatePartIndex(12), // (0x4003e0001234040302010) SlotDebugData { name: "", ty: UInt<134> }, + start: 70, + len: 64, + }, + 610: Copy { + dest: StatePartIndex(8), // (0x1e0001234040302010) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + src: StatePartIndex(14), // (0x1e0001234040302010) SlotDebugData { name: "", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 611: Copy { + dest: StatePartIndex(9), // (0x1) SlotDebugData { name: ".is_unrelated_pc", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 612: Copy { + dest: StatePartIndex(10), // (0x1000) SlotDebugData { name: ".pc", ty: UInt<64> }, + src: StatePartIndex(17), // (0x1000) SlotDebugData { name: "", ty: UInt<64> }, + }, + // at: reg_alloc.rs:48:11 + 613: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(8), // (0x1e0001234040302010) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + rhs: 0x3, + }, + // at: unit.rs:107:1 + 614: BranchIfSmallNeImmediate { + target: 616, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 615: Copy { + dest: StatePartIndex(286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(287), // (0x0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 616: BranchIfSmallNeImmediate { + target: 618, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 617: Copy { + dest: StatePartIndex(286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(289), // (0x1) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 618: BranchIfSmallNeImmediate { + target: 620, + lhs: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 619: Copy { + dest: StatePartIndex(286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + src: StatePartIndex(291), // (0x2) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + }, + 620: AndBigWithSmallImmediate { + dest: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + lhs: StatePartIndex(286), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::unit_kind", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x3, + }, + 621: BranchIfSmallNeImmediate { + target: 623, + lhs: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x0, + }, + 622: Copy { + dest: StatePartIndex(292), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(283), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 623: BranchIfSmallNeImmediate { + target: 625, + lhs: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x1, + }, + 624: Copy { + dest: StatePartIndex(292), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 625: BranchIfSmallNeImmediate { + target: 627, + lhs: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Enum {AluBranch, L2RegisterFile, LoadStore} }, + rhs: 0x2, + }, + 626: Copy { + dest: StatePartIndex(292), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:41:1 + 627: Copy { + dest: StatePartIndex(18), // (0x1e0001234040302010) SlotDebugData { name: "", ty: UInt<69> }, + src: StatePartIndex(8), // (0x1e0001234040302010) SlotDebugData { name: ".uop", ty: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})} }, + }, + 628: SliceInt { + dest: StatePartIndex(19), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: UInt<67> }, + src: StatePartIndex(18), // (0x1e0001234040302010) SlotDebugData { name: "", ty: UInt<69> }, + start: 2, + len: 67, + }, + 629: Copy { + dest: StatePartIndex(20), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + src: StatePartIndex(19), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: UInt<67> }, + }, + // at: reg_alloc.rs:48:11 + 630: AndBigWithSmallImmediate { + dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Enum {AddSub, AddSubI, Logical} }, + lhs: StatePartIndex(20), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + rhs: 0x3, + }, + // at: reg_alloc.rs:41:1 + 631: Copy { + dest: StatePartIndex(48), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: UInt<67> }, + src: StatePartIndex(20), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})} }, + }, + 632: SliceInt { + dest: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, + src: StatePartIndex(48), // (0x7800048d0100c0804) SlotDebugData { name: "", ty: UInt<67> }, + start: 2, + len: 65, + }, + 633: SliceInt { + dest: StatePartIndex(50), // (0x123404030201) SlotDebugData { name: "", ty: UInt<61> }, + src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, + start: 0, + len: 61, + }, + 634: SliceInt { + dest: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, + src: StatePartIndex(50), // (0x123404030201) SlotDebugData { name: "", ty: UInt<61> }, + start: 0, + len: 58, + }, + 635: SliceInt { + dest: StatePartIndex(52), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, + start: 0, + len: 0, + }, + 636: SliceInt { + dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, + start: 0, + len: 8, + }, + 637: SliceInt { + dest: StatePartIndex(57), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, + start: 8, + len: 24, + }, + 638: SliceInt { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(57), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 639: SliceInt { + dest: StatePartIndex(59), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(57), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 640: SliceInt { + dest: StatePartIndex(60), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(57), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 641: Copy { + dest: StatePartIndex(54), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 642: Copy { + dest: StatePartIndex(55), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(59), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 643: Copy { + dest: StatePartIndex(56), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(60), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 644: SliceInt { + dest: StatePartIndex(61), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, + start: 32, + len: 25, + }, + 645: SliceInt { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(51), // (0x123404030201) SlotDebugData { name: "", ty: UInt<58> }, + start: 57, + len: 1, + }, + 646: CastToSInt { + dest: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 647: Copy { + dest: StatePartIndex(41), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + src: StatePartIndex(52), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 648: Copy { + dest: StatePartIndex(42), // (0x1) SlotDebugData { name: ".dest", ty: UInt<8> }, + src: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + 649: Copy { + dest: StatePartIndex(43), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(54), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 650: Copy { + dest: StatePartIndex(44), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(55), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 651: Copy { + dest: StatePartIndex(45), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(56), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 652: Copy { + dest: StatePartIndex(46), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(61), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 653: Copy { + dest: StatePartIndex(47), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 654: SliceInt { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(50), // (0x123404030201) SlotDebugData { name: "", ty: UInt<61> }, + start: 58, + len: 3, + }, + 655: Copy { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 656: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(41), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<0> }, + }, + 657: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: ".common.dest", ty: UInt<8> }, + src: StatePartIndex(42), // (0x1) SlotDebugData { name: ".dest", ty: UInt<8> }, + }, + 658: Copy { + dest: StatePartIndex(35), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + src: StatePartIndex(43), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + }, + 659: Copy { + dest: StatePartIndex(36), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + src: StatePartIndex(44), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + }, + 660: Copy { + dest: StatePartIndex(37), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + src: StatePartIndex(45), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + }, + 661: Copy { + dest: StatePartIndex(38), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(46), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 662: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(47), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 663: Copy { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 664: SliceInt { + dest: StatePartIndex(66), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, + start: 61, + len: 1, + }, + 665: Copy { + dest: StatePartIndex(67), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(66), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 666: SliceInt { + dest: StatePartIndex(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, + start: 62, + len: 1, + }, + 667: Copy { + dest: StatePartIndex(69), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 668: SliceInt { + dest: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, + start: 63, + len: 1, + }, + 669: Copy { + dest: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 670: SliceInt { + dest: StatePartIndex(72), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, + start: 64, + len: 1, + }, + 671: Copy { + dest: StatePartIndex(73), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(72), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 672: Copy { + dest: StatePartIndex(21), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 673: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: ".alu_common.common.dest", ty: UInt<8> }, + src: StatePartIndex(34), // (0x1) SlotDebugData { name: ".common.dest", ty: UInt<8> }, + }, + 674: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + src: StatePartIndex(35), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + }, + 675: Copy { + dest: StatePartIndex(24), // (0x3) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + src: StatePartIndex(36), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + }, + 676: Copy { + dest: StatePartIndex(25), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + src: StatePartIndex(37), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + }, + 677: Copy { + dest: StatePartIndex(26), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(38), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 678: Copy { + dest: StatePartIndex(27), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 679: Copy { + dest: StatePartIndex(28), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 680: Copy { + dest: StatePartIndex(29), // (0x1) SlotDebugData { name: ".invert_src0", ty: Bool }, + src: StatePartIndex(67), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 681: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: ".invert_carry_in", ty: Bool }, + src: StatePartIndex(69), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 682: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: ".invert_carry_out", ty: Bool }, + src: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 683: Copy { + dest: StatePartIndex(32), // (0x1) SlotDebugData { name: ".add_pc", ty: Bool }, + src: StatePartIndex(73), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:48:11 + 684: AndBigWithSmallImmediate { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(28), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:41:1 + 685: SliceInt { + dest: StatePartIndex(83), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(49), // (0x1e000123404030201) SlotDebugData { name: "", ty: UInt<65> }, + start: 61, + len: 4, + }, + 686: Copy { + dest: StatePartIndex(74), // (0x0) SlotDebugData { name: ".alu_common.common.prefix_pad", ty: UInt<0> }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<0> }, + }, + 687: Copy { + dest: StatePartIndex(75), // (0x1) SlotDebugData { name: ".alu_common.common.dest", ty: UInt<8> }, + src: StatePartIndex(34), // (0x1) SlotDebugData { name: ".common.dest", ty: UInt<8> }, + }, + 688: Copy { + dest: StatePartIndex(76), // (0x2) SlotDebugData { name: ".alu_common.common.src[0]", ty: UInt<8> }, + src: StatePartIndex(35), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + }, + 689: Copy { + dest: StatePartIndex(77), // (0x3) SlotDebugData { name: ".alu_common.common.src[1]", ty: UInt<8> }, + src: StatePartIndex(36), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + }, + 690: Copy { + dest: StatePartIndex(78), // (0x4) SlotDebugData { name: ".alu_common.common.src[2]", ty: UInt<8> }, + src: StatePartIndex(37), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + }, + 691: Copy { + dest: StatePartIndex(79), // (0x1234) SlotDebugData { name: ".alu_common.common.imm_low", ty: UInt<25> }, + src: StatePartIndex(38), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + }, + 692: Copy { + dest: StatePartIndex(80), // (0x0) SlotDebugData { name: ".alu_common.common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + }, + 693: Copy { + dest: StatePartIndex(81), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: ".output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + }, + 694: Copy { + dest: StatePartIndex(82), // (0xf) SlotDebugData { name: ".lut", ty: UInt<4> }, + src: StatePartIndex(83), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: reg_alloc.rs:48:11 + 695: AndBigWithSmallImmediate { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + lhs: StatePartIndex(81), // (0x0) SlotDebugData { name: ".alu_common.output_integer_mode", ty: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8} }, + rhs: 0x7, + }, + // at: reg_alloc.rs:41:1 + 696: SliceInt { + dest: StatePartIndex(84), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, + src: StatePartIndex(18), // (0x1e0001234040302010) SlotDebugData { name: "", ty: UInt<69> }, + start: 2, + len: 60, + }, + 697: Copy { + dest: StatePartIndex(85), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + src: StatePartIndex(84), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, + }, + // at: reg_alloc.rs:48:11 + 698: AndBigWithSmallImmediate { + dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Enum {ReadL2Reg, WriteL2Reg} }, + lhs: StatePartIndex(85), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 699: Copy { + dest: StatePartIndex(100), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, + src: StatePartIndex(85), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})} }, + }, + 700: SliceInt { + dest: StatePartIndex(101), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(100), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, + start: 1, + len: 59, + }, + 701: SliceInt { + dest: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(101), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 0, + len: 59, + }, + 702: SliceInt { + dest: StatePartIndex(103), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 0, + len: 1, + }, + 703: SliceInt { + dest: StatePartIndex(104), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 1, + len: 8, + }, + 704: SliceInt { + dest: StatePartIndex(108), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 9, + len: 24, + }, + 705: SliceInt { + dest: StatePartIndex(109), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(108), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 706: SliceInt { + dest: StatePartIndex(110), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(108), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 707: SliceInt { + dest: StatePartIndex(111), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(108), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 708: Copy { + dest: StatePartIndex(105), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(109), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 709: Copy { + dest: StatePartIndex(106), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(110), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 710: Copy { + dest: StatePartIndex(107), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(111), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 711: SliceInt { + dest: StatePartIndex(112), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 33, + len: 25, + }, + 712: SliceInt { + dest: StatePartIndex(113), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(102), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 58, + len: 1, + }, + 713: CastToSInt { + dest: StatePartIndex(114), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(113), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 714: Copy { + dest: StatePartIndex(93), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(103), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 715: Copy { + dest: StatePartIndex(94), // (0x1) SlotDebugData { name: ".dest", ty: UInt<8> }, + src: StatePartIndex(104), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + 716: Copy { + dest: StatePartIndex(95), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(105), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 717: Copy { + dest: StatePartIndex(96), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(106), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 718: Copy { + dest: StatePartIndex(97), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(107), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 719: Copy { + dest: StatePartIndex(98), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(112), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 720: Copy { + dest: StatePartIndex(99), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(114), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + 721: Copy { + dest: StatePartIndex(86), // (0x0) SlotDebugData { name: ".common.prefix_pad", ty: UInt<1> }, + src: StatePartIndex(93), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + }, + 722: Copy { + dest: StatePartIndex(87), // (0x1) SlotDebugData { name: ".common.dest", ty: UInt<8> }, + src: StatePartIndex(94), // (0x1) SlotDebugData { name: ".dest", ty: UInt<8> }, + }, + 723: Copy { + dest: StatePartIndex(88), // (0x2) SlotDebugData { name: ".common.src[0]", ty: UInt<8> }, + src: StatePartIndex(95), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + }, + 724: Copy { + dest: StatePartIndex(89), // (0x3) SlotDebugData { name: ".common.src[1]", ty: UInt<8> }, + src: StatePartIndex(96), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + }, + 725: Copy { + dest: StatePartIndex(90), // (0x4) SlotDebugData { name: ".common.src[2]", ty: UInt<8> }, + src: StatePartIndex(97), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + }, + 726: Copy { + dest: StatePartIndex(91), // (0x1234) SlotDebugData { name: ".common.imm_low", ty: UInt<25> }, + src: StatePartIndex(98), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + }, + 727: Copy { + dest: StatePartIndex(92), // (0x0) SlotDebugData { name: ".common.imm_sign", ty: SInt<1> }, + src: StatePartIndex(99), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + }, + 728: Copy { + dest: StatePartIndex(115), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + src: StatePartIndex(84), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, + }, + // at: reg_alloc.rs:48:11 + 729: AndBigWithSmallImmediate { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Enum {Load, Store} }, + lhs: StatePartIndex(115), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 730: Copy { + dest: StatePartIndex(123), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, + src: StatePartIndex(115), // (0x48d0100c0804) SlotDebugData { name: "", ty: Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})} }, + }, + 731: SliceInt { + dest: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + src: StatePartIndex(123), // (0x48d0100c0804) SlotDebugData { name: "", ty: UInt<60> }, + start: 1, + len: 59, + }, + 732: SliceInt { + dest: StatePartIndex(125), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 0, + len: 1, + }, + 733: SliceInt { + dest: StatePartIndex(126), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 1, + len: 8, + }, + 734: SliceInt { + dest: StatePartIndex(130), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + src: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 9, + len: 24, + }, + 735: SliceInt { + dest: StatePartIndex(131), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(130), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 0, + len: 8, + }, + 736: SliceInt { + dest: StatePartIndex(132), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(130), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 8, + len: 8, + }, + 737: SliceInt { + dest: StatePartIndex(133), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(130), // (0x40302) SlotDebugData { name: "", ty: UInt<24> }, + start: 16, + len: 8, + }, + 738: Copy { + dest: StatePartIndex(127), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(131), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + 739: Copy { + dest: StatePartIndex(128), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(132), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + 740: Copy { + dest: StatePartIndex(129), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(133), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + 741: SliceInt { + dest: StatePartIndex(134), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + src: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 33, + len: 25, + }, + 742: SliceInt { + dest: StatePartIndex(135), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(124), // (0x246808060402) SlotDebugData { name: "", ty: UInt<59> }, + start: 58, + len: 1, + }, + 743: CastToSInt { + dest: StatePartIndex(136), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + src: StatePartIndex(135), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 1, + }, + 744: Copy { + dest: StatePartIndex(116), // (0x0) SlotDebugData { name: ".prefix_pad", ty: UInt<1> }, + src: StatePartIndex(125), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 745: Copy { + dest: StatePartIndex(117), // (0x1) SlotDebugData { name: ".dest", ty: UInt<8> }, + src: StatePartIndex(126), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + 746: Copy { + dest: StatePartIndex(118), // (0x2) SlotDebugData { name: ".src[0]", ty: UInt<8> }, + src: StatePartIndex(127), // (0x2) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 747: Copy { + dest: StatePartIndex(119), // (0x3) SlotDebugData { name: ".src[1]", ty: UInt<8> }, + src: StatePartIndex(128), // (0x3) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 748: Copy { + dest: StatePartIndex(120), // (0x4) SlotDebugData { name: ".src[2]", ty: UInt<8> }, + src: StatePartIndex(129), // (0x4) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 749: Copy { + dest: StatePartIndex(121), // (0x1234) SlotDebugData { name: ".imm_low", ty: UInt<25> }, + src: StatePartIndex(134), // (0x1234) SlotDebugData { name: "", ty: UInt<25> }, + }, + 750: Copy { + dest: StatePartIndex(122), // (0x0) SlotDebugData { name: ".imm_sign", ty: SInt<1> }, + src: StatePartIndex(136), // (0x0) SlotDebugData { name: "", ty: SInt<1> }, + }, + // at: reg_alloc.rs:48:11 + 751: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x8007c0002468080604021) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].data", ty: Enum {HdlNone, HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:70:9 + 752: BranchIfSmallNeImmediate { + target: 754, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:71:13 + 753: Copy { + dest: StatePartIndex(271), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, + src: StatePartIndex(292), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units_for_kind[0]", ty: Bool }, + }, + // at: reg_alloc.rs:95:21 + 754: BranchIfZero { + target: 756, + value: StatePartIndex(271), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[0][0]", ty: Bool }, + }, + // at: reg_alloc.rs:96:25 + 755: Copy { + dest: StatePartIndex(293), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + src: StatePartIndex(308), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + }, + // at: reg_alloc.rs:84:25 + 756: AndBigWithSmallImmediate { + dest: StatePartIndex(19), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(293), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 757: Copy { + dest: StatePartIndex(295), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(293), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + }, + 758: SliceInt { + dest: StatePartIndex(296), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(295), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 759: SliceInt { + dest: StatePartIndex(297), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(296), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + start: 0, + len: 1, + }, + 760: Copy { + dest: StatePartIndex(294), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, + src: StatePartIndex(297), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:76:9 + 761: Copy { + dest: StatePartIndex(273), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[0]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + src: StatePartIndex(293), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_0_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + }, + // at: reg_alloc.rs:59:30 + 762: AndBigWithSmallImmediate { + dest: StatePartIndex(16), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(273), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[0]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 763: Copy { + dest: StatePartIndex(276), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(273), // (0x1) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[0]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + }, + 764: SliceInt { + dest: StatePartIndex(277), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(276), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 765: SliceInt { + dest: StatePartIndex(278), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(277), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + start: 0, + len: 1, + }, + 766: Copy { + dest: StatePartIndex(275), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, + src: StatePartIndex(278), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 767: CastBigToArrayIndex { + dest: StatePartIndex(22), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(275), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, + }, + // at: reg_alloc.rs:123:13 + 768: BranchIfSmallNeImmediate { + target: 770, + lhs: StatePartIndex(16), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:124:17 + 769: WriteIndexed { + dest: StatePartIndex(272) /* (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool } */ [StatePartIndex(22) /* (0x0 0) SlotDebugData { name: "", ty: UInt<1> } */ , len=1, stride=1],, + src: StatePartIndex(285), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: reg_alloc.rs:95:21 + 770: BranchIfZero { + target: 772, + value: StatePartIndex(272), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::available_units[1][0]", ty: Bool }, + }, + // at: reg_alloc.rs:96:25 + 771: Copy { + dest: StatePartIndex(311), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + src: StatePartIndex(322), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + }, + // at: reg_alloc.rs:84:25 + 772: AndBigWithSmallImmediate { + dest: StatePartIndex(21), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(311), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 773: Copy { + dest: StatePartIndex(313), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(311), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + }, + 774: SliceInt { + dest: StatePartIndex(314), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(313), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 775: SliceInt { + dest: StatePartIndex(315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(314), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + start: 0, + len: 1, + }, + 776: Copy { + dest: StatePartIndex(312), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, + src: StatePartIndex(315), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: reg_alloc.rs:76:9 + 777: Copy { + dest: StatePartIndex(274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[1]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + src: StatePartIndex(311), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_leaf_1_0", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + }, + // at: reg_alloc.rs:59:30 + 778: AndBigWithSmallImmediate { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[1]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 779: Copy { + dest: StatePartIndex(280), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(274), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::selected_unit_nums[1]", ty: Enum {HdlNone, HdlSome(Bundle {value: UInt<1>})} }, + }, + 780: SliceInt { + dest: StatePartIndex(281), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(280), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 781: SliceInt { + dest: StatePartIndex(282), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(281), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + start: 0, + len: 1, + }, + 782: Copy { + dest: StatePartIndex(279), // (0x0) SlotDebugData { name: ".value", ty: UInt<1> }, + src: StatePartIndex(282), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: unit_free_regs_tracker.rs:27:25 + 783: BranchIfSmallZero { + target: 818, + value: StatePartIndex(26), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 784: BranchIfSmallNonZero { + target: 802, + value: StatePartIndex(28), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 785: Copy { + dest: StatePartIndex(343), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, + src: StatePartIndex(359), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[0]", ty: Bool }, + }, + 786: Copy { + dest: StatePartIndex(344), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, + src: StatePartIndex(360), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[1]", ty: Bool }, + }, + 787: Copy { + dest: StatePartIndex(345), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, + src: StatePartIndex(361), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[2]", ty: Bool }, + }, + 788: Copy { + dest: StatePartIndex(346), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, + src: StatePartIndex(362), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[3]", ty: Bool }, + }, + 789: Copy { + dest: StatePartIndex(347), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, + src: StatePartIndex(363), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[4]", ty: Bool }, + }, + 790: Copy { + dest: StatePartIndex(348), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, + src: StatePartIndex(364), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[5]", ty: Bool }, + }, + 791: Copy { + dest: StatePartIndex(349), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, + src: StatePartIndex(365), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[6]", ty: Bool }, + }, + 792: Copy { + dest: StatePartIndex(350), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, + src: StatePartIndex(366), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[7]", ty: Bool }, + }, + 793: Copy { + dest: StatePartIndex(351), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, + src: StatePartIndex(367), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[8]", ty: Bool }, + }, + 794: Copy { + dest: StatePartIndex(352), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, + src: StatePartIndex(368), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[9]", ty: Bool }, + }, + 795: Copy { + dest: StatePartIndex(353), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, + src: StatePartIndex(369), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[10]", ty: Bool }, + }, + 796: Copy { + dest: StatePartIndex(354), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, + src: StatePartIndex(370), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[11]", ty: Bool }, + }, + 797: Copy { + dest: StatePartIndex(355), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, + src: StatePartIndex(371), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[12]", ty: Bool }, + }, + 798: Copy { + dest: StatePartIndex(356), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, + src: StatePartIndex(372), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[13]", ty: Bool }, + }, + 799: Copy { + dest: StatePartIndex(357), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, + src: StatePartIndex(373), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[14]", ty: Bool }, + }, + 800: Copy { + dest: StatePartIndex(358), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, + src: StatePartIndex(374), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg$next[15]", ty: Bool }, + }, + 801: Branch { + target: 818, + }, + 802: Copy { + dest: StatePartIndex(343), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[0]", ty: Bool }, + src: StatePartIndex(375), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + }, + 803: Copy { + dest: StatePartIndex(344), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[1]", ty: Bool }, + src: StatePartIndex(376), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + }, + 804: Copy { + dest: StatePartIndex(345), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[2]", ty: Bool }, + src: StatePartIndex(377), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, + }, + 805: Copy { + dest: StatePartIndex(346), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[3]", ty: Bool }, + src: StatePartIndex(378), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, + }, + 806: Copy { + dest: StatePartIndex(347), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[4]", ty: Bool }, + src: StatePartIndex(379), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, + }, + 807: Copy { + dest: StatePartIndex(348), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[5]", ty: Bool }, + src: StatePartIndex(380), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, + }, + 808: Copy { + dest: StatePartIndex(349), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[6]", ty: Bool }, + src: StatePartIndex(381), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, + }, + 809: Copy { + dest: StatePartIndex(350), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[7]", ty: Bool }, + src: StatePartIndex(382), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, + }, + 810: Copy { + dest: StatePartIndex(351), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[8]", ty: Bool }, + src: StatePartIndex(383), // (0x0) SlotDebugData { name: "[8]", ty: Bool }, + }, + 811: Copy { + dest: StatePartIndex(352), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[9]", ty: Bool }, + src: StatePartIndex(384), // (0x0) SlotDebugData { name: "[9]", ty: Bool }, + }, + 812: Copy { + dest: StatePartIndex(353), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[10]", ty: Bool }, + src: StatePartIndex(385), // (0x0) SlotDebugData { name: "[10]", ty: Bool }, + }, + 813: Copy { + dest: StatePartIndex(354), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[11]", ty: Bool }, + src: StatePartIndex(386), // (0x0) SlotDebugData { name: "[11]", ty: Bool }, + }, + 814: Copy { + dest: StatePartIndex(355), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[12]", ty: Bool }, + src: StatePartIndex(387), // (0x0) SlotDebugData { name: "[12]", ty: Bool }, + }, + 815: Copy { + dest: StatePartIndex(356), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[13]", ty: Bool }, + src: StatePartIndex(388), // (0x0) SlotDebugData { name: "[13]", ty: Bool }, + }, + 816: Copy { + dest: StatePartIndex(357), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[14]", ty: Bool }, + src: StatePartIndex(389), // (0x0) SlotDebugData { name: "[14]", ty: Bool }, + }, + 817: Copy { + dest: StatePartIndex(358), // (0x0) SlotDebugData { name: "InstantiatedModule(reg_alloc.unit_0_free_regs_tracker: unit_free_regs_tracker).unit_free_regs_tracker::allocated_reg[15]", ty: Bool }, + src: StatePartIndex(390), // (0x0) SlotDebugData { name: "[15]", ty: Bool }, + }, + 818: XorSmallImmediate { + dest: StatePartIndex(25), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(27), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: reg_alloc.rs:41:1 + 819: Return, + ], + .. + }, + pc: 819, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [ + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 18446744073709551615, + 18446744073709551615, + 0, + 18446744073709551615, + 18446744073709551615, + 0, + 0, + 18446744073709551615, + 18446744073709551615, + 0, + 18446744073709551615, + 18446744073709551615, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 9673693953822641059020833, + 1, + 9681294011740541725728849, + 1, + 0, + 1, + 553402642445125034000, + 1, + 4096, + 9673693953822641059020833, + 4836846976911320529510416, + 553402642445125034000, + 553402642445125034000, + 1, + 1, + 4096, + 553402642445125034000, + 138350660611281258500, + 138350660611281258500, + 0, + 1, + 2, + 3, + 4, + 4660, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 2, + 3, + 4, + 4660, + 0, + 0, + 0, + 1, + 2, + 3, + 4, + 4660, + 0, + 138350660611281258500, + 34587665152820314625, + 20014614905345, + 20014614905345, + 0, + 1, + 2, + 3, + 4, + 262914, + 2, + 3, + 4, + 4660, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 2, + 3, + 4, + 4660, + 0, + 0, + 15, + 15, + 80058459621380, + 80058459621380, + 0, + 1, + 2, + 3, + 4, + 4660, + 0, + 0, + 1, + 2, + 3, + 4, + 4660, + 0, + 80058459621380, + 40029229810690, + 40029229810690, + 0, + 1, + 2, + 3, + 4, + 262914, + 2, + 3, + 4, + 4660, + 0, + 0, + 80058459621380, + 0, + 1, + 2, + 3, + 4, + 4660, + 0, + 80058459621380, + 40029229810690, + 0, + 1, + 2, + 3, + 4, + 262914, + 2, + 3, + 4, + 4660, + 0, + 0, + 221360928884518826024, + 0, + 4100, + 9681294011740541725728849, + 4840647005870270862864424, + 221360928884518826024, + 221360928884518826024, + 0, + 0, + 4100, + 221360928884518826024, + 55340232221129706506, + 55340232221129706506, + 0, + 2, + 3, + 4, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 2, + 3, + 4, + 0, + 0, + 0, + 0, + 0, + 2, + 3, + 4, + 0, + 0, + 0, + 55340232221129706506, + 13835058055282426626, + 262914, + 262914, + 0, + 2, + 3, + 4, + 0, + 1027, + 3, + 4, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 2, + 3, + 4, + 0, + 0, + 0, + 0, + 6, + 6, + 1051658, + 1051658, + 1, + 2, + 3, + 4, + 0, + 0, + 0, + 1, + 2, + 3, + 4, + 0, + 0, + 0, + 1051658, + 525829, + 525829, + 1, + 2, + 3, + 4, + 0, + 1027, + 3, + 4, + 0, + 0, + 0, + 0, + 1051658, + 1, + 2, + 3, + 4, + 0, + 0, + 0, + 1051658, + 525829, + 1, + 2, + 3, + 4, + 0, + 1027, + 3, + 4, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 2, + 2, + 1, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 36893488147419103231, + 0, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 36893488147419103231, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 2, + 2, + 2, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 36893488147419103231, + 0, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 36893488147419103231, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 2, + 2, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 4, + 4, + 4, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 36893488147419103231, + 0, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 36893488147419103231, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 2, + 2, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 36893488147419103231, + 0, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 36893488147419103231, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 2, + 2, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 4, + 4, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 8, + 8, + 8, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + ], + }, + }, + io: Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }, + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.cd: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::cd.rst", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 2 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.cd.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.cd.rst: CompiledValue { + layout: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + decoded_insns: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + #[hdl(flip)] /* offset = 272 */ + fetch_decode_special_op: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + #[hdl(flip)] /* offset = 2 */ + ready: Bool, + }, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 6, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.decoded_insns[1].ready", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.data", + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + }, + SlotDebugData { + name: "InstantiatedModule(reg_alloc: reg_alloc).reg_alloc::fetch_decode_interface.fetch_decode_special_op.ready", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 4, + debug_data: [ + SlotDebugData { + name: "[0].data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: "[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "[1].data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: "[1].ready", + ty: Bool, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + #[hdl(flip)] /* offset = 135 */ + ready: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: ".ready", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + }, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(4), + }, + ty: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + #[hdl(flip)] /* offset = 2 */ + ready: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".data", + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + }, + SlotDebugData { + name: ".ready", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 6 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface.decoded_insns: CompiledValue { + layout: CompiledTypeLayout { + ty: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 4, + debug_data: [ + SlotDebugData { + name: "[0].data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: "[0].ready", + ty: Bool, + }, + SlotDebugData { + name: "[1].data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: "[1].ready", + ty: Bool, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + #[hdl(flip)] /* offset = 135 */ + ready: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: ".ready", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 4 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface.decoded_insns[0]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + #[hdl(flip)] /* offset = 135 */ + ready: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: ".ready", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 2 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface.decoded_insns[0].data: CompiledValue { + layout: CompiledTypeLayout { + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface.decoded_insns[0].ready: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface.decoded_insns[1]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + #[hdl(flip)] /* offset = 135 */ + ready: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".data", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + SlotDebugData { + name: ".ready", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 2 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface.decoded_insns[1].data: CompiledValue { + layout: CompiledTypeLayout { + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface.decoded_insns[1].ready: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface.fetch_decode_special_op: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + #[hdl(flip)] /* offset = 2 */ + ready: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".data", + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + }, + SlotDebugData { + name: ".ready", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 2 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface.fetch_decode_special_op.data: CompiledValue { + layout: CompiledTypeLayout { + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 1 }, + }, + write: None, + }, + Instance { + name: ::reg_alloc, + instantiated: Module { + name: reg_alloc, + .. + }, + }.fetch_decode_interface.fetch_decode_special_op.ready: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 7, len: 1 }, + }, + write: None, + }, + }, + made_initial_step: true, + needs_settle: true, + trace_decls: TraceModule { + name: "reg_alloc", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "fetch_decode_interface", + child: TraceBundle { + name: "fetch_decode_interface", + fields: [ + TraceArray { + name: "decoded_insns", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceEnumWithFields { + name: "uop", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(3), + name: "$tag", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "AluBranch", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(4), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(5), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(6), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(7), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(8), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(9), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(10), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(11), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(12), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(13), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(14), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(15), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(16), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 61 */ + invert_src0: Bool, + /* offset = 62 */ + invert_carry_in: Bool, + /* offset = 63 */ + invert_carry_out: Bool, + /* offset = 64 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(17), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(18), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(19), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(20), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(21), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(22), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(23), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(24), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(25), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(26), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(27), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(28), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 61 */ + invert_src0: Bool, + /* offset = 62 */ + invert_carry_in: Bool, + /* offset = 63 */ + invert_carry_out: Bool, + /* offset = 64 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(29), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(30), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(31), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(32), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(33), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(34), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(35), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(36), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(37), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 61 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "L2RegisterFile", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(38), + name: "$tag", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "ReadL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(39), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(40), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(41), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(42), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(43), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(44), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(45), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + TraceBundle { + name: "WriteL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(46), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(47), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(48), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(49), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(50), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(51), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(52), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + ], + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "LoadStore", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(53), + name: "$tag", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "Load", + fields: [ + TraceUInt { + location: TraceScalarId(54), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(55), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(56), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(57), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(58), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(59), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(60), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceBundle { + name: "Store", + fields: [ + TraceUInt { + location: TraceScalarId(61), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(62), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(63), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(64), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(65), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(66), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(67), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + ], + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(68), + name: "is_unrelated_pc", + flow: Source, + }, + TraceUInt { + location: TraceScalarId(69), + name: "pc", + ty: UInt<64>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + uop: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + /* offset = 69 */ + is_unrelated_pc: Bool, + /* offset = 70 */ + pc: UInt<64>, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(70), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + #[hdl(flip)] /* offset = 135 */ + ready: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(71), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceEnumWithFields { + name: "uop", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(72), + name: "$tag", + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "AluBranch", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(73), + name: "$tag", + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "AddSub", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(74), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(75), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(76), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(77), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(78), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(79), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(80), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(81), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(82), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(83), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(84), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(85), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 61 */ + invert_src0: Bool, + /* offset = 62 */ + invert_carry_in: Bool, + /* offset = 63 */ + invert_carry_out: Bool, + /* offset = 64 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "AddSubI", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(86), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(87), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(88), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(89), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(90), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(91), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(92), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(93), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(94), + name: "invert_src0", + flow: Source, + }, + TraceBool { + location: TraceScalarId(95), + name: "invert_carry_in", + flow: Source, + }, + TraceBool { + location: TraceScalarId(96), + name: "invert_carry_out", + flow: Source, + }, + TraceBool { + location: TraceScalarId(97), + name: "add_pc", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 61 */ + invert_src0: Bool, + /* offset = 62 */ + invert_carry_in: Bool, + /* offset = 63 */ + invert_carry_out: Bool, + /* offset = 64 */ + add_pc: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "Logical", + fields: [ + TraceBundle { + name: "alu_common", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(98), + name: "prefix_pad", + ty: UInt<0>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(99), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(100), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(101), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(102), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(103), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(104), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceFieldlessEnum { + location: TraceScalarId(105), + name: "output_integer_mode", + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(106), + name: "lut", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + alu_common: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<0>, + /* offset = 0 */ + dest: UInt<8>, + /* offset = 8 */ + src: Array, 3>, + /* offset = 32 */ + imm_low: UInt<25>, + /* offset = 57 */ + imm_sign: SInt<1>, + /* offset = 58 */ + _phantom: Bundle {}, + }, + /* offset = 58 */ + output_integer_mode: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + /* offset = 61 */ + lut: UInt<4>, + }, + flow: Source, + }, + ], + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "L2RegisterFile", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(107), + name: "$tag", + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "ReadL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(108), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(109), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(110), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(111), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(112), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(113), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(114), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + TraceBundle { + name: "WriteL2Reg", + fields: [ + TraceBundle { + name: "common", + fields: [ + TraceUInt { + location: TraceScalarId(115), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(116), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(117), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(118), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(119), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(120), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(121), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + common: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + }, + flow: Source, + }, + ], + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + flow: Source, + }, + TraceEnumWithFields { + name: "LoadStore", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(122), + name: "$tag", + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "Load", + fields: [ + TraceUInt { + location: TraceScalarId(123), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(124), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(125), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(126), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(127), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(128), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(129), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + TraceBundle { + name: "Store", + fields: [ + TraceUInt { + location: TraceScalarId(130), + name: "prefix_pad", + ty: UInt<1>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(131), + name: "dest", + ty: UInt<8>, + flow: Source, + }, + TraceArray { + name: "src", + elements: [ + TraceUInt { + location: TraceScalarId(132), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(133), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(134), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 3>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(135), + name: "imm_low", + ty: UInt<25>, + flow: Source, + }, + TraceSInt { + location: TraceScalarId(136), + name: "imm_sign", + ty: SInt<1>, + flow: Source, + }, + TraceBundle { + name: "_phantom", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + prefix_pad: UInt<1>, + /* offset = 1 */ + dest: UInt<8>, + /* offset = 9 */ + src: Array, 3>, + /* offset = 33 */ + imm_low: UInt<25>, + /* offset = 58 */ + imm_sign: SInt<1>, + /* offset = 59 */ + _phantom: Bundle {}, + }, + flow: Source, + }, + ], + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + flow: Source, + }, + ], + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(137), + name: "is_unrelated_pc", + flow: Source, + }, + TraceUInt { + location: TraceScalarId(138), + name: "pc", + ty: UInt<64>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + uop: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + /* offset = 69 */ + is_unrelated_pc: Bool, + /* offset = 70 */ + pc: UInt<64>, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(139), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + #[hdl(flip)] /* offset = 135 */ + ready: Bool, + }, + flow: Source, + }, + ], + ty: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + flow: Source, + }, + TraceBundle { + name: "fetch_decode_special_op", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(140), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceEnumWithFields { + name: "HdlSome", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(141), + name: "$tag", + ty: Enum { + Trap(Bundle {}), + ICacheFlush, + }, + flow: Source, + }, + non_empty_fields: [ + TraceBundle { + name: "Trap", + fields: [], + ty: Bundle {}, + flow: Source, + }, + ], + ty: Enum { + Trap(Bundle {}), + ICacheFlush, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(142), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + #[hdl(flip)] /* offset = 2 */ + ready: Bool, + }, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + decoded_insns: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + #[hdl(flip)] /* offset = 272 */ + fetch_decode_special_op: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + #[hdl(flip)] /* offset = 2 */ + ready: Bool, + }, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + decoded_insns: Array, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>})}, #[hdl(flip)] ready: Bool}, 2>, + #[hdl(flip)] /* offset = 272 */ + fetch_decode_special_op: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + #[hdl(flip)] /* offset = 2 */ + ready: Bool, + }, + }, + flow: Source, + }, + TraceWire { + name: "available_units", + child: TraceArray { + name: "available_units", + elements: [ + TraceArray { + name: "[0]", + elements: [ + TraceBool { + location: TraceScalarId(143), + name: "[0]", + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + TraceArray { + name: "[1]", + elements: [ + TraceBool { + location: TraceScalarId(144), + name: "[0]", + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ], + ty: Array, 2>, + flow: Duplex, + }, + ty: Array, 2>, + }, + TraceWire { + name: "selected_unit_nums", + child: TraceArray { + name: "selected_unit_nums", + elements: [ + TraceEnumWithFields { + name: "[0]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(145), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceUInt { + location: TraceScalarId(146), + name: "value", + ty: UInt<1>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<1>, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + flow: Duplex, + }, + TraceEnumWithFields { + name: "[1]", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(147), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceUInt { + location: TraceScalarId(148), + name: "value", + ty: UInt<1>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<1>, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + flow: Duplex, + }, + ], + ty: Array})}, 2>, + flow: Duplex, + }, + ty: Array})}, 2>, + }, + TraceWire { + name: "unit_kind", + child: TraceFieldlessEnum { + location: TraceScalarId(149), + name: "unit_kind", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + flow: Duplex, + }, + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + TraceWire { + name: "available_units_for_kind", + child: TraceArray { + name: "available_units_for_kind", + elements: [ + TraceBool { + location: TraceScalarId(150), + name: "[0]", + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ty: Array, + }, + TraceWire { + name: "selected_unit_leaf_0_0", + child: TraceEnumWithFields { + name: "selected_unit_leaf_0_0", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(151), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceUInt { + location: TraceScalarId(152), + name: "value", + ty: UInt<1>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<1>, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + TraceWire { + name: "unit_num_0_0", + child: TraceBundle { + name: "unit_num_0_0", + fields: [ + TraceUInt { + location: TraceScalarId(153), + name: "value", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<1>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<1>, + }, + }, + TraceWire { + name: "unit_kind", + child: TraceFieldlessEnum { + location: TraceScalarId(154), + name: "unit_kind", + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + flow: Duplex, + }, + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + TraceWire { + name: "available_units_for_kind", + child: TraceArray { + name: "available_units_for_kind", + elements: [ + TraceBool { + location: TraceScalarId(155), + name: "[0]", + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ty: Array, + }, + TraceWire { + name: "selected_unit_leaf_1_0", + child: TraceEnumWithFields { + name: "selected_unit_leaf_1_0", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(156), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBundle { + name: "HdlSome", + fields: [ + TraceUInt { + location: TraceScalarId(157), + name: "value", + ty: UInt<1>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<1>, + }, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + TraceWire { + name: "unit_num_1_0", + child: TraceBundle { + name: "unit_num_1_0", + fields: [ + TraceUInt { + location: TraceScalarId(158), + name: "value", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Bundle { + /* offset = 0 */ + value: UInt<1>, + }, + flow: Duplex, + }, + ty: Bundle { + /* offset = 0 */ + value: UInt<1>, + }, + }, + TraceInstance { + name: "unit_0", + instance_io: TraceBundle { + name: "unit_0", + fields: [ + TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(161), + name: "clk", + flow: Sink, + }, + TraceSyncReset { + location: TraceScalarId(162), + name: "rst", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Sink, + }, + ], + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + cd: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + }, + flow: Source, + }, + module: TraceModule { + name: "alu_branch", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(159), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(160), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ], + }, + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + cd: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + }, + }, + TraceInstance { + name: "unit_0_free_regs_tracker", + instance_io: TraceBundle { + name: "unit_0_free_regs_tracker", + fields: [ + TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(236), + name: "clk", + flow: Sink, + }, + TraceSyncReset { + location: TraceScalarId(237), + name: "rst", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Sink, + }, + TraceArray { + name: "free_in", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(238), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(239), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(240), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + #[hdl(flip)] /* offset = 5 */ + ready: Bool, + }, + flow: Sink, + }, + ], + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Sink, + }, + TraceArray { + name: "alloc_out", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(241), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(242), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(243), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + #[hdl(flip)] /* offset = 5 */ + ready: Bool, + }, + flow: Source, + }, + ], + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Source, + }, + ], + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + cd: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + #[hdl(flip)] /* offset = 2 */ + free_in: Array)}, #[hdl(flip)] ready: Bool}, 1>, + /* offset = 8 */ + alloc_out: Array)}, #[hdl(flip)] ready: Bool}, 1>, + }, + flow: Source, + }, + module: TraceModule { + name: "unit_free_regs_tracker", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(163), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(164), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "free_in", + child: TraceArray { + name: "free_in", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(165), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(166), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(167), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + #[hdl(flip)] /* offset = 5 */ + ready: Bool, + }, + flow: Source, + }, + ], + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Source, + }, + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Source, + }, + TraceModuleIO { + name: "alloc_out", + child: TraceArray { + name: "alloc_out", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(168), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(169), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(170), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + #[hdl(flip)] /* offset = 5 */ + ready: Bool, + }, + flow: Sink, + }, + ], + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Sink, + }, + ty: Array)}, #[hdl(flip)] ready: Bool}, 1>, + flow: Sink, + }, + TraceReg { + name: "allocated_reg", + child: TraceArray { + name: "allocated_reg", + elements: [ + TraceBool { + location: TraceScalarId(171), + name: "[0]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(172), + name: "[1]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(173), + name: "[2]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(174), + name: "[3]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(175), + name: "[4]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(176), + name: "[5]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(177), + name: "[6]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(178), + name: "[7]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(179), + name: "[8]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(180), + name: "[9]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(181), + name: "[10]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(182), + name: "[11]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(183), + name: "[12]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(184), + name: "[13]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(185), + name: "[14]", + flow: Duplex, + }, + TraceBool { + location: TraceScalarId(186), + name: "[15]", + flow: Duplex, + }, + ], + ty: Array, + flow: Duplex, + }, + ty: Array, + }, + TraceWire { + name: "firing_data", + child: TraceEnumWithFields { + name: "firing_data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(187), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(188), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + TraceWire { + name: "reduced_count_0_2", + child: TraceUInt { + location: TraceScalarId(189), + name: "reduced_count_0_2", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_0_2", + child: TraceBool { + location: TraceScalarId(190), + name: "reduced_count_overflowed_0_2", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_0_2", + child: TraceArray { + name: "reduced_alloc_nums_0_2", + elements: [ + TraceUInt { + location: TraceScalarId(191), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_2_4", + child: TraceUInt { + location: TraceScalarId(192), + name: "reduced_count_2_4", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_2_4", + child: TraceBool { + location: TraceScalarId(193), + name: "reduced_count_overflowed_2_4", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_2_4", + child: TraceArray { + name: "reduced_alloc_nums_2_4", + elements: [ + TraceUInt { + location: TraceScalarId(194), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_0_4", + child: TraceUInt { + location: TraceScalarId(195), + name: "reduced_count_0_4", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_0_4", + child: TraceBool { + location: TraceScalarId(196), + name: "reduced_count_overflowed_0_4", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_0_4", + child: TraceArray { + name: "reduced_alloc_nums_0_4", + elements: [ + TraceUInt { + location: TraceScalarId(197), + name: "[0]", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_4_6", + child: TraceUInt { + location: TraceScalarId(198), + name: "reduced_count_4_6", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_4_6", + child: TraceBool { + location: TraceScalarId(199), + name: "reduced_count_overflowed_4_6", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_4_6", + child: TraceArray { + name: "reduced_alloc_nums_4_6", + elements: [ + TraceUInt { + location: TraceScalarId(200), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_6_8", + child: TraceUInt { + location: TraceScalarId(201), + name: "reduced_count_6_8", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_6_8", + child: TraceBool { + location: TraceScalarId(202), + name: "reduced_count_overflowed_6_8", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_6_8", + child: TraceArray { + name: "reduced_alloc_nums_6_8", + elements: [ + TraceUInt { + location: TraceScalarId(203), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_4_8", + child: TraceUInt { + location: TraceScalarId(204), + name: "reduced_count_4_8", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_4_8", + child: TraceBool { + location: TraceScalarId(205), + name: "reduced_count_overflowed_4_8", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_4_8", + child: TraceArray { + name: "reduced_alloc_nums_4_8", + elements: [ + TraceUInt { + location: TraceScalarId(206), + name: "[0]", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_0_8", + child: TraceUInt { + location: TraceScalarId(207), + name: "reduced_count_0_8", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_0_8", + child: TraceBool { + location: TraceScalarId(208), + name: "reduced_count_overflowed_0_8", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_0_8", + child: TraceArray { + name: "reduced_alloc_nums_0_8", + elements: [ + TraceUInt { + location: TraceScalarId(209), + name: "[0]", + ty: UInt<3>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_8_10", + child: TraceUInt { + location: TraceScalarId(210), + name: "reduced_count_8_10", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_8_10", + child: TraceBool { + location: TraceScalarId(211), + name: "reduced_count_overflowed_8_10", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_8_10", + child: TraceArray { + name: "reduced_alloc_nums_8_10", + elements: [ + TraceUInt { + location: TraceScalarId(212), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_10_12", + child: TraceUInt { + location: TraceScalarId(213), + name: "reduced_count_10_12", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_10_12", + child: TraceBool { + location: TraceScalarId(214), + name: "reduced_count_overflowed_10_12", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_10_12", + child: TraceArray { + name: "reduced_alloc_nums_10_12", + elements: [ + TraceUInt { + location: TraceScalarId(215), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_8_12", + child: TraceUInt { + location: TraceScalarId(216), + name: "reduced_count_8_12", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_8_12", + child: TraceBool { + location: TraceScalarId(217), + name: "reduced_count_overflowed_8_12", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_8_12", + child: TraceArray { + name: "reduced_alloc_nums_8_12", + elements: [ + TraceUInt { + location: TraceScalarId(218), + name: "[0]", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_12_14", + child: TraceUInt { + location: TraceScalarId(219), + name: "reduced_count_12_14", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_12_14", + child: TraceBool { + location: TraceScalarId(220), + name: "reduced_count_overflowed_12_14", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_12_14", + child: TraceArray { + name: "reduced_alloc_nums_12_14", + elements: [ + TraceUInt { + location: TraceScalarId(221), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_14_16", + child: TraceUInt { + location: TraceScalarId(222), + name: "reduced_count_14_16", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_14_16", + child: TraceBool { + location: TraceScalarId(223), + name: "reduced_count_overflowed_14_16", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_14_16", + child: TraceArray { + name: "reduced_alloc_nums_14_16", + elements: [ + TraceUInt { + location: TraceScalarId(224), + name: "[0]", + ty: UInt<1>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_12_16", + child: TraceUInt { + location: TraceScalarId(225), + name: "reduced_count_12_16", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_12_16", + child: TraceBool { + location: TraceScalarId(226), + name: "reduced_count_overflowed_12_16", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_12_16", + child: TraceArray { + name: "reduced_alloc_nums_12_16", + elements: [ + TraceUInt { + location: TraceScalarId(227), + name: "[0]", + ty: UInt<2>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_8_16", + child: TraceUInt { + location: TraceScalarId(228), + name: "reduced_count_8_16", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_8_16", + child: TraceBool { + location: TraceScalarId(229), + name: "reduced_count_overflowed_8_16", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_8_16", + child: TraceArray { + name: "reduced_alloc_nums_8_16", + elements: [ + TraceUInt { + location: TraceScalarId(230), + name: "[0]", + ty: UInt<3>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "reduced_count_0_16", + child: TraceUInt { + location: TraceScalarId(231), + name: "reduced_count_0_16", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceWire { + name: "reduced_count_overflowed_0_16", + child: TraceBool { + location: TraceScalarId(232), + name: "reduced_count_overflowed_0_16", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "reduced_alloc_nums_0_16", + child: TraceArray { + name: "reduced_alloc_nums_0_16", + elements: [ + TraceUInt { + location: TraceScalarId(233), + name: "[0]", + ty: UInt<4>, + flow: Duplex, + }, + ], + ty: Array, 1>, + flow: Duplex, + }, + ty: Array, 1>, + }, + TraceWire { + name: "firing_data", + child: TraceEnumWithFields { + name: "firing_data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(234), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(235), + name: "HdlSome", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + flow: Duplex, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + ], + }, + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + cd: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + #[hdl(flip)] /* offset = 2 */ + free_in: Array)}, #[hdl(flip)] ready: Bool}, 1>, + /* offset = 8 */ + alloc_out: Array)}, #[hdl(flip)] ready: Bool}, 1>, + }, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(4), + kind: EnumDiscriminant { + index: StatePartIndex(2), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigUInt { + index: StatePartIndex(21), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigUInt { + index: StatePartIndex(23), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(24), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigUInt { + index: StatePartIndex(26), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigSInt { + index: StatePartIndex(27), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(12), + kind: EnumDiscriminant { + index: StatePartIndex(3), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigBool { + index: StatePartIndex(29), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigUInt { + index: StatePartIndex(21), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(23), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigUInt { + index: StatePartIndex(24), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigUInt { + index: StatePartIndex(26), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigSInt { + index: StatePartIndex(27), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: EnumDiscriminant { + index: StatePartIndex(3), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(29), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(74), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(30), + kind: BigUInt { + index: StatePartIndex(75), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(31), + kind: BigUInt { + index: StatePartIndex(76), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(32), + kind: BigUInt { + index: StatePartIndex(77), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(33), + kind: BigUInt { + index: StatePartIndex(78), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(34), + kind: BigUInt { + index: StatePartIndex(79), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(35), + kind: BigSInt { + index: StatePartIndex(80), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(36), + kind: EnumDiscriminant { + index: StatePartIndex(4), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(37), + kind: BigUInt { + index: StatePartIndex(82), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(38), + kind: EnumDiscriminant { + index: StatePartIndex(5), + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(39), + kind: BigUInt { + index: StatePartIndex(86), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(40), + kind: BigUInt { + index: StatePartIndex(87), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(41), + kind: BigUInt { + index: StatePartIndex(88), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(42), + kind: BigUInt { + index: StatePartIndex(89), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(43), + kind: BigUInt { + index: StatePartIndex(90), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(44), + kind: BigUInt { + index: StatePartIndex(91), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(45), + kind: BigSInt { + index: StatePartIndex(92), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(46), + kind: BigUInt { + index: StatePartIndex(86), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(47), + kind: BigUInt { + index: StatePartIndex(87), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(48), + kind: BigUInt { + index: StatePartIndex(88), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(49), + kind: BigUInt { + index: StatePartIndex(89), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(50), + kind: BigUInt { + index: StatePartIndex(90), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(51), + kind: BigUInt { + index: StatePartIndex(91), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(52), + kind: BigSInt { + index: StatePartIndex(92), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(53), + kind: EnumDiscriminant { + index: StatePartIndex(6), + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(54), + kind: BigUInt { + index: StatePartIndex(116), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(55), + kind: BigUInt { + index: StatePartIndex(117), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(56), + kind: BigUInt { + index: StatePartIndex(118), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(57), + kind: BigUInt { + index: StatePartIndex(119), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(58), + kind: BigUInt { + index: StatePartIndex(120), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(59), + kind: BigUInt { + index: StatePartIndex(121), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(60), + kind: BigSInt { + index: StatePartIndex(122), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(61), + kind: BigUInt { + index: StatePartIndex(116), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(62), + kind: BigUInt { + index: StatePartIndex(117), + ty: UInt<8>, + }, + state: 0x01, + last_state: 0x01, + }, + SimTrace { + id: TraceScalarId(63), + kind: BigUInt { + index: StatePartIndex(118), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(64), + kind: BigUInt { + index: StatePartIndex(119), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(65), + kind: BigUInt { + index: StatePartIndex(120), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(66), + kind: BigUInt { + index: StatePartIndex(121), + ty: UInt<25>, + }, + state: 0x0001234, + last_state: 0x0001234, + }, + SimTrace { + id: TraceScalarId(67), + kind: BigSInt { + index: StatePartIndex(122), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(68), + kind: BigBool { + index: StatePartIndex(9), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(69), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<64>, + }, + state: 0x0000000000001000, + last_state: 0x0000000000001000, + }, + SimTrace { + id: TraceScalarId(70), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(71), + kind: EnumDiscriminant { + index: StatePartIndex(7), + ty: Enum { + HdlNone, + HdlSome(Bundle {uop: Enum {AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})})}, is_unrelated_pc: Bool, pc: UInt<64>}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(72), + kind: EnumDiscriminant { + index: StatePartIndex(8), + ty: Enum { + AluBranch(Enum {AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>})}), + L2RegisterFile(Enum {ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}})}), + LoadStore(Enum {Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}})}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(73), + kind: EnumDiscriminant { + index: StatePartIndex(9), + ty: Enum { + AddSub(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + AddSubI(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, invert_src0: Bool, invert_carry_in: Bool, invert_carry_out: Bool, add_pc: Bool}), + Logical(Bundle {alu_common: Bundle {common: Bundle {prefix_pad: UInt<0>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}, output_integer_mode: Enum {Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8}}, lut: UInt<4>}), + }, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(74), + kind: BigUInt { + index: StatePartIndex(150), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(75), + kind: BigUInt { + index: StatePartIndex(151), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(76), + kind: BigUInt { + index: StatePartIndex(152), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(77), + kind: BigUInt { + index: StatePartIndex(153), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(78), + kind: BigUInt { + index: StatePartIndex(154), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(79), + kind: BigUInt { + index: StatePartIndex(155), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(80), + kind: BigSInt { + index: StatePartIndex(156), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(81), + kind: EnumDiscriminant { + index: StatePartIndex(10), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(82), + kind: BigBool { + index: StatePartIndex(158), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(83), + kind: BigBool { + index: StatePartIndex(159), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(84), + kind: BigBool { + index: StatePartIndex(160), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(85), + kind: BigBool { + index: StatePartIndex(161), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(86), + kind: BigUInt { + index: StatePartIndex(150), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(87), + kind: BigUInt { + index: StatePartIndex(151), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(88), + kind: BigUInt { + index: StatePartIndex(152), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(89), + kind: BigUInt { + index: StatePartIndex(153), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(90), + kind: BigUInt { + index: StatePartIndex(154), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(91), + kind: BigUInt { + index: StatePartIndex(155), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(92), + kind: BigSInt { + index: StatePartIndex(156), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(93), + kind: EnumDiscriminant { + index: StatePartIndex(10), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(94), + kind: BigBool { + index: StatePartIndex(158), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(95), + kind: BigBool { + index: StatePartIndex(159), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(96), + kind: BigBool { + index: StatePartIndex(160), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(97), + kind: BigBool { + index: StatePartIndex(161), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(98), + kind: BigUInt { + index: StatePartIndex(203), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(99), + kind: BigUInt { + index: StatePartIndex(204), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(100), + kind: BigUInt { + index: StatePartIndex(205), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(101), + kind: BigUInt { + index: StatePartIndex(206), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(102), + kind: BigUInt { + index: StatePartIndex(207), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(103), + kind: BigUInt { + index: StatePartIndex(208), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(104), + kind: BigSInt { + index: StatePartIndex(209), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(105), + kind: EnumDiscriminant { + index: StatePartIndex(11), + ty: Enum { + Full64, + DupLow32, + ZeroExt32, + SignExt32, + ZeroExt16, + SignExt16, + ZeroExt8, + SignExt8, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(106), + kind: BigUInt { + index: StatePartIndex(211), + ty: UInt<4>, + }, + state: 0x6, + last_state: 0x6, + }, + SimTrace { + id: TraceScalarId(107), + kind: EnumDiscriminant { + index: StatePartIndex(12), + ty: Enum { + ReadL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + WriteL2Reg(Bundle {common: Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(108), + kind: BigUInt { + index: StatePartIndex(215), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(109), + kind: BigUInt { + index: StatePartIndex(216), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(110), + kind: BigUInt { + index: StatePartIndex(217), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(111), + kind: BigUInt { + index: StatePartIndex(218), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(112), + kind: BigUInt { + index: StatePartIndex(219), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(113), + kind: BigUInt { + index: StatePartIndex(220), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(114), + kind: BigSInt { + index: StatePartIndex(221), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(115), + kind: BigUInt { + index: StatePartIndex(215), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(116), + kind: BigUInt { + index: StatePartIndex(216), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(117), + kind: BigUInt { + index: StatePartIndex(217), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(118), + kind: BigUInt { + index: StatePartIndex(218), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(119), + kind: BigUInt { + index: StatePartIndex(219), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(120), + kind: BigUInt { + index: StatePartIndex(220), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(121), + kind: BigSInt { + index: StatePartIndex(221), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(122), + kind: EnumDiscriminant { + index: StatePartIndex(13), + ty: Enum { + Load(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + Store(Bundle {prefix_pad: UInt<1>, dest: UInt<8>, src: Array, 3>, imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Bundle {}}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(123), + kind: BigUInt { + index: StatePartIndex(245), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(124), + kind: BigUInt { + index: StatePartIndex(246), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(125), + kind: BigUInt { + index: StatePartIndex(247), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(126), + kind: BigUInt { + index: StatePartIndex(248), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(127), + kind: BigUInt { + index: StatePartIndex(249), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(128), + kind: BigUInt { + index: StatePartIndex(250), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(129), + kind: BigSInt { + index: StatePartIndex(251), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(130), + kind: BigUInt { + index: StatePartIndex(245), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(131), + kind: BigUInt { + index: StatePartIndex(246), + ty: UInt<8>, + }, + state: 0x02, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(132), + kind: BigUInt { + index: StatePartIndex(247), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + SimTrace { + id: TraceScalarId(133), + kind: BigUInt { + index: StatePartIndex(248), + ty: UInt<8>, + }, + state: 0x04, + last_state: 0x04, + }, + SimTrace { + id: TraceScalarId(134), + kind: BigUInt { + index: StatePartIndex(249), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(135), + kind: BigUInt { + index: StatePartIndex(250), + ty: UInt<25>, + }, + state: 0x0000000, + last_state: 0x0000000, + }, + SimTrace { + id: TraceScalarId(136), + kind: BigSInt { + index: StatePartIndex(251), + ty: SInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(137), + kind: BigBool { + index: StatePartIndex(138), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(138), + kind: BigUInt { + index: StatePartIndex(139), + ty: UInt<64>, + }, + state: 0x0000000000001004, + last_state: 0x0000000000001004, + }, + SimTrace { + id: TraceScalarId(139), + kind: BigBool { + index: StatePartIndex(5), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(140), + kind: EnumDiscriminant { + index: StatePartIndex(14), + ty: Enum { + HdlNone, + HdlSome(Enum {Trap(Bundle {}), ICacheFlush}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(141), + kind: EnumDiscriminant { + index: StatePartIndex(15), + ty: Enum { + Trap(Bundle {}), + ICacheFlush, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(142), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(143), + kind: BigBool { + index: StatePartIndex(271), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(144), + kind: BigBool { + index: StatePartIndex(272), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(145), + kind: EnumDiscriminant { + index: StatePartIndex(16), + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(146), + kind: BigUInt { + index: StatePartIndex(275), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(147), + kind: EnumDiscriminant { + index: StatePartIndex(17), + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(148), + kind: BigUInt { + index: StatePartIndex(279), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(149), + kind: EnumDiscriminant { + index: StatePartIndex(18), + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(150), + kind: BigBool { + index: StatePartIndex(292), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(151), + kind: EnumDiscriminant { + index: StatePartIndex(19), + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(152), + kind: BigUInt { + index: StatePartIndex(294), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(153), + kind: BigUInt { + index: StatePartIndex(299), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(154), + kind: EnumDiscriminant { + index: StatePartIndex(20), + ty: Enum { + AluBranch, + L2RegisterFile, + LoadStore, + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(155), + kind: BigBool { + index: StatePartIndex(310), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(156), + kind: EnumDiscriminant { + index: StatePartIndex(21), + ty: Enum { + HdlNone, + HdlSome(Bundle {value: UInt<1>}), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(157), + kind: BigUInt { + index: StatePartIndex(312), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(158), + kind: BigUInt { + index: StatePartIndex(316), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(159), + kind: BigClock { + index: StatePartIndex(325), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(160), + kind: BigSyncReset { + index: StatePartIndex(326), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(161), + kind: BigClock { + index: StatePartIndex(323), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(162), + kind: BigSyncReset { + index: StatePartIndex(324), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(163), + kind: BigClock { + index: StatePartIndex(333), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(164), + kind: BigSyncReset { + index: StatePartIndex(334), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(165), + kind: EnumDiscriminant { + index: StatePartIndex(23), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(166), + kind: BigUInt { + index: StatePartIndex(338), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(167), + kind: BigBool { + index: StatePartIndex(336), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(168), + kind: EnumDiscriminant { + index: StatePartIndex(24), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(169), + kind: BigUInt { + index: StatePartIndex(342), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(170), + kind: BigBool { + index: StatePartIndex(340), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(171), + kind: BigBool { + index: StatePartIndex(343), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(172), + kind: BigBool { + index: StatePartIndex(344), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(173), + kind: BigBool { + index: StatePartIndex(345), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(174), + kind: BigBool { + index: StatePartIndex(346), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(175), + kind: BigBool { + index: StatePartIndex(347), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(176), + kind: BigBool { + index: StatePartIndex(348), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(177), + kind: BigBool { + index: StatePartIndex(349), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(178), + kind: BigBool { + index: StatePartIndex(350), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(179), + kind: BigBool { + index: StatePartIndex(351), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(180), + kind: BigBool { + index: StatePartIndex(352), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(181), + kind: BigBool { + index: StatePartIndex(353), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(182), + kind: BigBool { + index: StatePartIndex(354), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(183), + kind: BigBool { + index: StatePartIndex(355), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(184), + kind: BigBool { + index: StatePartIndex(356), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(185), + kind: BigBool { + index: StatePartIndex(357), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(186), + kind: BigBool { + index: StatePartIndex(358), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(187), + kind: EnumDiscriminant { + index: StatePartIndex(29), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(188), + kind: BigUInt { + index: StatePartIndex(393), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(189), + kind: BigUInt { + index: StatePartIndex(396), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(190), + kind: BigBool { + index: StatePartIndex(405), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(191), + kind: BigUInt { + index: StatePartIndex(409), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(192), + kind: BigUInt { + index: StatePartIndex(420), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(193), + kind: BigBool { + index: StatePartIndex(429), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(194), + kind: BigUInt { + index: StatePartIndex(433), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(195), + kind: BigUInt { + index: StatePartIndex(440), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(196), + kind: BigBool { + index: StatePartIndex(443), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(197), + kind: BigUInt { + index: StatePartIndex(447), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(198), + kind: BigUInt { + index: StatePartIndex(456), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(199), + kind: BigBool { + index: StatePartIndex(465), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(200), + kind: BigUInt { + index: StatePartIndex(469), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(201), + kind: BigUInt { + index: StatePartIndex(476), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(202), + kind: BigBool { + index: StatePartIndex(485), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(203), + kind: BigUInt { + index: StatePartIndex(489), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(204), + kind: BigUInt { + index: StatePartIndex(496), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(205), + kind: BigBool { + index: StatePartIndex(499), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(206), + kind: BigUInt { + index: StatePartIndex(503), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(207), + kind: BigUInt { + index: StatePartIndex(511), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(208), + kind: BigBool { + index: StatePartIndex(514), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(209), + kind: BigUInt { + index: StatePartIndex(518), + ty: UInt<3>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(210), + kind: BigUInt { + index: StatePartIndex(527), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(211), + kind: BigBool { + index: StatePartIndex(536), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(212), + kind: BigUInt { + index: StatePartIndex(540), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(213), + kind: BigUInt { + index: StatePartIndex(547), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(214), + kind: BigBool { + index: StatePartIndex(556), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(215), + kind: BigUInt { + index: StatePartIndex(560), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(216), + kind: BigUInt { + index: StatePartIndex(567), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(217), + kind: BigBool { + index: StatePartIndex(570), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(218), + kind: BigUInt { + index: StatePartIndex(574), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(219), + kind: BigUInt { + index: StatePartIndex(582), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(220), + kind: BigBool { + index: StatePartIndex(591), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(221), + kind: BigUInt { + index: StatePartIndex(595), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(222), + kind: BigUInt { + index: StatePartIndex(602), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(223), + kind: BigBool { + index: StatePartIndex(611), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(224), + kind: BigUInt { + index: StatePartIndex(615), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(225), + kind: BigUInt { + index: StatePartIndex(622), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(226), + kind: BigBool { + index: StatePartIndex(625), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(227), + kind: BigUInt { + index: StatePartIndex(629), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(228), + kind: BigUInt { + index: StatePartIndex(637), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(229), + kind: BigBool { + index: StatePartIndex(640), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(230), + kind: BigUInt { + index: StatePartIndex(644), + ty: UInt<3>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(231), + kind: BigUInt { + index: StatePartIndex(652), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(232), + kind: BigBool { + index: StatePartIndex(655), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(233), + kind: BigUInt { + index: StatePartIndex(659), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(234), + kind: EnumDiscriminant { + index: StatePartIndex(46), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(235), + kind: BigUInt { + index: StatePartIndex(670), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(236), + kind: BigClock { + index: StatePartIndex(327), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(237), + kind: BigSyncReset { + index: StatePartIndex(328), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(238), + kind: EnumDiscriminant { + index: StatePartIndex(48), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(239), + kind: BigUInt { + index: StatePartIndex(680), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(240), + kind: BigBool { + index: StatePartIndex(330), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(241), + kind: EnumDiscriminant { + index: StatePartIndex(49), + ty: Enum { + HdlNone, + HdlSome(UInt<4>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(242), + kind: BigUInt { + index: StatePartIndex(682), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(243), + kind: BigBool { + index: StatePartIndex(332), + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + instant: 10 μs, + clocks_triggered: [ + StatePartIndex(26), + ], + .. +} \ No newline at end of file diff --git a/crates/cpu/tests/expected/reg_alloc.vcd b/crates/cpu/tests/expected/reg_alloc.vcd index 1012150..7642a58 100644 --- a/crates/cpu/tests/expected/reg_alloc.vcd +++ b/crates/cpu/tests/expected/reg_alloc.vcd @@ -327,26 +327,26 @@ $var string 1 X" unit_kind $end $scope struct available_units_for_kind $end $var wire 1 Y" \[0] $end $upscope $end -$scope struct selected_unit_leaf $end +$scope struct selected_unit_leaf_0_0 $end $var string 1 Z" \$tag $end $scope struct HdlSome $end $var wire 1 [" value $end $upscope $end $upscope $end -$scope struct unit_num $end +$scope struct unit_num_0_0 $end $var wire 1 \" value $end $upscope $end $var string 1 ]" unit_kind_2 $end $scope struct available_units_for_kind_2 $end $var wire 1 ^" \[0] $end $upscope $end -$scope struct selected_unit_leaf_2 $end +$scope struct selected_unit_leaf_1_0 $end $var string 1 _" \$tag $end $scope struct HdlSome $end $var wire 1 `" value $end $upscope $end $upscope $end -$scope struct unit_num_2 $end +$scope struct unit_num_1_0 $end $var wire 1 a" value $end $upscope $end $scope struct unit_0 $end @@ -657,10 +657,10 @@ sHdlNone\x20(0) O" sTrap\x20(0) P" 1Q" 1R" -1S" +0S" sHdlSome\x20(1) T" 0U" -sHdlSome\x20(1) V" +sHdlNone\x20(0) V" 0W" sAluBranch\x20(0) X" 1Y" @@ -669,7 +669,7 @@ sHdlSome\x20(1) Z" 0\" sAluBranch\x20(0) ]" 1^" -sHdlSome\x20(1) _" +sHdlNone\x20(0) _" 0`" 0a" 0b" diff --git a/crates/cpu/tests/reg_alloc.rs b/crates/cpu/tests/reg_alloc.rs index 975a73e..f38081b 100644 --- a/crates/cpu/tests/reg_alloc.rs +++ b/crates/cpu/tests/reg_alloc.rs @@ -11,6 +11,8 @@ use cpu::{ unit::UnitKind, }; use fayalite::{ + assert_export_firrtl, + firrtl::ExportOptions, prelude::*, sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation}, util::RcWriter, @@ -23,7 +25,8 @@ fn test_reg_alloc() { let _n = SourceLocation::normalize_files_for_tests(); let mut config = CpuConfig::new(vec![UnitKind::AluBranch]); config.fetch_width = NonZeroUsize::new(2).unwrap(); - let mut sim = Simulation::new(reg_alloc(&config)); + let m = reg_alloc(&config); + let mut sim = Simulation::new(m); let mut writer = RcWriter::default(); sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); let fetch_decode_interface = sim.io().fetch_decode_interface; @@ -98,4 +101,487 @@ fn test_reg_alloc() { if vcd != include_str!("expected/reg_alloc.vcd") { panic!(); } + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_enums: None, + ..ExportOptions::default() + }, + "/test/reg_alloc.fir": r"FIRRTL version 3.2.0 +circuit reg_alloc: + type Ty0 = {clk: Clock, rst: Reset} + type Ty1 = {} + type Ty2 = {prefix_pad: UInt<0>, dest: UInt<8>, src: UInt<8>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty1} + type Ty3 = {|Full64, DupLow32, ZeroExt32, SignExt32, ZeroExt16, SignExt16, ZeroExt8, SignExt8|} + type Ty4 = {common: Ty2, output_integer_mode: Ty3} + type Ty5 = {alu_common: Ty4, invert_src0: UInt<1>, invert_carry_in: UInt<1>, invert_carry_out: UInt<1>, add_pc: UInt<1>} + type Ty6 = {alu_common: Ty4, lut: UInt<4>} + type Ty7 = {|AddSub: Ty5, AddSubI: Ty5, Logical: Ty6|} + type Ty8 = {prefix_pad: UInt<1>, dest: UInt<8>, src: UInt<8>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty1} + type Ty9 = {common: Ty8} + type Ty10 = {|ReadL2Reg: Ty9, WriteL2Reg: Ty9|} + type Ty11 = {|Load: Ty8, Store: Ty8|} + type Ty12 = {|AluBranch: Ty7, L2RegisterFile: Ty10, LoadStore: Ty11|} + type Ty13 = {uop: Ty12, is_unrelated_pc: UInt<1>, pc: UInt<64>} + type Ty14 = {|HdlNone, HdlSome: Ty13|} + type Ty15 = {data: Ty14, flip ready: UInt<1>} + type Ty16 = {|Trap: Ty1, ICacheFlush|} + type Ty17 = {|HdlNone, HdlSome: Ty16|} + type Ty18 = {data: Ty17, flip ready: UInt<1>} + type Ty19 = {decoded_insns: Ty15[2], flip fetch_decode_special_op: Ty18} + type Ty20 = {value: UInt<1>} + type Ty21 = {|HdlNone, HdlSome: Ty20|} + type Ty22 = {|AluBranch, L2RegisterFile, LoadStore|} + type Ty23 = {flip cd: Ty0} + type Ty24 = {|HdlNone, HdlSome: UInt<4>|} + type Ty25 = {data: Ty24, flip ready: UInt<1>} + type Ty26 = {flip cd: Ty0, flip free_in: Ty25[1], alloc_out: Ty25[1]} + module reg_alloc: @[reg_alloc.rs 41:1] + input cd: Ty0 @[reg_alloc.rs 45:29] + input fetch_decode_interface: Ty19 @[reg_alloc.rs 48:11] + connect fetch_decode_interface.fetch_decode_special_op.data, {|HdlNone, HdlSome: Ty16|}(HdlNone) @[reg_alloc.rs 50:5] + wire available_units: UInt<1>[1][2] @[reg_alloc.rs 57:9] + wire selected_unit_nums: Ty21[2] @[reg_alloc.rs 59:30] + connect fetch_decode_interface.decoded_insns[0].ready, UInt<1>(0h1) @[reg_alloc.rs 61:9] + wire _array_literal_expr: UInt<1>[1] + connect _array_literal_expr[0], UInt<1>(0h0) + connect available_units[0], _array_literal_expr @[reg_alloc.rs 65:9] + match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 70:9] + HdlNone: + skip + HdlSome(_match_arm_value): + wire unit_kind: Ty22 @[unit.rs 107:1] + match _match_arm_value.uop: @[unit.rs 107:1] + AluBranch(_match_arm_value_1): + connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 107:1] + L2RegisterFile(_match_arm_value_2): + connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 107:1] + LoadStore(_match_arm_value_3): + connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 107:1] + wire available_units_for_kind: UInt<1>[1] @[unit.rs 107:1] + match unit_kind: @[unit.rs 107:1] + AluBranch: + connect available_units_for_kind[0], UInt<1>(0h1) @[unit.rs 107:1] + L2RegisterFile: + connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 107:1] + LoadStore: + connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 107:1] + connect available_units[0], available_units_for_kind @[reg_alloc.rs 71:13] + wire selected_unit_leaf_0_0: Ty21 @[reg_alloc.rs 84:25] + connect selected_unit_leaf_0_0, {|HdlNone, HdlSome: Ty20|}(HdlNone) @[reg_alloc.rs 87:21] + wire unit_num_0_0: Ty20 @[reg_alloc.rs 90:25] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<64> + connect unit_num_0_0.value, UInt<64>(0h0) @[reg_alloc.rs 93:21] + when available_units[0][0]: @[reg_alloc.rs 95:21] + connect selected_unit_leaf_0_0, {|HdlNone, HdlSome: Ty20|}(HdlSome, unit_num_0_0) @[reg_alloc.rs 96:25] + connect selected_unit_nums[0], selected_unit_leaf_0_0 @[reg_alloc.rs 76:9] + connect fetch_decode_interface.decoded_insns[1].ready, UInt<1>(0h1) @[reg_alloc.rs 61:9] + wire _array_literal_expr_1: UInt<1>[1] + connect _array_literal_expr_1[0], UInt<1>(0h0) + connect available_units[1], _array_literal_expr_1 @[reg_alloc.rs 65:9] + match fetch_decode_interface.decoded_insns[1].data: @[reg_alloc.rs 70:9] + HdlNone: + skip + HdlSome(_match_arm_value_4): + wire unit_kind_1: Ty22 @[unit.rs 107:1] + match _match_arm_value_4.uop: @[unit.rs 107:1] + AluBranch(_match_arm_value_5): + connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 107:1] + L2RegisterFile(_match_arm_value_6): + connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 107:1] + LoadStore(_match_arm_value_7): + connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 107:1] + wire available_units_for_kind_1: UInt<1>[1] @[unit.rs 107:1] + match unit_kind_1: @[unit.rs 107:1] + AluBranch: + connect available_units_for_kind_1[0], UInt<1>(0h1) @[unit.rs 107:1] + L2RegisterFile: + connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 107:1] + LoadStore: + connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 107:1] + connect available_units[1], available_units_for_kind_1 @[reg_alloc.rs 71:13] + wire selected_unit_leaf_1_0: Ty21 @[reg_alloc.rs 84:25] + connect selected_unit_leaf_1_0, {|HdlNone, HdlSome: Ty20|}(HdlNone) @[reg_alloc.rs 87:21] + wire unit_num_1_0: Ty20 @[reg_alloc.rs 90:25] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<64> + connect unit_num_1_0.value, UInt<64>(0h0) @[reg_alloc.rs 93:21] + when available_units[1][0]: @[reg_alloc.rs 95:21] + connect selected_unit_leaf_1_0, {|HdlNone, HdlSome: Ty20|}(HdlSome, unit_num_1_0) @[reg_alloc.rs 96:25] + connect selected_unit_nums[1], selected_unit_leaf_1_0 @[reg_alloc.rs 76:9] + match selected_unit_nums[0]: @[reg_alloc.rs 123:13] + HdlNone: + skip + HdlSome(_match_arm_value_8): + connect available_units[1][_match_arm_value_8.value], UInt<1>(0h0) @[reg_alloc.rs 124:17] + inst unit_0 of alu_branch @[reg_alloc.rs 136:13] + connect unit_0.cd, cd @[reg_alloc.rs 138:9] + inst unit_0_free_regs_tracker of unit_free_regs_tracker @[reg_alloc.rs 150:13] + connect unit_0_free_regs_tracker.cd, cd @[reg_alloc.rs 152:9] + wire _uninit_expr: Ty24 + invalidate _uninit_expr + connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr @[reg_alloc.rs 154:9] + wire _uninit_expr_1: UInt<1> + invalidate _uninit_expr_1 + connect unit_0_free_regs_tracker.alloc_out[0].ready, _uninit_expr_1 @[reg_alloc.rs 158:9] + module alu_branch: @[alu_branch.rs 15:1] + input cd: Ty0 @[alu_branch.rs 18:29] + module unit_free_regs_tracker: @[unit_free_regs_tracker.rs 7:1] + input cd: Ty0 @[unit_free_regs_tracker.rs 14:29] + input free_in: Ty25[1] @[unit_free_regs_tracker.rs 17:11] + output alloc_out: Ty25[1] @[unit_free_regs_tracker.rs 20:11] + wire _array_literal_expr: UInt<1>[16] + connect _array_literal_expr[0], UInt<1>(0h0) + connect _array_literal_expr[1], UInt<1>(0h0) + connect _array_literal_expr[2], UInt<1>(0h0) + connect _array_literal_expr[3], UInt<1>(0h0) + connect _array_literal_expr[4], UInt<1>(0h0) + connect _array_literal_expr[5], UInt<1>(0h0) + connect _array_literal_expr[6], UInt<1>(0h0) + connect _array_literal_expr[7], UInt<1>(0h0) + connect _array_literal_expr[8], UInt<1>(0h0) + connect _array_literal_expr[9], UInt<1>(0h0) + connect _array_literal_expr[10], UInt<1>(0h0) + connect _array_literal_expr[11], UInt<1>(0h0) + connect _array_literal_expr[12], UInt<1>(0h0) + connect _array_literal_expr[13], UInt<1>(0h0) + connect _array_literal_expr[14], UInt<1>(0h0) + connect _array_literal_expr[15], UInt<1>(0h0) + regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25] + connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9] + wire firing_data: Ty24 @[ready_valid.rs 30:27] + connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] + when free_in[0].ready: @[ready_valid.rs 33:9] + connect firing_data, free_in[0].data @[ready_valid.rs 34:13] + match firing_data: @[unit_free_regs_tracker.rs 31:9] + HdlNone: + skip + HdlSome(_match_arm_value): + connect allocated_reg[_match_arm_value], UInt<1>(0h0) @[unit_free_regs_tracker.rs 32:13] + wire reduced_count_0_2: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_0_2, add(not(allocated_reg[0]), not(allocated_reg[1])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_0_2: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_0_2, or(or(neq(add(not(allocated_reg[0]), not(allocated_reg[1])), reduced_count_0_2), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_0_2: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[0]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_1: UInt<0>[1] + connect _array_literal_expr_1[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_0_2[0], _array_literal_expr_1[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_2: UInt<0>[1] + connect _array_literal_expr_2[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_0_2[0], add(_array_literal_expr_2[sub(UInt<64>(0h0), not(allocated_reg[0]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_2_4: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_2_4, add(not(allocated_reg[2]), not(allocated_reg[3])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_2_4: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_2_4, or(or(neq(add(not(allocated_reg[2]), not(allocated_reg[3])), reduced_count_2_4), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_2_4: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[2]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_3: UInt<0>[1] + connect _array_literal_expr_3[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_2_4[0], _array_literal_expr_3[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_4: UInt<0>[1] + connect _array_literal_expr_4[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_2_4[0], add(_array_literal_expr_4[sub(UInt<64>(0h0), not(allocated_reg[2]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_0_4: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_0_4, add(reduced_count_0_2, reduced_count_2_4) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_0_4: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_0_4, or(or(neq(add(reduced_count_0_2, reduced_count_2_4), reduced_count_0_4), reduced_count_overflowed_0_2), reduced_count_overflowed_2_4) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_0_4: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_0_2, gt(reduced_count_0_2, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<1> + connect reduced_alloc_nums_0_4[0], reduced_alloc_nums_0_2[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<65> + connect reduced_alloc_nums_0_4[0], add(reduced_alloc_nums_2_4[sub(UInt<64>(0h0), reduced_count_0_2)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_4_6: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_4_6, add(not(allocated_reg[4]), not(allocated_reg[5])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_4_6: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_4_6, or(or(neq(add(not(allocated_reg[4]), not(allocated_reg[5])), reduced_count_4_6), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_4_6: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[4]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_5: UInt<0>[1] + connect _array_literal_expr_5[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_4_6[0], _array_literal_expr_5[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_6: UInt<0>[1] + connect _array_literal_expr_6[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_4_6[0], add(_array_literal_expr_6[sub(UInt<64>(0h0), not(allocated_reg[4]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_6_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_6_8, add(not(allocated_reg[6]), not(allocated_reg[7])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_6_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_6_8, or(or(neq(add(not(allocated_reg[6]), not(allocated_reg[7])), reduced_count_6_8), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_6_8: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[6]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_7: UInt<0>[1] + connect _array_literal_expr_7[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_6_8[0], _array_literal_expr_7[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_8: UInt<0>[1] + connect _array_literal_expr_8[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_6_8[0], add(_array_literal_expr_8[sub(UInt<64>(0h0), not(allocated_reg[6]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_4_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_4_8, add(reduced_count_4_6, reduced_count_6_8) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_4_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_4_8, or(or(neq(add(reduced_count_4_6, reduced_count_6_8), reduced_count_4_8), reduced_count_overflowed_4_6), reduced_count_overflowed_6_8) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_4_8: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_4_6, gt(reduced_count_4_6, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<1> + connect reduced_alloc_nums_4_8[0], reduced_alloc_nums_4_6[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<65> + connect reduced_alloc_nums_4_8[0], add(reduced_alloc_nums_6_8[sub(UInt<64>(0h0), reduced_count_4_6)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_0_8: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_0_8, add(reduced_count_0_4, reduced_count_4_8) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_0_8: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_0_8, or(or(neq(add(reduced_count_0_4, reduced_count_4_8), reduced_count_0_8), reduced_count_overflowed_0_4), reduced_count_overflowed_4_8) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_0_8: UInt<3>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_0_4, gt(reduced_count_0_4, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<3> + ; rhs: UInt<2> + connect reduced_alloc_nums_0_8[0], reduced_alloc_nums_0_4[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<3> + ; rhs: UInt<65> + connect reduced_alloc_nums_0_8[0], add(reduced_alloc_nums_4_8[sub(UInt<64>(0h0), reduced_count_0_4)], UInt<64>(0h4)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_8_10: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_8_10, add(not(allocated_reg[8]), not(allocated_reg[9])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_8_10: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_8_10, or(or(neq(add(not(allocated_reg[8]), not(allocated_reg[9])), reduced_count_8_10), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_8_10: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[8]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_9: UInt<0>[1] + connect _array_literal_expr_9[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_8_10[0], _array_literal_expr_9[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_10: UInt<0>[1] + connect _array_literal_expr_10[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_8_10[0], add(_array_literal_expr_10[sub(UInt<64>(0h0), not(allocated_reg[8]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_10_12: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_10_12, add(not(allocated_reg[10]), not(allocated_reg[11])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_10_12: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_10_12, or(or(neq(add(not(allocated_reg[10]), not(allocated_reg[11])), reduced_count_10_12), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_10_12: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[10]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_11: UInt<0>[1] + connect _array_literal_expr_11[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_10_12[0], _array_literal_expr_11[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_12: UInt<0>[1] + connect _array_literal_expr_12[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_10_12[0], add(_array_literal_expr_12[sub(UInt<64>(0h0), not(allocated_reg[10]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_8_12: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_8_12, add(reduced_count_8_10, reduced_count_10_12) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_8_12: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_8_12, or(or(neq(add(reduced_count_8_10, reduced_count_10_12), reduced_count_8_12), reduced_count_overflowed_8_10), reduced_count_overflowed_10_12) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_8_12: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_8_10, gt(reduced_count_8_10, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<1> + connect reduced_alloc_nums_8_12[0], reduced_alloc_nums_8_10[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<65> + connect reduced_alloc_nums_8_12[0], add(reduced_alloc_nums_10_12[sub(UInt<64>(0h0), reduced_count_8_10)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_12_14: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_12_14, add(not(allocated_reg[12]), not(allocated_reg[13])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_12_14: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_12_14, or(or(neq(add(not(allocated_reg[12]), not(allocated_reg[13])), reduced_count_12_14), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_12_14: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[12]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_13: UInt<0>[1] + connect _array_literal_expr_13[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_12_14[0], _array_literal_expr_13[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_14: UInt<0>[1] + connect _array_literal_expr_14[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_12_14[0], add(_array_literal_expr_14[sub(UInt<64>(0h0), not(allocated_reg[12]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_14_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_14_16, add(not(allocated_reg[14]), not(allocated_reg[15])) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_14_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_14_16, or(or(neq(add(not(allocated_reg[14]), not(allocated_reg[15])), reduced_count_14_16), UInt<1>(0h0)), UInt<1>(0h0)) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_14_16: UInt<1>[1] @[unit_free_regs_tracker.rs 75:17] + when or(UInt<1>(0h0), gt(not(allocated_reg[14]), UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + wire _array_literal_expr_15: UInt<0>[1] + connect _array_literal_expr_15[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<0> + connect reduced_alloc_nums_14_16[0], _array_literal_expr_15[0] @[unit_free_regs_tracker.rs 81:21] + else: + wire _array_literal_expr_16: UInt<0>[1] + connect _array_literal_expr_16[0], UInt<0>(0h0) + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<65> + connect reduced_alloc_nums_14_16[0], add(_array_literal_expr_16[sub(UInt<64>(0h0), not(allocated_reg[14]))], UInt<64>(0h1)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_12_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_12_16, add(reduced_count_12_14, reduced_count_14_16) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_12_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_12_16, or(or(neq(add(reduced_count_12_14, reduced_count_14_16), reduced_count_12_16), reduced_count_overflowed_12_14), reduced_count_overflowed_14_16) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_12_16: UInt<2>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_12_14, gt(reduced_count_12_14, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<1> + connect reduced_alloc_nums_12_16[0], reduced_alloc_nums_12_14[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<2> + ; rhs: UInt<65> + connect reduced_alloc_nums_12_16[0], add(reduced_alloc_nums_14_16[sub(UInt<64>(0h0), reduced_count_12_14)], UInt<64>(0h2)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_8_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_8_16, add(reduced_count_8_12, reduced_count_12_16) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_8_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_8_16, or(or(neq(add(reduced_count_8_12, reduced_count_12_16), reduced_count_8_16), reduced_count_overflowed_8_12), reduced_count_overflowed_12_16) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_8_16: UInt<3>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_8_12, gt(reduced_count_8_12, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<3> + ; rhs: UInt<2> + connect reduced_alloc_nums_8_16[0], reduced_alloc_nums_8_12[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<3> + ; rhs: UInt<65> + connect reduced_alloc_nums_8_16[0], add(reduced_alloc_nums_12_16[sub(UInt<64>(0h0), reduced_count_8_12)], UInt<64>(0h4)) @[unit_free_regs_tracker.rs 83:21] + wire reduced_count_0_16: UInt<1> @[unit_free_regs_tracker.rs 60:17] + ; connect different types: + ; lhs: UInt<1> + ; rhs: UInt<2> + connect reduced_count_0_16, add(reduced_count_0_8, reduced_count_8_16) @[unit_free_regs_tracker.rs 63:13] + wire reduced_count_overflowed_0_16: UInt<1> @[unit_free_regs_tracker.rs 66:17] + connect reduced_count_overflowed_0_16, or(or(neq(add(reduced_count_0_8, reduced_count_8_16), reduced_count_0_16), reduced_count_overflowed_0_8), reduced_count_overflowed_8_16) @[unit_free_regs_tracker.rs 69:13] + wire reduced_alloc_nums_0_16: UInt<4>[1] @[unit_free_regs_tracker.rs 75:17] + when or(reduced_count_overflowed_0_8, gt(reduced_count_0_8, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 80:17] + ; connect different types: + ; lhs: UInt<4> + ; rhs: UInt<3> + connect reduced_alloc_nums_0_16[0], reduced_alloc_nums_0_8[0] @[unit_free_regs_tracker.rs 81:21] + else: + ; connect different types: + ; lhs: UInt<4> + ; rhs: UInt<65> + connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21] + wire firing_data_1: Ty24 @[ready_valid.rs 30:27] + connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9] + when alloc_out[0].ready: @[ready_valid.rs 33:9] + connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13] + match firing_data_1: @[unit_free_regs_tracker.rs 102:9] + HdlNone: + skip + HdlSome(_match_arm_value_1): + connect allocated_reg[_match_arm_value_1], UInt<1>(0h1) @[unit_free_regs_tracker.rs 103:13] + when or(reduced_count_overflowed_0_16, gt(reduced_count_0_16, UInt<64>(0h0))): @[unit_free_regs_tracker.rs 106:9] + connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlSome, reduced_alloc_nums_0_16[0]) @[unit_free_regs_tracker.rs 107:13] + else: + connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[unit_free_regs_tracker.rs 112:13] +", + }; + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("expected/reg_alloc.txt") { + panic!(); + } } diff --git a/scripts/check-copyright.sh b/scripts/check-copyright.sh index 65c2081..43d3b08 100755 --- a/scripts/check-copyright.sh +++ b/scripts/check-copyright.sh @@ -45,7 +45,7 @@ function main() */LICENSE.md|*/Notices.txt) # copyright file ;; - /crates/cpu/tests/expected/*.vcd) + /crates/cpu/tests/expected/*.vcd|/crates/cpu/tests/expected/*.txt) # file that can't contain copyright header ;; /.forgejo/workflows/*.yml|*/.gitignore|*.toml)