From 2de4a673604376c55665b723664e6e30a71a8b44 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 16 Dec 2025 23:10:07 -0800 Subject: [PATCH] add link to other NLnet task and note lack of optimization --- crates/cpu/src/next_pc.rs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/crates/cpu/src/next_pc.rs b/crates/cpu/src/next_pc.rs index 11a3d9c..db22f7e 100644 --- a/crates/cpu/src/next_pc.rs +++ b/crates/cpu/src/next_pc.rs @@ -1,7 +1,11 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information -//! [Next-Instruction Logic](https://git.libre-chip.org/libre-chip/grant-tracking/issues/10) +//! Next-Instruction Logic and Instruction Fetch/Decode Control System +//! [#10](https://git.libre-chip.org/libre-chip/grant-tracking/issues/10) +//! and [#13](https://git.libre-chip.org/libre-chip/grant-tracking/issues/13). +//! +//! This could use a lot more optimization, but it works AFAIK. //! //! The basic idea here is that there's a `next_pc` stage that sends predicted fetch PCs to the `fetch` stage, //! the `fetch` stage's outputs eventually end up in the `decode` stage,