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fifo-proof

formal_memories

formal_test_case

master

v0.1.0

v0.2.0

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• 3771cea78e
  
  Gather the FIFO debug ports in a bundle fifo-proof Cesar Strauss 2024-12-29 13:17:24 -0300
• dcf865caec
  
  Add assertions and debug ports in order for the FIFO to pass induction Cesar Strauss 2024-12-29 13:12:58 -0300
• 31d01046a8
  
  Initial queue formal proof based on one-entry FIFO equivalence Cesar Strauss 2024-12-29 13:04:01 -0300
• c16726cee6
  
  fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s Jacob Lifshay 2024-12-29 00:48:15 -0800
• b63676d0ca
  
  add test for cfgs Jacob Lifshay 2024-12-27 04:01:53 -0800
• 7005fa3330
  
  implement handling #[cfg] and #[cfg_attr] in proc macro inputs Jacob Lifshay 2024-12-27 04:02:39 -0800
• 2ab8428062
  
  upgrade syn version Jacob Lifshay 2024-12-28 23:34:46 -0800
• 9b06019bf5
  
  make sim::Compiler not print things to stdout unless you ask for it Jacob Lifshay 2024-12-18 21:15:09 -0800
• 36bad52978
  
  sim: fix sim.write to struct Jacob Lifshay 2024-12-18 20:50:50 -0800
• 21c73051ec
  
  sim: add SimValue and reading/writing more than just a scalar Jacob Lifshay 2024-12-18 01:39:35 -0800
• 304d8da0e8
  
  Merge remote-tracking branch 'origin/master' into adding-simulator Jacob Lifshay 2024-12-13 15:06:45 -0800
• 2af38de900
  
  add more memory tests Jacob Lifshay 2024-12-13 15:04:48 -0800
• c756aeec70
  
  tests/sim: add test for memory rw port Jacob Lifshay 2024-12-12 20:50:41 -0800
• 903ca1bf30
  
  sim: simple memory test works! Jacob Lifshay 2024-12-12 19:47:57 -0800
• 8d030ac65d
  
  sim/interpreter: add addresses to instruction listing Jacob Lifshay 2024-12-12 16:25:38 -0800
• 562c479b62
  
  sim/interpreter: fix StatePartLayout name in debug output Jacob Lifshay 2024-12-12 15:06:17 -0800
• 393f78a14d
  
  sim: add WIP memory test Jacob Lifshay 2024-12-11 23:28:15 -0800
• 8616ee4737
  
  tests/sim: test_enums works! Jacob Lifshay 2024-12-11 00:01:04 -0800
• 5087f16099
  
  sim: fix assignments graph by properly including conditions as assignment inputs Jacob Lifshay 2024-12-11 00:00:21 -0800
• 6b31e6d515
  
  sim: add .dot output for Assignments graph for debugging Jacob Lifshay 2024-12-10 23:40:33 -0800
• 564ccb30bc
  
  sim/vcd: fix variable identifiers to follow verilog rules Jacob Lifshay 2024-12-10 23:39:17 -0800
• ca759168ff
  
  tests/sim: add WIP test for enums Jacob Lifshay 2024-12-10 23:37:26 -0800
• e4cf66adf8
  
  sim: implement memories, still needs testing Jacob Lifshay 2024-12-09 23:03:01 -0800
• cd0dd7b7ee
  
  change memory write latency to NonZeroUsize to match read latency being usize Jacob Lifshay 2024-12-09 23:01:40 -0800
• 2e7d685dc7 add module exercising formal verification of memories formal_memories Cesar Strauss 2024-12-08 15:25:21 -0300
• 9654167ca3
  
  sim: WIP working on memory Jacob Lifshay 2024-12-06 15:53:34 -0800
• 3ed7827485
  
  sim: WIP adding memory support Jacob Lifshay 2024-12-05 21:35:23 -0800
• e504cfebfe
  
  add BoolOrIntType::copy_bits_from_bigint_wrapping and take BigInt arguments by reference Jacob Lifshay 2024-12-05 20:27:50 -0800
• 9f42cab471
  
  change to version 0.3.0 for breaking change Jacob Lifshay 2024-12-05 20:26:28 -0800
• 259bee39c2
  
  tests/sim: split expected output text into separate files Jacob Lifshay 2024-12-05 18:15:38 -0800
• 643816d5b5
  
  vcd: handle enums with fields Jacob Lifshay 2024-12-04 21:03:29 -0800
• 42afd2da0e
  
  sim: implement enums (except for connecting unequal enum types) Jacob Lifshay 2024-12-04 20:58:39 -0800
• 15bc304bb6
  
  impl ToExpr for TargetBase Jacob Lifshay 2024-12-04 20:57:44 -0800
• 4422157db8
  
  WIP adding enums to simulator Jacob Lifshay 2024-12-02 21:06:23 -0800
• d3f52292a1
  
  test doc tests in CI Jacob Lifshay 2024-12-01 20:21:26 -0800
• fd45465d35
  
  sim: add support for registers Jacob Lifshay 2024-12-01 20:14:13 -0800
• 5e0548db26
  
  vcd: single bit signals have no spaces in their value changes Jacob Lifshay 2024-12-01 20:12:43 -0800
• 12b3ba57f1
  
  add some ExprCastTo supertraits to ResetType to make generic code easier Jacob Lifshay 2024-12-01 20:10:25 -0800
• 965fe53077
  
  deduce_resets: show more debugging info on assertion failure Jacob Lifshay 2024-12-01 20:08:43 -0800
• 3abba7f9eb
  
  simulating circuits with deduced resets works Jacob Lifshay 2024-11-27 23:52:07 -0800
• 6446b71afd
  
  deduce_resets works! Jacob Lifshay 2024-11-27 23:20:22 -0800
• d36cf92d7f
  
  make ToReset generic over the reset type Jacob Lifshay 2024-11-27 23:19:55 -0800
• d744d85c66
  
  working on deduce_resets Jacob Lifshay 2024-11-27 01:31:18 -0800
• 358cdd10c8
  
  add more expr casts Jacob Lifshay 2024-11-27 01:30:28 -0800
• 9128a84284
  
  Merge remote-tracking branch 'origin/master' into adding-simulator Jacob Lifshay 2024-11-26 21:28:22 -0800
• 546010739a
  
  working on deduce_resets Jacob Lifshay 2024-11-26 21:26:56 -0800
• 9b5f1218fd
  
  make ClockDomain and Reg generic over reset type Jacob Lifshay 2024-11-26 20:47:03 -0800
• 89d84551f8
  
  add ResetType to the list of recognized type bounds Jacob Lifshay 2024-11-26 18:52:03 -0800
• c45624e3c2
  
  Fix SInt::for_value not accounting for sign bit for positive values Jacob Lifshay 2024-11-26 16:26:29 -0800
• 7851bf545c
  
  working on deduce_resets.rs Jacob Lifshay 2024-11-26 00:07:11 -0800
• 3e3da53bd2
  
  working on deduce_resets Jacob Lifshay 2024-11-25 00:01:02 -0800
• fa50930ff8
  
  update petgraph dependency to include UnionFind::new_set() Jacob Lifshay 2024-11-25 00:00:26 -0800
• 9516fe03a1
  
  increase rust version in CI too Jacob Lifshay 2024-11-24 14:46:25 -0800
• 52ab134673
  
  increase rust version to support omitting match arms with uninhabited types Jacob Lifshay 2024-11-24 14:41:39 -0800
• 698b8adc23
  
  working on deduce_resets pass Jacob Lifshay 2024-11-24 14:39:32 -0800
• 59be3bd645
  
  WIP working on implementing deduce_resets pass Jacob Lifshay 2024-11-24 03:44:31 -0800
• 913baa37e9
  
  WIP adding deduce_resets pass Jacob Lifshay 2024-11-22 16:07:18 -0800
• 11ddbc43c7
  
  writing VCD for combinatorial circuits works! Jacob Lifshay 2024-11-20 22:36:12 -0800
• c4b5d00419
  
  WIP adding VCD output Jacob Lifshay 2024-11-18 03:04:10 -0800
• 09aa9fbc78
  
  wire up simulator trace writing interface Jacob Lifshay 2024-11-17 21:02:44 -0800
• 288a6b71b9
  
  WIP adding VCD output Jacob Lifshay 2024-11-17 01:02:00 -0800
• 0095570f19
  
  simple combinatorial simulation works! Jacob Lifshay 2024-11-14 20:28:43 -0800
• f54e55a143
  
  Simulation::settle_step() works for simple modules Jacob Lifshay 2024-11-13 21:20:15 -0800
• a6e40839ac
  
  simulator WIP: use petgraph for topological sort over assignments Jacob Lifshay 2024-11-13 04:14:04 -0800
• 3106a6fff6
  
  working on simulator... Jacob Lifshay 2024-11-12 22:11:12 -0800
• f338f37d3e
  
  working on simulator Jacob Lifshay 2024-11-12 01:08:32 -0800
• 277d3e0d4d
  
  working on simulator Jacob Lifshay 2024-11-10 22:12:57 -0800
• b288d6f8f2
  
  add missing copyright headers Jacob Lifshay 2024-11-07 21:50:31 -0800
• 479d59b287
  
  WIP implementing simulator Jacob Lifshay 2024-11-07 21:46:34 -0800
• 6f904148c4
  
  WIP adding simulator Jacob Lifshay 2024-11-07 01:19:07 -0800
• 3ea0d98924
  
  always write formal cache json Jacob Lifshay 2024-11-20 22:51:40 -0800
• c1f1a8b749 Add test module exercising formal verification. formal_test_case Cesar Strauss 2024-11-20 17:39:00 -0300
• 3d5d8c54b6
  
  add repository to cache key master Jacob Lifshay 2024-10-30 20:55:02 -0700
• ee15fd2b94
  
  support #[hdl] type aliases Jacob Lifshay 2024-10-30 20:47:10 -0700
• 20cf0abbcc
  
  fix using #[hdl] types like S<{ 1 + 2 }> Jacob Lifshay 2024-10-30 20:46:11 -0700
• 5bd0de48b7
  
  change to version 0.2.1 Jacob Lifshay 2024-10-30 19:36:05 -0700
• 0c9c48a066
  
  split out deps into separate workflow with better caching using deps.yml from cpu.git v0.2.0 Jacob Lifshay 2024-10-17 21:05:18 -0700
• cb17913004
  
  limit sby to one thread each since it seems not to respect job count in parallel mode Jacob Lifshay 2024-10-15 21:32:38 -0700
• 42effd1132
  
  switch to using a make job server for managing test parallelism Jacob Lifshay 2024-10-15 20:32:33 -0700
• 3d0f95cfe5
  
  formal: add workaround for wires disappearing because yosys optimizes them out Jacob Lifshay 2024-10-15 01:48:48 -0700
• 3939ce2360
  
  add Bundle and Enum to prelude Jacob Lifshay 2024-10-14 17:47:58 -0700
• d0229fbcfb
  
  get #[hdl] struct S<A: KnownSize, B: KnownSize> to work Jacob Lifshay 2024-10-11 17:30:49 -0700
• 4909724995
  
  add more thorough checks that bounds are properly handled on #[hdl] structs Jacob Lifshay 2024-10-10 23:34:46 -0700
• d0694cbd52
  
  add disabled test for #[hdl] struct S4<W: KnownSize, W2: KnownSize> which type errors Jacob Lifshay 2024-10-10 22:58:15 -0700
• 1a2149b040
  
  silence warnings for field names that start with _ Jacob Lifshay 2024-10-10 20:53:29 -0700
• 59cef3f398
  
  add PhantomData as a hdl bundle Jacob Lifshay 2024-10-10 20:48:09 -0700
• bf907c3872
  
  cache results of formal proofs Jacob Lifshay 2024-10-07 23:31:24 -0700
• 99180eb3b4
  
  fix clippy lints in generated code Jacob Lifshay 2024-10-07 21:59:50 -0700
• 017c14a2f1
  
  don't use #[allow(..., reason = "...")] since that's not stable yet on rust 1.80.1 Jacob Lifshay 2024-10-07 22:05:30 -0700
• ed1aea41f3
  
  clean up some clippy warnings Jacob Lifshay 2024-10-07 21:49:18 -0700
• f12322aa2a
  
  remove interning contexts Jacob Lifshay 2024-10-07 21:33:56 -0700
• 44ca1a607a
  
  remove unused AGCContext Jacob Lifshay 2024-10-07 20:27:39 -0700
• 30b9a5e48d
  
  change NameId to have an opaque Id so output firrtl doesn't depend on how many modules of the same name were ever created Jacob Lifshay 2024-10-07 19:06:01 -0700
• eed0afc6ab
  
  add some utility From<Interned<T>> impls Jacob Lifshay 2024-10-07 19:05:20 -0700
• aec383c0af
  
  try to fix ccache Jacob Lifshay 2024-10-06 20:57:42 -0700
• f403eed7c0
  
  only run tests once, since they are quite slow Jacob Lifshay 2024-10-06 20:08:39 -0700
• 2e8b73d2fc
  
  rename fire/fire_data to firing/firing_data Jacob Lifshay 2024-10-06 19:04:48 -0700
• e05c368688
  
  change register names to end in _reg by convention Jacob Lifshay 2024-10-06 18:50:09 -0700
• ec77559e2b
  
  fix cache action name Jacob Lifshay 2024-10-04 17:10:06 -0700
• b7f1101164
  
  reduce parallelism to fit within the number of available cpus even when running sby in prove mode (which likes to run 2 smt solvers in parallel) Jacob Lifshay 2024-10-04 17:03:51 -0700