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Code Pull requests Activity
157 commits 4 branches 2 tags 6.4 MiB
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132 commits

Author SHA1 Message Date
Jacob Lifshay d36cf92d7f
make ToReset generic over the reset type 2024-11-27 23:19:55 -08:00
Jacob Lifshay d744d85c66
working on deduce_resets 2024-11-27 01:31:18 -08:00
Jacob Lifshay 358cdd10c8
add more expr casts 2024-11-27 01:30:28 -08:00
Jacob Lifshay 9128a84284
Merge remote-tracking branch 'origin/master' into adding-simulator 2024-11-26 21:28:22 -08:00
Jacob Lifshay 546010739a
working on deduce_resets 2024-11-26 21:26:56 -08:00
Jacob Lifshay 9b5f1218fd
make ClockDomain and Reg generic over reset type 2024-11-26 20:47:03 -08:00
Jacob Lifshay 89d84551f8
add ResetType to the list of recognized type bounds 2024-11-26 18:52:03 -08:00
Jacob Lifshay c45624e3c2
Fix SInt::for_value not accounting for sign bit for positive values 
Fixes: #4
 2024-11-26 16:26:29 -08:00
Jacob Lifshay 7851bf545c
working on deduce_resets.rs 2024-11-26 00:07:11 -08:00
Jacob Lifshay 3e3da53bd2
working on deduce_resets 2024-11-25 00:01:02 -08:00
Jacob Lifshay 698b8adc23
working on deduce_resets pass 2024-11-24 14:39:32 -08:00
Jacob Lifshay 59be3bd645
WIP working on implementing deduce_resets pass 2024-11-24 03:44:31 -08:00
Jacob Lifshay 913baa37e9
WIP adding deduce_resets pass 2024-11-22 16:07:18 -08:00
Jacob Lifshay 11ddbc43c7
writing VCD for combinatorial circuits works! 2024-11-20 22:53:54 -08:00
Jacob Lifshay c4b5d00419
WIP adding VCD output 2024-11-20 22:53:54 -08:00
Jacob Lifshay 09aa9fbc78
wire up simulator trace writing interface 2024-11-20 22:53:54 -08:00
Jacob Lifshay 288a6b71b9
WIP adding VCD output 2024-11-20 22:53:54 -08:00
Jacob Lifshay 0095570f19
simple combinatorial simulation works! 2024-11-20 22:53:54 -08:00
Jacob Lifshay f54e55a143
Simulation::settle_step() works for simple modules 2024-11-20 22:53:54 -08:00
Jacob Lifshay a6e40839ac
simulator WIP: use petgraph for topological sort over assignments 2024-11-20 22:53:54 -08:00
Jacob Lifshay 3106a6fff6
working on simulator... 2024-11-20 22:53:54 -08:00
Jacob Lifshay f338f37d3e
working on simulator 2024-11-20 22:53:54 -08:00
Jacob Lifshay 277d3e0d4d
working on simulator 2024-11-20 22:53:54 -08:00
Jacob Lifshay b288d6f8f2
add missing copyright headers 2024-11-20 22:53:54 -08:00
Jacob Lifshay 479d59b287
WIP implementing simulator 2024-11-20 22:53:54 -08:00
Jacob Lifshay 6f904148c4
WIP adding simulator 2024-11-20 22:53:54 -08:00
Jacob Lifshay 3ea0d98924
always write formal cache json 2024-11-20 22:51:40 -08:00
Cesar Strauss c1f1a8b749 Add test module exercising formal verification. 2024-11-20 18:29:39 -03:00
Jacob Lifshay ee15fd2b94
support #[hdl] type aliases 2024-10-30 20:47:10 -07:00
Jacob Lifshay 20cf0abbcc
fix using #[hdl] types like S<{ 1 + 2 }> 2024-10-30 20:46:11 -07:00
Jacob Lifshay cb17913004
limit sby to one thread each since it seems not to respect job count in parallel mode 2024-10-15 21:32:38 -07:00
Jacob Lifshay 42effd1132
switch to using a make job server for managing test parallelism 2024-10-15 20:32:33 -07:00
Jacob Lifshay 3d0f95cfe5
formal: add workaround for wires disappearing because yosys optimizes them out 2024-10-15 01:48:48 -07:00
Jacob Lifshay 3939ce2360
add Bundle and Enum to prelude 2024-10-14 17:47:58 -07:00
Jacob Lifshay d0229fbcfb
get #[hdl] struct S<A: KnownSize, B: KnownSize> to work 2024-10-11 17:30:49 -07:00
Jacob Lifshay 4909724995
add more thorough checks that bounds are properly handled on #[hdl] structs 2024-10-10 23:34:46 -07:00
Jacob Lifshay d0694cbd52
add disabled test for #[hdl] struct S4<W: KnownSize, W2: KnownSize> which type errors 2024-10-10 22:58:15 -07:00
Jacob Lifshay 1a2149b040
silence warnings for field names that start with _ 2024-10-10 20:53:29 -07:00
Jacob Lifshay 59cef3f398
add PhantomData as a hdl bundle 2024-10-10 20:48:09 -07:00
Jacob Lifshay bf907c3872
cache results of formal proofs 2024-10-07 23:31:24 -07:00
Jacob Lifshay 99180eb3b4
fix clippy lints in generated code 2024-10-07 22:06:59 -07:00
Jacob Lifshay 017c14a2f1
don't use #[allow(..., reason = "...")] since that's not stable yet on rust 1.80.1 2024-10-07 22:06:59 -07:00
Jacob Lifshay ed1aea41f3
clean up some clippy warnings 2024-10-07 21:49:18 -07:00
Jacob Lifshay f12322aa2a
remove interning contexts 2024-10-07 21:33:56 -07:00
Jacob Lifshay 44ca1a607a
remove unused AGCContext 2024-10-07 21:23:13 -07:00
Jacob Lifshay 30b9a5e48d
change NameId to have an opaque Id so output firrtl doesn't depend on how many modules of the same name were ever created 2024-10-07 19:06:01 -07:00
Jacob Lifshay eed0afc6ab
add some utility From<Interned<T>> impls 2024-10-07 19:05:20 -07:00
Jacob Lifshay 2e8b73d2fc
rename fire/fire_data to firing/firing_data 2024-10-06 19:04:48 -07:00
Jacob Lifshay e05c368688
change register names to end in _reg by convention 2024-10-06 18:50:09 -07:00
Jacob Lifshay b7f1101164
reduce parallelism to fit within the number of available cpus even when running sby in prove mode (which likes to run 2 smt solvers in parallel) 2024-10-04 17:03:51 -07:00