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Author	SHA1	Message	Date
Jacob Lifshay	4b24a88641	add docs for #[hdl] and particularly for #[hdl] type aliases	2025-10-26 03:25:35 -07:00
Jacob Lifshay	094c77e26e	add #[hdl(get(|v| ...))] type GetStuff<P: PhantomConstGet<MyStruct>> = MyType or DynSize;	2025-10-26 03:25:35 -07:00
Jacob Lifshay	d2c8b023bf	deny broken docs	2025-10-26 03:25:35 -07:00
Jacob Lifshay	c043ee54d0	fix rustdoc warning for link in readme	2025-10-26 03:25:35 -07:00
Jacob Lifshay	edcc5927a5	don't cache external job failures if they could be caused by the user killing processes	2025-10-24 02:27:20 -07:00
Jacob Lifshay	7dc4417874	add test_many_memories so we catch if memories are iterated in an inconsistent order like in 838bd469ce	2025-10-24 01:40:30 -07:00
Jacob Lifshay	838bd469ce	change SimulationImpl::trace_memories to a BTreeMap for consistent iteration order	2025-10-24 00:53:13 -07:00
Jacob Lifshay	b6e4cd0614	move FormalMode to crate::testing and add to prelude	2025-10-24 00:14:04 -07:00
Jacob Lifshay	3e5b2f126a	make UIntInRange[Inclusive][Type] castable from/to any UInt<N> and add methods to get bit_width, start, and end	2025-10-23 23:52:41 -07:00
Jacob Lifshay	040cefea21	add tx_only_uart example to readme	2025-10-22 20:31:25 -07:00
Jacob Lifshay	3267cb38c4	build tx_only_uart in CI	2025-10-22 20:12:08 -07:00
Jacob Lifshay	b3cc28e2b6	add transmit-only UART example	2025-10-22 20:11:02 -07:00
Jacob Lifshay	26840daf13	arty_a7: add divided clocks as available input peripherals so you're not stuck with 100MHz	2025-10-22 20:11:02 -07:00
Jacob Lifshay	4d9e8d3b47	Add building blinky example to the readme	2025-10-21 23:00:16 -07:00
Jacob Lifshay	c6feea6d51	properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency	2025-10-21 22:24:02 -07:00
Jacob Lifshay	409992961c	switch to using verilog for reset synchronizer so we can use attributes on FDPE instances	2025-10-21 22:24:02 -07:00
Jacob Lifshay	2bdc8a7c72	WIP adding xdc create_clock -- nextpnr-xilinx currently ignores it	2025-10-19 23:13:28 -07:00
Jacob Lifshay	477a1f2d29	Add peripherals and Arty A7 platforms -- blinky works correctly now on arty-a7-100t!	2025-10-19 23:13:28 -07:00
Jacob Lifshay	4d54f903be	move vendor module to top level	2025-10-17 15:00:19 -07:00
Jacob Lifshay	3f5dd61e46	WIP adding Platform	2025-10-17 05:55:22 -07:00
Jacob Lifshay	def406ab52	group all xilinx annotations together	2025-10-16 04:53:58 -07:00
Jacob Lifshay	a565be1b09	do some clean up	2025-10-16 04:32:56 -07:00
Jacob Lifshay	676c1e3b7d	WIP adding annotations for generating the .xdc file for yosys-nextpnr-prjxray	2025-10-15 04:29:00 -07:00
Jacob Lifshay	169be960f8	generate Arty A7 100T .bit file for blinky example in CI	2025-10-15 04:29:00 -07:00
Jacob Lifshay	2b52799f5c	try building .bit file	2025-10-15 04:29:00 -07:00
Jacob Lifshay	35f98f3229	fix redirects	2025-10-15 04:29:00 -07:00
Jacob Lifshay	8a63ea89d0	WIP adding yosys-nextpnr-xray xilinx fpga toolchain -- blinky works on arty a7 100t (except for inverted reset)	2025-10-15 04:29:00 -07:00
Jacob Lifshay	84c5978eaf	WIP build Xilinx FPGA dependencies in CI	2025-10-15 04:29:00 -07:00
Jacob Lifshay	42e3179a60	change cache directory name to be fayalite-specific	2025-10-15 04:29:00 -07:00
Jacob Lifshay	53ae3ff670	mark create-unix-shell-script as incomplete in CLI	2025-10-15 04:29:00 -07:00
Jacob Lifshay	7af9abfb6f	switch to using new crate::build system	2025-10-15 04:29:00 -07:00
Jacob Lifshay	aacd05378f	WIP converting from cli.rs to build/*.rs	2025-10-15 04:29:00 -07:00
Jacob Lifshay	908ccef674	added automatically-added dependencies; added caching for external jobs	2025-10-15 04:29:00 -07:00
Jacob Lifshay	057670c12a	WIP adding FPGA support -- build module should be complete	2025-10-15 04:29:00 -07:00
Jacob Lifshay	f8ac78abd6	Remove extraneous #[automatically_derived] annotations that are causing warnings as reported by Tobias	2025-10-15 04:17:47 -07:00
Jacob Lifshay	64ec6c0dcc	switch to use server's new actions org	2025-10-09 23:48:17 -07:00
Jacob Lifshay	c06ef56482	add NLnet grant 2024-12-324 to readme	2025-09-08 23:08:25 -07:00
Jacob Lifshay	db9b1c202c	add simulator support for sim-only values	2025-09-08 22:19:43 -07:00
Jacob Lifshay	d3dd66cbf0	add rust-src component in CI for consistent error messages	2025-09-08 22:18:10 -07:00
Jacob Lifshay	b5b1ee866c	converted to using get_state_part_kinds!	2025-09-05 19:10:06 -07:00
Jacob Lifshay	f0e3aef061	add get_state_part_kinds! macro	2025-09-05 19:07:07 -07:00
Jacob Lifshay	6d36698adf	move public paths of sim::{Compiled,Compiler} to sim::compiler	2025-08-26 19:23:21 -07:00
Jacob Lifshay	e7e831cf00	split out simulator compiler into a separate module	2025-08-26 19:17:21 -07:00
Jacob Lifshay	4008c311bf	format code after switching to edition 2024	2025-08-24 16:35:21 -07:00
Jacob Lifshay	ef85d11327	try to get actions to run	2025-08-24 16:14:03 -07:00
Jacob Lifshay	ae7c4be9dc	remove get_many_mut since it was stabilized in std as get_disjoint_mut	2025-08-24 15:53:21 -07:00
Jacob Lifshay	65f9ab32f4	switch to edition 2024	2025-08-24 15:53:21 -07:00
Jacob Lifshay	67e66ac3bd	upgrade to rust 1.89.0	2025-08-24 15:53:21 -07:00
Jacob Lifshay	668e714dc9	actually test always_zero hasher	2025-04-09 21:11:09 -07:00
Jacob Lifshay	88323a8c16	run some tests with always_zero hasher	2025-04-09 21:03:57 -07:00