cesar/fayalite
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Code Pull requests Activity
198 commits 4 branches 2 tags 6.4 MiB
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64 commits

Author SHA1 Message Date
Jacob Lifshay c16726cee6
fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s 2024-12-29 00:48:15 -08:00
Jacob Lifshay b63676d0ca
add test for cfgs 2024-12-28 23:39:50 -08:00
Jacob Lifshay 36bad52978
sim: fix sim.write to struct 2024-12-18 20:50:50 -08:00
Jacob Lifshay 21c73051ec
sim: add SimValue and reading/writing more than just a scalar 2024-12-18 01:39:35 -08:00
Jacob Lifshay 304d8da0e8
Merge remote-tracking branch 'origin/master' into adding-simulator 2024-12-13 15:06:45 -08:00
Jacob Lifshay 2af38de900
add more memory tests 2024-12-13 15:04:48 -08:00
Jacob Lifshay c756aeec70
tests/sim: add test for memory rw port 2024-12-12 20:50:41 -08:00
Jacob Lifshay 903ca1bf30
sim: simple memory test works! 2024-12-12 19:47:57 -08:00
Jacob Lifshay 8d030ac65d
sim/interpreter: add addresses to instruction listing 2024-12-12 16:25:38 -08:00
Jacob Lifshay 562c479b62
sim/interpreter: fix StatePartLayout name in debug output 2024-12-12 15:06:17 -08:00
Jacob Lifshay 393f78a14d
sim: add WIP memory test 2024-12-11 23:28:15 -08:00
Jacob Lifshay 8616ee4737
tests/sim: test_enums works! 2024-12-11 00:01:04 -08:00
Jacob Lifshay ca759168ff
tests/sim: add WIP test for enums 2024-12-10 23:37:26 -08:00
Jacob Lifshay e4cf66adf8
sim: implement memories, still needs testing 2024-12-09 23:03:01 -08:00
Cesar Strauss 2e7d685dc7 add module exercising formal verification of memories 2024-12-08 17:13:26 -03:00
Jacob Lifshay 3ed7827485
sim: WIP adding memory support 2024-12-05 21:35:23 -08:00
Jacob Lifshay 259bee39c2
tests/sim: split expected output text into separate files 2024-12-05 18:17:13 -08:00
Jacob Lifshay 42afd2da0e
sim: implement enums (except for connecting unequal enum types) 2024-12-04 20:58:39 -08:00
Jacob Lifshay fd45465d35
sim: add support for registers 2024-12-01 20:14:13 -08:00
Jacob Lifshay 5e0548db26
vcd: single bit signals have no spaces in their value changes 2024-12-01 20:12:43 -08:00
Jacob Lifshay 3abba7f9eb
simulating circuits with deduced resets works 2024-11-27 23:52:07 -08:00
Jacob Lifshay 6446b71afd
deduce_resets works! 2024-11-27 23:24:11 -08:00
Jacob Lifshay 11ddbc43c7
writing VCD for combinatorial circuits works! 2024-11-20 22:53:54 -08:00
Jacob Lifshay c4b5d00419
WIP adding VCD output 2024-11-20 22:53:54 -08:00
Jacob Lifshay 09aa9fbc78
wire up simulator trace writing interface 2024-11-20 22:53:54 -08:00
Jacob Lifshay 288a6b71b9
WIP adding VCD output 2024-11-20 22:53:54 -08:00
Jacob Lifshay 0095570f19
simple combinatorial simulation works! 2024-11-20 22:53:54 -08:00
Jacob Lifshay f54e55a143
Simulation::settle_step() works for simple modules 2024-11-20 22:53:54 -08:00
Cesar Strauss c1f1a8b749 Add test module exercising formal verification. 2024-11-20 18:29:39 -03:00
Jacob Lifshay ee15fd2b94
support #[hdl] type aliases 2024-10-30 20:47:10 -07:00
Jacob Lifshay d0229fbcfb
get #[hdl] struct S<A: KnownSize, B: KnownSize> to work 2024-10-11 17:30:49 -07:00
Jacob Lifshay 4909724995
add more thorough checks that bounds are properly handled on #[hdl] structs 2024-10-10 23:34:46 -07:00
Jacob Lifshay d0694cbd52
add disabled test for #[hdl] struct S4<W: KnownSize, W2: KnownSize> which type errors 2024-10-10 22:58:15 -07:00
Jacob Lifshay 1a2149b040
silence warnings for field names that start with _ 2024-10-10 20:53:29 -07:00
Jacob Lifshay 59cef3f398
add PhantomData as a hdl bundle 2024-10-10 20:48:09 -07:00
Jacob Lifshay ed1aea41f3
clean up some clippy warnings 2024-10-07 21:49:18 -07:00
Jacob Lifshay 30b9a5e48d
change NameId to have an opaque Id so output firrtl doesn't depend on how many modules of the same name were ever created 2024-10-07 19:06:01 -07:00
Jacob Lifshay e05c368688
change register names to end in _reg by convention 2024-10-06 18:50:09 -07:00
Jacob Lifshay 0d54b9a2a9
queue formal proof passes! 2024-10-03 23:07:14 -07:00
Jacob Lifshay 343805f80b
fix #[hdl] to work with unusual identifier hygiene from macros 2024-10-03 23:04:14 -07:00
Jacob Lifshay 3e2fb9b94f
WIP getting queue formal to pass -- passes for capacity <= 2 2024-10-03 01:08:01 -07:00
Jacob Lifshay f3d6528f5b
make annotations easier to use 2024-10-01 19:54:17 -07:00
Jacob Lifshay d0b406d288
add more annotation kinds 2024-10-01 18:33:32 -07:00
Jacob Lifshay d089095667
change default to --simplify-enums=replace-with-bundle-of-uints 2024-10-01 00:07:48 -07:00
Jacob Lifshay 186488a82e
remove FIXME now that simplify_enums is fixed 2024-09-30 23:31:45 -07:00
Jacob Lifshay edcea1adc3
add firrtl comments when connecting expressions with different types 2024-09-30 22:33:27 -07:00
Jacob Lifshay 30a38bc8da
fix simplify_enums to properly handle nested enums and connects with different types 2024-09-30 22:31:16 -07:00
Jacob Lifshay 04752c5037
add test for connect_any with nested enums with different-sized variant bodies 
simplify_enums is currently broken in that case
 2024-09-25 21:55:52 -07:00
Jacob Lifshay 28aad19bf5
add assert/assume/cover 2024-09-23 19:10:51 -07:00
Jacob Lifshay 9ad4ec0f39
add ty.uninit() 2024-09-22 17:26:23 -07:00