HaeckseAlex/cpu
2
0
Fork 0
forked from libre-chip/cpu
Code Pull requests Activity

Compare commits

base: HaeckseAlex:1ead550d1356a4ef263a0ac9ad41e618e820ab8a
Branches Tags
HaeckseAlex:master
HaeckseAlex:main_memory_wip
HaeckseAlex:wip-splitting-reg-alloc
libre-chip:master
libre-chip:wip-splitting-reg-alloc
...
compare: HaeckseAlex:672a29e76d37b3674f164400f6cabca0a44c02f9
Branches Tags
HaeckseAlex:main_memory_wip
HaeckseAlex:master
HaeckseAlex:wip-splitting-reg-alloc
libre-chip:master
libre-chip:wip-splitting-reg-alloc

2 commits
1ead550d13 ... 672a29e76d

Author SHA1 Message Date
Tobias Alexandra Platen
672a29e76d run cargo fmt on main_memory 2025-10-14 20:11:24 +02:00
Tobias Alexandra Platen
35ea85d074 add write port 2025-10-14 20:08:29 +02:00
2 changed files with 38 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

17
crates/cpu/src/main_memory.rs
View file

@ -29,13 +29,17 @@ pub fn main_memory(config: &CpuConfig) {
let read_data: UInt<8> = m.output();
#[hdl]
let en: Bool = m.input();
// add write support
#[hdl]
let write_en: Bool = m.input();
#[hdl]
let write_data: UInt<8> = m.input();
#[hdl]
let cd: ClockDomain = m.input();
// for each instance do
// connect(instance.cd, cd);
#[hdl]
//let mut mem = memory_with_init([0x12u8, 0x34, 0x56, 0x78]);
let mut my_memory = memory_with_init([0x12_hdl_u8, 0x34_hdl_u8, 0x56_hdl_u8, 0x78_hdl_u8]);
@ -48,10 +52,13 @@ pub fn main_memory(config: &CpuConfig) {
connect(read_port.clk, cd.clk);
connect(read_data, read_port.data);
let write_port = my_memory.new_write_port();
connect_any(write_port.addr, addr);
connect_any(write_port.en, addr.cmp_lt(4u64) & write_en);
connect_any(write_port.data, write_data);
connect(write_port.clk, cd.clk);
//connect_any(write_port.mask, 0xFFu8); //try that one
connect_any(write_port.mask, true);
}
// see https://git.libre-chip.org/libre-chip/fayalite/src/branch/master/crates/fayalite/tests/sim.rs

20
crates/cpu/tests/main_memory.rs
View file

@ -4,10 +4,10 @@
use cpu::{
config::{CpuConfig, UnitConfig},
instruction::{AddSubMOp, LogicalMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode},
main_memory::main_memory,
reg_alloc::{FetchedDecodedMOp, reg_alloc},
register::{FlagsMode, PRegFlagsPowerISA},
unit::{GlobalState, UnitKind},
main_memory::main_memory,
};
use fayalite::{
assert_export_firrtl,
@ -41,6 +41,8 @@ fn test_main_memory() {
sim.write(sim.io().en, true);
sim.write(sim.io().cd.rst, false);
sim.write(sim.io().cd.clk, false);
sim.write(sim.io().write_en, false);
sim.write(sim.io().write_data, 0xFFu8);
// TODO convert to for loop
// you need to write an initial value to all inputs before you can start running the simulation
@ -50,15 +52,25 @@ fn test_main_memory() {
dbg!(sim.read(sim.io().read_data)); // dbg! macro just displays the value you pass to it
for n in 0u64..4u64 {
sim.write(sim.io().addr, n);
// now wait 1us because why not
sim.advance_time(SimDuration::from_micros(1));
}
sim.write(sim.io().write_en, true);
sim.write(sim.io().addr, 0u64);
sim.write(sim.io().write_data, 0x11u8);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 1u64);
sim.write(sim.io().write_data, 0x22u8);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 2u64);
sim.write(sim.io().write_data, 0x33u8);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 3u64);
sim.write(sim.io().write_data, 0x44u8);
sim.advance_time(SimDuration::from_micros(1));
sim.flush_traces().unwrap(); // make sure everything is written to the output file
}