forked from libre-chip/cpu
use for loop in unit test
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1 changed files with 10 additions and 1 deletions
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@ -49,7 +49,16 @@ fn test_main_memory() {
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sim.advance_time(SimDuration::from_micros(1)); //panic here at simulation
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dbg!(sim.read(sim.io().read_data)); // dbg! macro just displays the value you pass to it
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for n in 0u64..4u64 {
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sim.write(sim.io().addr, n);
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// now wait 1us because why not
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sim.advance_time(SimDuration::from_micros(1));
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}
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sim.flush_traces().unwrap(); // make sure everything is written to the output file
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}
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}
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