programmerjake
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  • Joined on 2024-07-08
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programmerjake deleted branch custom-debug from programmerjake/fayalite 2026-05-01 06:18:32 +00:00
programmerjake automatically merged pull request libre-chip/fayalite#70 2026-05-01 06:18:31 +00:00
programmerjake pushed to master at libre-chip/fayalite 2026-05-01 06:18:31 +00:00
8e4eeef723 add support for custom debug/display formatting of #[hdl] structs/enums
programmerjake created pull request libre-chip/fayalite#70 2026-05-01 06:14:21 +00:00
add support for custom debug/display formatting of #[hdl] structs/enums
programmerjake created branch custom-debug in programmerjake/fayalite 2026-05-01 06:13:44 +00:00
programmerjake pushed to custom-debug at programmerjake/fayalite 2026-05-01 06:13:44 +00:00
8e4eeef723 add support for custom debug/display formatting of #[hdl] structs/enums
402f457c68 sim: Speed up updating traces by tracking which traces are written to
8cff3687f7 Run Rocq tests.
80b92c7dd3 change vcd output to have module contents under instance's name, more closely matching how it works in verilog
2aa41137d4 add simulator tests for queue()
Compare 10 commits »
programmerjake pushed to rename-execute-retire at programmerjake/cpu 2026-05-01 02:23:30 +00:00
c3679f2718 update fayalite to include simulator optimizations
programmerjake deleted branch speed-up-sim from programmerjake/fayalite 2026-05-01 02:18:41 +00:00
programmerjake pushed to master at libre-chip/fayalite 2026-05-01 02:18:40 +00:00
402f457c68 sim: Speed up updating traces by tracking which traces are written to
programmerjake automatically merged pull request libre-chip/fayalite#69 2026-05-01 02:18:39 +00:00
programmerjake created pull request libre-chip/fayalite#69 2026-05-01 02:14:24 +00:00
sim: Speed up updating traces by tracking which traces are written to
programmerjake pushed to speed-up-sim at programmerjake/fayalite 2026-05-01 02:12:45 +00:00
402f457c68 sim: Speed up updating traces by tracking which traces are written to
programmerjake created branch speed-up-sim in programmerjake/fayalite 2026-05-01 02:11:58 +00:00
programmerjake pushed to speed-up-sim at programmerjake/fayalite 2026-05-01 02:11:58 +00:00
b4b8354668 sim: Try to speed up updating traces by tracking which traces are written to
8cff3687f7 Run Rocq tests.
80b92c7dd3 change vcd output to have module contents under instance's name, more closely matching how it works in verilog
2aa41137d4 add simulator tests for queue()
a0b2dc085c add test that simulator handles last-connect semantics properly
Compare 10 commits »
programmerjake pushed to rename-execute-retire at programmerjake/cpu 2026-05-01 00:51:43 +00:00
283117d8df add support for speculative loads
programmerjake pushed to rename-execute-retire at programmerjake/cpu 2026-05-01 00:51:14 +00:00
7ea22dafe2 add support for speculative loads
programmerjake pushed to rename-execute-retire at programmerjake/cpu 2026-04-30 08:40:27 +00:00
52b1b625d1 add support for speculative loads
programmerjake pushed to rename-execute-retire at programmerjake/cpu 2026-04-28 07:53:02 +00:00
9fbb517cf4 WIP adding support for speculative loads/stores
programmerjake created pull request libre-chip/cpu#12 2026-04-25 01:28:55 +00:00
WIP: add a procedural implementation of rename_execute_retire
programmerjake pushed to rename-execute-retire at programmerjake/cpu 2026-04-25 01:16:10 +00:00
4d21ca622b add initial impl of rename_execute_retire; running a recursive fibonacci gives the correct output