programmerjake
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  • Joined on 2024-07-08
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programmerjake pushed to support-unknown-trait-bounds at programmerjake/fayalite 2025-02-14 02:36:41 +00:00
cdd84953d0 support unknown trait bounds in type parameters
86a1bb46be add #[hdl] let destructuring and, while at it, tuple patterns
209d5b5fe1 fix broken doc links
d4ea826051 sim: fix "label address not set" bug when the last Assignment is conditional
404a2ee043 tests/sim: add test_array_rw
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programmerjake deleted branch add-let-destructuring from programmerjake/fayalite 2025-02-14 02:32:18 +00:00
programmerjake pushed to master at libre-chip/cpu 2025-02-12 03:27:50 +00:00
1084278f34 reg_alloc: add writes to rename table
64566f718f update fayalite to latest git
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programmerjake pushed to master at libre-chip/fayalite 2025-02-11 07:07:28 +00:00
86a1bb46be add #[hdl] let destructuring and, while at it, tuple patterns
209d5b5fe1 fix broken doc links
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programmerjake automatically merged pull request libre-chip/fayalite#17 2025-02-11 07:07:26 +00:00
programmerjake created pull request libre-chip/fayalite#17 2025-02-11 06:52:06 +00:00
add #[hdl] let destructuring
programmerjake created branch add-let-destructuring in programmerjake/fayalite 2025-02-11 06:50:46 +00:00
programmerjake pushed to add-let-destructuring at programmerjake/fayalite 2025-02-11 06:50:46 +00:00
86a1bb46be add #[hdl] let destructuring and, while at it, tuple patterns
209d5b5fe1 fix broken doc links
d4ea826051 sim: fix "label address not set" bug when the last Assignment is conditional
404a2ee043 tests/sim: add test_array_rw
e3a2ccd41c properly handle duplicate names in vcd
Compare 10 commits »
programmerjake pushed to master at libre-chip/cpu 2025-02-07 05:32:01 +00:00
294e979848 tests/reg_alloc: remove simulator debug output
programmerjake pushed to master at libre-chip/cpu 2025-02-07 05:29:16 +00:00
7efcd872b5 working on reg_alloc
programmerjake pushed to main at libre-chip/website 2025-01-16 04:34:24 +00:00
f62d5b01ea add link to https://forum.libre-chip.org/t/idea-for-maybe-allowing-much-wider-fetch-rename-etc-widths-in-a-cpu/33
programmerjake pushed to master at libre-chip/cpu 2025-01-16 03:48:25 +00:00
88eff5952b working on reg_alloc -- wire up free_regs_tracker.alloc_out
programmerjake pushed to master at libre-chip/cpu 2025-01-16 03:15:31 +00:00
9781f1f4c5 update to latest fayalite to include bug fix libre-chip/fayalite#16
programmerjake pushed to master at libre-chip/fayalite 2025-01-16 03:12:06 +00:00
d4ea826051 sim: fix "label address not set" bug when the last Assignment is conditional
programmerjake deleted branch fix_label_address_not_set_bug from programmerjake/fayalite 2025-01-16 03:12:06 +00:00
programmerjake merged pull request libre-chip/fayalite#16 2025-01-16 03:12:04 +00:00
sim: fix "label address not set" bug when the last Assignment is conditional
programmerjake created pull request libre-chip/fayalite#16 2025-01-16 03:07:51 +00:00
sim: fix "label address not set" bug when the last Assignment is conditional
programmerjake created branch fix_label_address_not_set_bug in programmerjake/fayalite 2025-01-16 03:06:35 +00:00
programmerjake pushed to fix_label_address_not_set_bug at programmerjake/fayalite 2025-01-16 03:06:35 +00:00
d4ea826051 sim: fix "label address not set" bug when the last Assignment is conditional
404a2ee043 tests/sim: add test_array_rw
e3a2ccd41c properly handle duplicate names in vcd
3771cea78e Gather the FIFO debug ports in a bundle
dcf865caec Add assertions and debug ports in order for the FIFO to pass induction
Compare 10 commits »
programmerjake pushed to master at libre-chip/cpu 2025-01-13 06:13:15 +00:00
5f7766777a working on reg_alloc -- selected_unit_nums should be correct now