programmerjake
created branch add-uart-example in programmerjake/fayalite
2025-10-22 12:07:26 +00:00
c6feea6d51
properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency
409992961c
switch to using verilog for reset synchronizer so we can use attributes on FDPE instances
NLnet 2024-12-324 Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain).
"Results" from request for payment for this and #6, since it's probably useful for others:
I rewrote the code for Fayalite's CLI to support being extensible from outside the Fayalite library,…
programmerjake
deleted branch add-blinky-to-readme from programmerjake/fayalite
2025-10-22 06:11:43 +00:00
Add building blinky example to the readme
Add building blinky example to the readme
programmerjake
created branch add-blinky-to-readme in programmerjake/fayalite
2025-10-22 06:00:49 +00:00
c6feea6d51
properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency
409992961c
switch to using verilog for reset synchronizer so we can use attributes on FDPE instances
programmerjake
deleted branch fpga-support-and-arty-a7-100t from programmerjake/fayalite
2025-10-22 05:36:16 +00:00
c6feea6d51
properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency
409992961c
switch to using verilog for reset synchronizer so we can use attributes on FDPE instances
fpga support and arty a7 100t
NLnet 2024-12-324 Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain).
NLnet 2024-12-324 Add support for the Arty A7 100T since that's what we're using for CI.
fpga support and arty a7 100t
@programmerjake wrote in libre-chip/fayalite#38 (comment):
also I need to adjust the generated xdc so the clock properly gets the frequency constraint…
programmerjake
pushed to fpga-support-and-arty-a7-100t at programmerjake/fayalite
2025-10-22 05:24:14 +00:00
c6feea6d51
properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency
409992961c
switch to using verilog for reset synchronizer so we can use attributes on FDPE instances
fpga support and arty a7 100t
@programmerjake wrote in libre-chip/fayalite#38 (comment):
I got everything to work except that either blinky has an error or the board is broken --…
fpga support and arty a7 100t
I got everything to work except that either blinky has an error or the board is broken -- one of the rgb leds blinks randomly as if there's a broken connection somewhere.
also I need to adjust…
programmerjake
pushed to fpga-support-and-arty-a7-100t at programmerjake/fayalite
2025-10-20 06:13:36 +00:00
programmerjake
pushed to fpga-support-and-arty-a7-100t at programmerjake/fayalite
2025-10-20 06:11:43 +00:00