programmerjake
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  • Joined on 2024-07-08
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programmerjake pushed to improve-simvalue at programmerjake/fayalite 2025-04-02 05:23:34 +00:00
62058dc141 fix cargo doc warnings -- convert urls to auto links
programmerjake pushed to improve-simvalue at programmerjake/fayalite 2025-04-02 05:17:05 +00:00
c4b6a0fee6 add support for #[hdl(sim)] enum_ty.Variant(value) and #[hdl(sim)] EnumTy::Variant(value) and non-sim variants too
programmerjake pushed to improve-simvalue at programmerjake/fayalite 2025-04-02 05:07:17 +00:00
43c29bf221 add support for #[hdl(sim)] enum_ty.Variant(value) and #[hdl(sim)] EnumTy::Variant(value) and non-sim variants too
programmerjake pushed to improve-simvalue at programmerjake/fayalite 2025-03-30 08:25:59 +00:00
9092e45447 fix #[hdl(sim)] match on enums
programmerjake created pull request libre-chip/fayalite#27 2025-03-30 08:00:26 +00:00
improve SimValue<T> to generally be more like Expr<T>
programmerjake pushed to improve-simvalue at programmerjake/fayalite 2025-03-30 07:56:33 +00:00
a40eaaa2da expand SimValue support
programmerjake created branch improve-simvalue in programmerjake/fayalite 2025-03-28 06:46:16 +00:00
programmerjake pushed to improve-simvalue at programmerjake/fayalite 2025-03-28 06:46:16 +00:00
5028401a5a change SimValue to contain and deref to a value and not just contain bits
e0f978fbb6 silence unused m variable warning in #[hdl_module] with an empty body.
ec3a61513b simulator read/write types must be passive
fdc73b5f3b add ripple counter test to test simulating alternating circuits and extern modules
a115585d5a simulator: allow external module generators to wait for value changes and/or clock edges
Compare 10 commits »
programmerjake merged pull request libre-chip/fayalite#26 2025-03-26 02:02:54 +00:00
implement simulation of extern modules
programmerjake pushed to master at libre-chip/fayalite 2025-03-26 02:02:54 +00:00
fdc73b5f3b add ripple counter test to test simulating alternating circuits and extern modules
a115585d5a simulator: allow external module generators to wait for value changes and/or clock edges
ab9ff4f2db simplify setting an extern module simulation
d1bd176b28 implement simulation of extern modules
920d8d875f add some missing #[track_caller]
Compare 5 commits »
programmerjake deleted branch sim-extern-module from programmerjake/fayalite 2025-03-26 02:02:54 +00:00
programmerjake pushed to sim-extern-module at programmerjake/fayalite 2025-03-26 01:56:45 +00:00
fdc73b5f3b add ripple counter test to test simulating alternating circuits and extern modules
programmerjake pushed to sim-extern-module at programmerjake/fayalite 2025-03-26 01:54:33 +00:00
1b220b73e7 add ripple counter test to test simulating alternating circuits and extern modules
programmerjake pushed to sim-extern-module at programmerjake/fayalite 2025-03-26 01:28:34 +00:00
a115585d5a simulator: allow external module generators to wait for value changes and/or clock edges
programmerjake pushed to sim-extern-module at programmerjake/fayalite 2025-03-22 00:09:18 +00:00
ab9ff4f2db simplify setting an extern module simulation
programmerjake created pull request libre-chip/fayalite#26 2025-03-21 08:50:38 +00:00
implement simulation of extern modules
programmerjake pushed to sim-extern-module at programmerjake/fayalite 2025-03-21 08:48:11 +00:00
d1bd176b28 implement simulation of extern modules
programmerjake pushed to sim-extern-module at programmerjake/fayalite 2025-03-21 08:46:04 +00:00
a5a7284483 simple extern module simulation works!
programmerjake pushed to sim-extern-module at programmerjake/fayalite 2025-03-20 10:51:15 +00:00
f378b9a1d2 WIP: added running generators to settle loop
programmerjake pushed to sim-extern-module at programmerjake/fayalite 2025-03-20 03:49:19 +00:00
b4650f1bff WIP adding extern modules to simulator