programmerjake
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  • Joined on 2024-07-08
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edcc5927a5 don't cache external job failures if they could be caused by the user killing processes
7dc4417874 add test_many_memories so we catch if memories are iterated in an inconsistent order like in 838bd469ce
838bd469ce change SimulationImpl::trace_memories to a BTreeMap for consistent iteration order
b6e4cd0614 move FormalMode to crate::testing and add to prelude
3e5b2f126a make UIntInRange[Inclusive][Type] castable from/to any UInt<N> and add methods to get bit_width, start, and end
Compare 10 commits »
programmerjake merged pull request libre-chip/fayalite#42 2025-10-24 08:48:50 +00:00
misc fixes from using new fayalite version in cpu: improve UIntInRange's API, move FormalMode to testing and add to prelude, and fix inconsistent ordering of memories in vcd
programmerjake pushed to master at libre-chip/fayalite 2025-10-24 08:48:50 +00:00
7dc4417874 add test_many_memories so we catch if memories are iterated in an inconsistent order like in 838bd469ce
838bd469ce change SimulationImpl::trace_memories to a BTreeMap for consistent iteration order
b6e4cd0614 move FormalMode to crate::testing and add to prelude
3e5b2f126a make UIntInRange[Inclusive][Type] castable from/to any UInt<N> and add methods to get bit_width, start, and end
Compare 4 commits »
programmerjake deleted branch misc_fixes_for_cpu from programmerjake/fayalite 2025-10-24 08:48:50 +00:00
programmerjake created pull request libre-chip/fayalite#42 2025-10-24 08:43:48 +00:00
misc fixes from using new fayalite version in cpu: improve UIntInRange's API, move FormalMode to testing and add to prelude, and fix inconsistent ordering of memories in vcd
programmerjake pushed to misc_fixes_for_cpu at programmerjake/fayalite 2025-10-24 08:41:04 +00:00
7dc4417874 add test_many_memories so we catch if memories are iterated in an inconsistent order like in 838bd469ce
programmerjake pushed to misc_fixes_for_cpu at programmerjake/fayalite 2025-10-24 07:54:37 +00:00
838bd469ce change SimulationImpl::trace_memories to a BTreeMap for consistent iteration order
b6e4cd0614 move FormalMode to crate::testing and add to prelude
3e5b2f126a make UIntInRange[Inclusive][Type] castable from/to any UInt<N> and add methods to get bit_width, start, and end
040cefea21 add tx_only_uart example to readme
3267cb38c4 build tx_only_uart in CI
Compare 10 commits »
programmerjake created branch misc_fixes_for_cpu in programmerjake/fayalite 2025-10-24 07:54:36 +00:00
programmerjake deleted branch extend_uint_in_range from programmerjake/fayalite 2025-10-24 07:52:15 +00:00
programmerjake created branch extend_uint_in_range in programmerjake/fayalite 2025-10-24 06:56:09 +00:00
programmerjake pushed to extend_uint_in_range at programmerjake/fayalite 2025-10-24 06:56:09 +00:00
3e5b2f126a make UIntInRange[Inclusive][Type] castable from/to any UInt<N> and add methods to get bit_width, start, and end
040cefea21 add tx_only_uart example to readme
3267cb38c4 build tx_only_uart in CI
b3cc28e2b6 add transmit-only UART example
26840daf13 arty_a7: add divided clocks as available input peripherals so you're not stuck with 100MHz
Compare 10 commits »
programmerjake pushed to master at libre-chip/fayalite 2025-10-23 03:36:41 +00:00
040cefea21 add tx_only_uart example to readme
3267cb38c4 build tx_only_uart in CI
b3cc28e2b6 add transmit-only UART example
26840daf13 arty_a7: add divided clocks as available input peripherals so you're not stuck with 100MHz
Compare 4 commits »
programmerjake deleted branch add-uart-example from programmerjake/fayalite 2025-10-23 03:36:41 +00:00
programmerjake merged pull request libre-chip/fayalite#41 2025-10-23 03:36:39 +00:00
add transmit-only UART example
programmerjake pushed to add-uart-example at programmerjake/fayalite 2025-10-23 03:31:33 +00:00
040cefea21 add tx_only_uart example to readme
programmerjake pushed to add-uart-example at programmerjake/fayalite 2025-10-23 03:19:40 +00:00
e6dbeb2c85 add tx_only_uart example to readme
programmerjake pushed to add-uart-example at programmerjake/fayalite 2025-10-23 03:12:22 +00:00
3267cb38c4 build tx_only_uart in CI
programmerjake pushed to add-uart-example at programmerjake/fayalite 2025-10-23 03:11:11 +00:00
b3cc28e2b6 add transmit-only UART example
26840daf13 arty_a7: add divided clocks as available input peripherals so you're not stuck with 100MHz
Compare 2 commits »
programmerjake created pull request libre-chip/fayalite#41 2025-10-22 12:08:27 +00:00
WIP: add transmit-only UART example
programmerjake created branch add-uart-example in programmerjake/fayalite 2025-10-22 12:07:26 +00:00