link to register renaming page

src/first_arch/index.md

@@ -12,6 +12,10 @@ Possible follow-on work, order TBD:
 * Add FPGA-style programmable decoder and μOp Cache, with trap-to-software fallback for uncommon/complex ops, which allows running more ISAs such as RISC-V, older x86-32/64, more PowerISA support, and then if we can figure out the legal situation, ARM and modern x86-64. The idea is QEMU (or similar) will be compiled with a special compiler that generates both the fallback software and the bitstream for the decoder, the compiled output will be covered by QEMU's license which has some patent clauses, which hopefully helps with the legal situation. Jacob Lifshay came up with this idea [back in 2022](https://web.archive.org/web/20220612082603/https://bugs.libre-soc.org/show_bug.cgi?id=841)
 * Formal proof that the CPU doesn't have any spectre-style bugs even though it still is OoO superscalar with speculative execution. Jacob Lifshay came up with this idea [back in 2020](https://web.archive.org/web/20201021124234/https://bugs.libre-soc.org/show_bug.cgi?id=209)
 
+## Register Renaming & Internal Registers
+
+See [Register Renaming](register_renaming.md)
+
 ## Architecture Diagram
 
-![](architecture.dia.svg)
+![](architecture.dia.svg)

src/first_arch/register_renaming.md

@@ -23,4 +23,4 @@ Because each Unit doesn't necessarily have enough output registers to hold all I
 
 All Units' Output Registers are actually stored distributed in duplicated register files positioned at the beginning of every Unit's pipeline, this allows for faster reads from Units' Output Registers, as well as allowing register files to be more optimal for FPGAs since FPGAs tend to only support at most 2-port register files.
 
-![](distributed_registers.dia.svg)
+![](distributed_registers.dia.svg)