forked from libre-chip/grant-tracking
71 lines
4.4 KiB
Markdown
71 lines
4.4 KiB
Markdown
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SPDX-License-Identifier: LGPL-3.0-or-later
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See Notices.txt for copyright information
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# NLnet 2025-12-681 Grant Progress
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[Forgejo Project for this grant. TODO](https://git.libre-chip.org/libre-chip/grant-tracking/projects/TODO)
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# € 120000 Libre-Chip Programmable Decoder
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Modern computers are built on several different mutually-incompatible
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instruction sets such as x86, ARM, PowerISA, and RISC-V. Many of the most
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popular instruction sets have no high-speed libre/open-source CPUs, which
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makes those CPUs much harder to trust since you can't inspect their
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source-code to look for bugs or secret backdoors. Additionally, there are
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basically no existing modern CPUs which can run more than one of those ISAs
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without requiring software emulation, which is slow and can often be buggy.
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To solve those issues, this project is building a fast libre-licensed CPU that
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will support a programmable decoder - so the CPU can run nearly any
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instruction set at full speed. Another goal is to be able to prove that the
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resulting CPU doesn't have speculative-execution security flaws
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("Spectre"-style bugs).
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## € 45000 Adding missing features to our CPU, such as floating-point instructions, and better compatibility with the PowerISA specification.
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- € 5750 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Floating-point Add/Sub
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- € 7650 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Floating-point Mul/FMA
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- € 11500 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Floating-point Div/Sqrt
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- € 2850 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Floating-point Comparison
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- € 5750 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Floating-point Conversion from/to Integers and Rounding to Integer (floor/ceil/etc.)
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- € 11500 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Handling Floating-point control/status and PowerISA's OV/SO
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## € 20000 Add the programmable decoder and µOp cache to our CPU design.
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This task I don't actually expect to be all that complex, since
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the programmable decoder will be pretty straightforward, basically a
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pipeline of adders and muxes. the µOp cache will be a bit more
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complex, but probably simpler than the d-cache.
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- € 10000 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Add the programmable decoder
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- € 10000 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Add the µOp cache
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## € 20000 Build a compiler that can extract the decoder portion of QEMU using pattern matching and some symbolic execution of LLVM IR, converting to a HDL IR more suitable for hardware.
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- € 10000 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Make the compiler be able to symbolically execute QEMU up to where it can run QEMU's x86 and/or powerpc decoder
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- € 10000 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Make the compiler be able to extract HDL IR from symbolically executing the decoder
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## € 25000 Write code to convert the HDL IR to a bitstream we can program into the decoder.
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I expect this to be mostly running a FPGA toolchain like normal and invoking
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nextpnr with the appropriate custom FPGA model, since IIRC you can supply that
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with a config file.
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- € 5000 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Investigate what is needed for getting nextpnr to work for our programmable decoder
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- € 10000 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Write a custom FPGA model for nextpnr for our programmable decoder.
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- € 10000 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Write code to translate from the HDL IR produced by our compiler and run the HDL through nextpnr, generating a working bitstream for our programmable decoder.
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## € 10000 Work towards the Formal Proof of No Spectre bugs
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This covers working on the Formal Proof of No Spectre bugs as well
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as improvements to other software/hardware needed for that. A major
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portion of this is to figure out what exact properties we need to
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formally prove for each part of the CPU, so we can put those parts
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together to make a working proof for the entire CPU.
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- € 10000 [Issue #N](https://git.libre-chip.org/libre-chip/grant-tracking/issues/N) Work towards the Formal Proof of No Spectre bugs
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