Jacob Lifshay 85dfc8117d WIP adding FPGA support -- build module should be complete		2025-09-19 19:08:30 -07:00
..
examples	change register names to end in `_reg` by convention	2024-10-06 18:50:09 -07:00
src	WIP adding FPGA support -- build module should be complete	2025-09-19 19:08:30 -07:00
tests	add simulator support for sim-only values	2025-09-08 22:19:43 -07:00
build.rs	add test for cfgs	2024-12-28 23:39:50 -08:00
Cargo.toml	add simulator support for sim-only values	2025-09-08 22:19:43 -07:00
LICENSE.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
Notices.txt	prep for eventual publishing	2024-07-11 22:39:00 -07:00
README.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
visit_types.json	add simulator support for sim-only values	2025-09-08 22:19:43 -07:00

README.md

Fayalite

Fayalite is a library for designing digital hardware -- a hardware description language (HDL) embedded in the Rust programming language. Fayalite's semantics are based on FIRRTL as interpreted by LLVM CIRCT.

Funding

NLnet Grants

Libre-Chip CPU with proof of No Spectre bugs 2024-12-324 (progress)

This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement № 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).