forked from libre-chip/fayalite
change register names to end in _reg by convention
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parent
ec77559e2b
commit
e05c368688
SSH key fingerprint:
SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
4 changed files with 87 additions and 69 deletions
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@ -17,15 +17,15 @@ fn blinky(clock_frequency: u64) {
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let max_value = clock_frequency / 2 - 1;
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let int_ty = UInt::range_inclusive(0..=max_value);
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#[hdl]
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let counter: UInt = reg_builder().clock_domain(cd).reset(0u8.cast_to(int_ty));
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let counter_reg: UInt = reg_builder().clock_domain(cd).reset(0u8.cast_to(int_ty));
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#[hdl]
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let output_reg: Bool = reg_builder().clock_domain(cd).reset(false);
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#[hdl]
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if counter.cmp_eq(max_value) {
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connect_any(counter, 0u8);
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if counter_reg.cmp_eq(max_value) {
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connect_any(counter_reg, 0u8);
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connect(output_reg, !output_reg);
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} else {
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connect_any(counter, counter + 1_hdl_u1);
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connect_any(counter_reg, counter_reg + 1_hdl_u1);
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}
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#[hdl]
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let led: Bool = m.output();
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@ -9,6 +9,9 @@
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//!
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//! Registers follow [connection semantics], which are unlike assignments in software, so you should read it.
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//!
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//! By convention, register names end in `_reg` -- this helps you tell which values are written
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//! immediately or on the next clock edge when connecting to them.
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//!
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//! ```
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//! # use fayalite::prelude::*;
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//! # #[hdl_module]
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@ -18,11 +21,11 @@
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//! #[hdl]
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//! let cd: ClockDomain = m.input();
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//! #[hdl]
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//! let my_register: UInt<8> = reg_builder().clock_domain(cd).reset(8_hdl_u8);
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//! let my_reg: UInt<8> = reg_builder().clock_domain(cd).reset(8_hdl_u8);
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//! #[hdl]
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//! if v {
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//! // my_register is only changed when both `v` is set and `cd`'s clock edge occurs.
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//! connect(my_register, 0x45_hdl_u8);
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//! // my_reg is only changed when both `v` is set and `cd`'s clock edge occurs.
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//! connect(my_reg, 0x45_hdl_u8);
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//! }
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//! # }
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//! ```
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@ -69,11 +69,11 @@ pub fn queue<T: Type>(
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let count: UInt = m.output(count_ty);
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#[hdl]
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let inp_index = reg_builder().clock_domain(cd).reset(0.cast_to(index_ty));
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let inp_index_reg = reg_builder().clock_domain(cd).reset(0.cast_to(index_ty));
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#[hdl]
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let out_index = reg_builder().clock_domain(cd).reset(0.cast_to(index_ty));
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let out_index_reg = reg_builder().clock_domain(cd).reset(0.cast_to(index_ty));
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#[hdl]
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let maybe_full = reg_builder().clock_domain(cd).reset(false);
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let maybe_full_reg = reg_builder().clock_domain(cd).reset(false);
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#[hdl]
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let mut mem = memory(ty);
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@ -89,18 +89,18 @@ pub fn queue<T: Type>(
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connect(out_fire, ReadyValid::fire(out));
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#[hdl]
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let indexes_equal: Bool = wire();
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connect(indexes_equal, inp_index.cmp_eq(out_index));
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connect(indexes_equal, inp_index_reg.cmp_eq(out_index_reg));
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#[hdl]
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let empty: Bool = wire();
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connect(empty, indexes_equal & !maybe_full);
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connect(empty, indexes_equal & !maybe_full_reg);
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#[hdl]
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let full: Bool = wire();
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connect(full, indexes_equal & maybe_full);
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connect(full, indexes_equal & maybe_full_reg);
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connect(read_port.addr, out_index);
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connect(read_port.addr, out_index_reg);
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connect(read_port.en, true);
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connect(read_port.clk, cd.clk);
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connect(write_port.addr, inp_index);
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connect(write_port.addr, inp_index_reg);
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connect(write_port.en, inp_fire);
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connect(write_port.clk, cd.clk);
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connect(write_port.data, HdlOption::unwrap_or(inp.data, ty.uninit()));
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@ -127,33 +127,33 @@ pub fn queue<T: Type>(
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#[hdl]
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if inp_fire.cmp_ne(out_fire) {
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connect(maybe_full, inp_fire);
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connect(maybe_full_reg, inp_fire);
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}
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#[hdl]
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if inp_fire {
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#[hdl]
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if inp_index.cmp_eq(capacity.get() - 1) {
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connect_any(inp_index, 0_hdl_u0);
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if inp_index_reg.cmp_eq(capacity.get() - 1) {
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connect_any(inp_index_reg, 0_hdl_u0);
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} else {
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connect_any(inp_index, inp_index + 1_hdl_u1);
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connect_any(inp_index_reg, inp_index_reg + 1_hdl_u1);
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}
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}
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#[hdl]
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if out_fire {
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#[hdl]
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if out_index.cmp_eq(capacity.get() - 1) {
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connect_any(out_index, 0_hdl_u0);
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if out_index_reg.cmp_eq(capacity.get() - 1) {
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connect_any(out_index_reg, 0_hdl_u0);
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} else {
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connect_any(out_index, out_index + 1_hdl_u1);
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connect_any(out_index_reg, out_index_reg + 1_hdl_u1);
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}
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}
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#[hdl]
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if indexes_equal {
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#[hdl]
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if maybe_full {
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if maybe_full_reg {
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connect_any(count, capacity);
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} else {
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connect_any(count, 0_hdl_u0);
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@ -163,15 +163,18 @@ pub fn queue<T: Type>(
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debug_assert_eq!(count_ty.width(), index_ty.width() + 1);
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#[hdl]
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let count_lower = wire(index_ty);
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connect(count_lower, (inp_index - out_index).cast_to(index_ty)); // wrap
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connect(
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count_lower,
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(inp_index_reg - out_index_reg).cast_to(index_ty),
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); // wrap
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connect(count, count_lower.cast_to(count_ty));
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} else {
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debug_assert_eq!(count_ty.width(), index_ty.width());
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#[hdl]
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if inp_index.cmp_lt(out_index) {
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connect(count, inp_index + capacity - out_index);
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if inp_index_reg.cmp_lt(out_index_reg) {
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connect(count, inp_index_reg + capacity - out_index_reg);
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} else {
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connect(count, inp_index - out_index);
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connect(count, inp_index_reg - out_index_reg);
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}
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}
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}
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@ -249,89 +252,101 @@ mod tests {
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);
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#[hdl]
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let expected_count = reg_builder().clock_domain(cd).reset(0u32);
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let expected_count_reg = reg_builder().clock_domain(cd).reset(0u32);
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#[hdl]
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let next_expected_count = wire();
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connect(next_expected_count, expected_count);
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connect(expected_count, next_expected_count);
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connect(next_expected_count, expected_count_reg);
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connect(expected_count_reg, next_expected_count);
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#[hdl]
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if ReadyValid::fire(dut.inp) & !ReadyValid::fire(dut.out) {
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connect_any(next_expected_count, expected_count + 1u8);
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connect_any(next_expected_count, expected_count_reg + 1u8);
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} else if !ReadyValid::fire(dut.inp) & ReadyValid::fire(dut.out) {
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connect_any(next_expected_count, expected_count - 1u8);
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connect_any(next_expected_count, expected_count_reg - 1u8);
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}
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hdl_assert(cd.clk, expected_count.cmp_eq(dut.count), "");
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hdl_assert(cd.clk, expected_count_reg.cmp_eq(dut.count), "");
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#[hdl]
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let prev_out_ready = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
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let prev_out_ready_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
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connect_any(
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prev_out_ready,
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(prev_out_ready << 1) | out_ready.cast_to(UInt[1]),
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prev_out_ready_reg,
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(prev_out_ready_reg << 1) | out_ready.cast_to(UInt[1]),
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);
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#[hdl]
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let prev_inp_valid = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
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let prev_inp_valid_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
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connect_any(
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prev_inp_valid,
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(prev_inp_valid << 1) | HdlOption::is_some(inp_data).cast_to(UInt[1]),
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prev_inp_valid_reg,
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(prev_inp_valid_reg << 1) | HdlOption::is_some(inp_data).cast_to(UInt[1]),
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);
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hdl_assume(
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clk,
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(prev_out_ready_reg & prev_inp_valid_reg).cmp_ne(0u8),
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"",
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);
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hdl_assume(clk, (prev_out_ready & prev_inp_valid).cmp_ne(0u8), "");
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#[hdl]
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let inp_index = reg_builder().clock_domain(cd).reset(index_ty.zero());
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let inp_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
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#[hdl]
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let stored_inp_data = reg_builder().clock_domain(cd).reset(0u8);
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let stored_inp_data_reg = reg_builder().clock_domain(cd).reset(0u8);
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#[hdl]
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if let HdlSome(data) = ReadyValid::fire_data(dut.inp) {
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#[hdl]
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if inp_index.cmp_lt(index_max) {
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connect_any(inp_index, inp_index + 1u8);
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if inp_index_reg.cmp_lt(index_max) {
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connect_any(inp_index_reg, inp_index_reg + 1u8);
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#[hdl]
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if inp_index.cmp_eq(index_to_check) {
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connect(stored_inp_data, data);
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if inp_index_reg.cmp_eq(index_to_check) {
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connect(stored_inp_data_reg, data);
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}
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}
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}
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#[hdl]
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if inp_index.cmp_lt(index_to_check) {
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hdl_assert(clk, stored_inp_data.cmp_eq(0u8), "");
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if inp_index_reg.cmp_lt(index_to_check) {
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hdl_assert(clk, stored_inp_data_reg.cmp_eq(0u8), "");
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}
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#[hdl]
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let out_index = reg_builder().clock_domain(cd).reset(index_ty.zero());
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let out_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
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#[hdl]
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let stored_out_data = reg_builder().clock_domain(cd).reset(0u8);
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let stored_out_data_reg = reg_builder().clock_domain(cd).reset(0u8);
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#[hdl]
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if let HdlSome(data) = ReadyValid::fire_data(dut.out) {
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#[hdl]
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if out_index.cmp_lt(index_max) {
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connect_any(out_index, out_index + 1u8);
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if out_index_reg.cmp_lt(index_max) {
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connect_any(out_index_reg, out_index_reg + 1u8);
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#[hdl]
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if out_index.cmp_eq(index_to_check) {
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connect(stored_out_data, data);
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if out_index_reg.cmp_eq(index_to_check) {
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connect(stored_out_data_reg, data);
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}
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}
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}
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#[hdl]
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if out_index.cmp_lt(index_to_check) {
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hdl_assert(clk, stored_out_data.cmp_eq(0u8), "");
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if out_index_reg.cmp_lt(index_to_check) {
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hdl_assert(clk, stored_out_data_reg.cmp_eq(0u8), "");
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}
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hdl_assert(clk, inp_index.cmp_ge(out_index), "");
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hdl_assert(clk, inp_index_reg.cmp_ge(out_index_reg), "");
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#[hdl]
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if inp_index.cmp_lt(index_max) & out_index.cmp_lt(index_max) {
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hdl_assert(clk, expected_count.cmp_eq(inp_index - out_index), "");
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if inp_index_reg.cmp_lt(index_max) & out_index_reg.cmp_lt(index_max) {
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hdl_assert(
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clk,
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expected_count_reg.cmp_eq(inp_index_reg - out_index_reg),
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"",
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);
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} else {
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hdl_assert(clk, expected_count.cmp_ge(inp_index - out_index), "");
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hdl_assert(
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clk,
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expected_count_reg.cmp_ge(inp_index_reg - out_index_reg),
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"",
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);
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}
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#[hdl]
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if inp_index.cmp_gt(index_to_check) & out_index.cmp_gt(index_to_check) {
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hdl_assert(clk, stored_inp_data.cmp_eq(stored_out_data), "");
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if inp_index_reg.cmp_gt(index_to_check) & out_index_reg.cmp_gt(index_to_check) {
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hdl_assert(clk, stored_inp_data_reg.cmp_eq(stored_out_data_reg), "");
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}
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}
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}
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@ -41,13 +41,13 @@ pub fn my_module(width: usize) {
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#[hdl]
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let m2 = instance(module2());
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#[hdl]
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let r: UInt<8> = reg_builder().clock_domain(clock_domain).reset(8_hdl_u8);
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let r_reg: UInt<8> = reg_builder().clock_domain(clock_domain).reset(8_hdl_u8);
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connect(m2.i, i);
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connect(r, m2.o);
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connect(r_reg, m2.o);
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connect(
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o,
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#[hdl]
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[r, r, b'\r'_hdl],
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[r_reg, r_reg, b'\r'_hdl],
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);
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connect(o[1], 30_hdl_u8);
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connect(o2, i2);
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@ -109,12 +109,12 @@ circuit my_module:
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connect _bundle_literal_expr.`1`, SInt<5>(-0h3)
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connect o3, _bundle_literal_expr @[module-XXXXXXXXXX.rs 12:1]
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inst m2 of module2 @[module-XXXXXXXXXX.rs 13:1]
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regreset r: UInt<8>, clock_domain.clk, clock_domain.rst, UInt<8>(0h8) @[module-XXXXXXXXXX.rs 14:1]
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regreset r_reg: UInt<8>, clock_domain.clk, clock_domain.rst, UInt<8>(0h8) @[module-XXXXXXXXXX.rs 14:1]
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connect m2.i, i @[module-XXXXXXXXXX.rs 15:1]
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connect r, m2.o @[module-XXXXXXXXXX.rs 16:1]
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connect r_reg, m2.o @[module-XXXXXXXXXX.rs 16:1]
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wire _array_literal_expr: UInt<8>[3]
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connect _array_literal_expr[0], r
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connect _array_literal_expr[1], r
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connect _array_literal_expr[0], r_reg
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connect _array_literal_expr[1], r_reg
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connect _array_literal_expr[2], UInt<8>(0hD)
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connect o, _array_literal_expr @[module-XXXXXXXXXX.rs 17:1]
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connect o[1], UInt<8>(0h1E) @[module-XXXXXXXXXX.rs 18:1]
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