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base: programmerjake:226631594458f4137739baf98d2a9cd2c257242e
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programmerjake:master
libre-chip:master
libre-chip:square-brackets-generics-experiment
libre-chip:runtime-generics
libre-chip:type-deduction
programmerjake:v0.2.0
programmerjake:v0.1.0
libre-chip:v0.2.0
libre-chip:v0.1.0
..
compare: programmerjake:52c41bb5db06730e430b0efa99e8edcce8e26ee3
Branches Tags
programmerjake:master
libre-chip:master
libre-chip:square-brackets-generics-experiment
libre-chip:runtime-generics
libre-chip:type-deduction
programmerjake:v0.2.0
programmerjake:v0.1.0
libre-chip:v0.2.0
libre-chip:v0.1.0

No commits in common. "226631594458f4137739baf98d2a9cd2c257242e" and "52c41bb5db06730e430b0efa99e8edcce8e26ee3" have entirely different histories.
2266315944 ... 52c41bb5db

96 changed files with 1467 additions and 70885 deletions
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1
.forgejo/workflows/test.yml
View file

@ -18,7 +18,6 @@ jobs:
save-if: ${{ github.ref == 'refs/heads/master' }}
- run: rustup override set 1.93.0
- run: rustup component add rust-src
- run: make -C rocq-demo
- run: cargo test
- run: cargo build --tests --features=unstable-doc
- run: cargo test --doc --features=unstable-doc

1
crates/fayalite-proc-macros-impl/src/fold.rs
View file

@ -257,6 +257,5 @@ no_op_fold!(syn::Token![let]);
no_op_fold!(syn::Token![mut]);
no_op_fold!(syn::Token![static]);
no_op_fold!(syn::Token![struct]);
no_op_fold!(syn::Token![type]);
no_op_fold!(syn::Token![where]);
no_op_fold!(usize);

130
crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
View file

@ -3,9 +3,8 @@
use crate::{
Errors, HdlAttr, PairsIterExt,
hdl_type_common::{
CustomDebugOptions, CustomDebugTrait, ItemOptions, MakeHdlTypeExpr, MaybeParsed,
ParsedField, ParsedFieldsNamed, ParsedGenerics, SplitForImpl, TypesParser, WrappedInConst,
common_derives, create_struct_debug_impl, get_target,
ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedField, ParsedFieldsNamed, ParsedGenerics,
SplitForImpl, TypesParser, WrappedInConst, common_derives, get_target,
},
kw,
};
@ -31,7 +30,6 @@ pub(crate) struct ParsedBundle {
pub(crate) fields: MaybeParsed<ParsedFieldsNamed, FieldsNamed>,
pub(crate) field_flips: Vec<Option<HdlAttr<kw::flip, kw::hdl>>>,
pub(crate) mask_type_ident: Ident,
pub(crate) mask_type_name: String,
pub(crate) mask_type_match_variant_ident: Ident,
pub(crate) mask_type_sim_value_ident: Ident,
pub(crate) match_variant_ident: Ident,
@ -90,8 +88,6 @@ impl ParsedBundle {
no_runtime_generics: _,
cmp_eq: _,
ref get,
custom_debug: _,
custom_sim_display: _,
} = options.body;
if let Some((get, ..)) = get {
errors.error(get, "#[hdl(get(...))] is not allowed on structs");
@ -135,7 +131,6 @@ impl ParsedBundle {
fields,
field_flips,
mask_type_ident: format_ident!("__{}__MaskType", ident),
mask_type_name: format!("MaskType<{}>", ident),
mask_type_match_variant_ident: format_ident!("__{}__MaskType__MatchVariant", ident),
mask_type_sim_value_ident: format_ident!("__{}__MaskType__SimValue", ident),
match_variant_ident: format_ident!("__{}__MatchVariant", ident),
@ -453,7 +448,6 @@ impl ToTokens for ParsedBundle {
fields,
field_flips,
mask_type_ident,
mask_type_name,
mask_type_match_variant_ident,
mask_type_sim_value_ident,
match_variant_ident,
@ -470,20 +464,11 @@ impl ToTokens for ParsedBundle {
no_runtime_generics,
cmp_eq,
get: _,
custom_debug: _,
custom_sim_display,
} = &options.body;
let CustomDebugOptions {
type_: custom_debug_type,
sim: custom_debug_sim,
mask_type: custom_debug_mask_type,
mask_sim: custom_debug_mask_sim,
} = options.body.custom_debug();
let target = get_target(target, ident);
let struct_name = ident.to_string();
let mut item_attrs = attrs.clone();
item_attrs.push(common_derives(span, false));
let type_struct = ItemStruct {
item_attrs.push(common_derives(span));
ItemStruct {
attrs: item_attrs,
vis: vis.clone(),
struct_token: *struct_token,
@ -491,8 +476,8 @@ impl ToTokens for ParsedBundle {
generics: generics.into(),
fields: Fields::Named(fields.clone().into()),
semi_token: None,
};
type_struct.to_tokens(tokens);
}
.to_tokens(tokens);
let (impl_generics, type_generics, where_clause) = generics.split_for_impl();
if let (MaybeParsed::Parsed(generics), MaybeParsed::Parsed(fields), None) =
(generics, fields, no_runtime_generics)
@ -518,9 +503,6 @@ impl ToTokens for ParsedBundle {
}
let mut wrapped_in_const = WrappedInConst::new(tokens, span);
let tokens = wrapped_in_const.inner();
if custom_debug_type.is_none() {
create_struct_debug_impl(&type_struct, &struct_name, None).to_tokens(tokens);
}
let builder = Builder {
vis: vis.clone(),
struct_token: *struct_token,
@ -548,9 +530,9 @@ impl ToTokens for ParsedBundle {
mask_type_builder.to_tokens(tokens);
let unfilled_mask_type_builder_ty =
mask_type_builder.builder_struct_ty(|_| BuilderFieldState::Unfilled);
let mask_type_struct = ItemStruct {
ItemStruct {
attrs: vec![
common_derives(span, false),
common_derives(span),
parse_quote_spanned! {span=>
#[allow(non_camel_case_types, dead_code)]
},
@ -561,20 +543,17 @@ impl ToTokens for ParsedBundle {
generics: generics.into(),
fields: Fields::Named(mask_type_fields.clone()),
semi_token: None,
};
mask_type_struct.to_tokens(tokens);
if custom_debug_mask_type.is_none() {
create_struct_debug_impl(&mask_type_struct, mask_type_name, None).to_tokens(tokens);
}
.to_tokens(tokens);
let mut mask_type_match_variant_fields = mask_type_fields.clone();
for Field { ty, .. } in &mut mask_type_match_variant_fields.named {
*ty = parse_quote_spanned! {span=>
::fayalite::expr::Expr<#ty>
};
}
let mask_type_match_variant_struct = ItemStruct {
ItemStruct {
attrs: vec![
common_derives(span, false),
common_derives(span),
parse_quote_spanned! {span=>
#[allow(non_camel_case_types, dead_code)]
},
@ -585,19 +564,17 @@ impl ToTokens for ParsedBundle {
generics: generics.into(),
fields: Fields::Named(mask_type_match_variant_fields),
semi_token: None,
};
mask_type_match_variant_struct.to_tokens(tokens);
create_struct_debug_impl(&mask_type_match_variant_struct, mask_type_name, None)
.to_tokens(tokens);
}
.to_tokens(tokens);
let mut match_variant_fields = FieldsNamed::from(fields.clone());
for Field { ty, .. } in &mut match_variant_fields.named {
*ty = parse_quote_spanned! {span=>
::fayalite::expr::Expr<#ty>
};
}
let match_variant_struct = ItemStruct {
ItemStruct {
attrs: vec![
common_derives(span, false),
common_derives(span),
parse_quote_spanned! {span=>
#[allow(non_camel_case_types, dead_code)]
},
@ -608,19 +585,19 @@ impl ToTokens for ParsedBundle {
generics: generics.into(),
fields: Fields::Named(match_variant_fields),
semi_token: None,
};
match_variant_struct.to_tokens(tokens);
create_struct_debug_impl(&match_variant_struct, &struct_name, None).to_tokens(tokens);
}
.to_tokens(tokens);
let mut mask_type_sim_value_fields = mask_type_fields;
for Field { ty, .. } in &mut mask_type_sim_value_fields.named {
*ty = parse_quote_spanned! {span=>
::fayalite::sim::value::SimValue<#ty>
};
}
let mask_type_sim_value_struct = ItemStruct {
ItemStruct {
attrs: vec![
parse_quote_spanned! {span=>
#[::fayalite::__std::prelude::v1::derive(
::fayalite::__std::fmt::Debug,
::fayalite::__std::clone::Clone,
)]
},
@ -634,34 +611,19 @@ impl ToTokens for ParsedBundle {
generics: generics.into(),
fields: Fields::Named(mask_type_sim_value_fields),
semi_token: None,
};
mask_type_sim_value_struct.to_tokens(tokens);
if custom_debug_mask_sim.is_none() {
create_struct_debug_impl(
&mask_type_struct,
mask_type_name,
Some(CustomDebugTrait {
trait_path: &parse_quote_spanned! {span=>
::fayalite::ty::SimValueDebug
},
fn_name: &format_ident!("sim_value_debug", span = span),
this_arg: &parse_quote_spanned! {span=>
value: &<Self as ::fayalite::ty::Type>::SimValue
},
}),
)
.to_tokens(tokens);
}
.to_tokens(tokens);
let mut sim_value_fields = FieldsNamed::from(fields.clone());
for Field { ty, .. } in &mut sim_value_fields.named {
*ty = parse_quote_spanned! {span=>
::fayalite::sim::value::SimValue<#ty>
};
}
let sim_value_struct = ItemStruct {
ItemStruct {
attrs: vec![
parse_quote_spanned! {span=>
#[::fayalite::__std::prelude::v1::derive(
::fayalite::__std::fmt::Debug,
::fayalite::__std::clone::Clone,
)]
},
@ -675,36 +637,8 @@ impl ToTokens for ParsedBundle {
generics: generics.into(),
fields: Fields::Named(sim_value_fields),
semi_token: None,
};
sim_value_struct.to_tokens(tokens);
if custom_debug_sim.is_none() {
create_struct_debug_impl(
&type_struct,
&struct_name,
Some(CustomDebugTrait {
trait_path: &parse_quote_spanned! {span=>
::fayalite::ty::SimValueDebug
},
fn_name: &format_ident!("sim_value_debug", span = span),
this_arg: &parse_quote_spanned! {span=>
value: &<Self as ::fayalite::ty::Type>::SimValue
},
}),
)
.to_tokens(tokens);
}
if custom_sim_display.is_some() {
quote_spanned! {span=>
#[automatically_derived]
impl #impl_generics ::fayalite::__std::fmt::Display for #sim_value_ident #type_generics
#where_clause
{
fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
<#target #type_generics as ::fayalite::ty::SimValueDisplay>::sim_value_display(self, f)
}
}
}.to_tokens(tokens);
}
.to_tokens(tokens);
let this_token = Ident::new("__this", span);
let fields_token = Ident::new("__fields", span);
let self_token = Token![self](span);
@ -886,14 +820,6 @@ impl ToTokens for ParsedBundle {
}
}
#[automatically_derived]
impl #impl_generics ::fayalite::__std::fmt::Debug for #mask_type_sim_value_ident #type_generics
#where_clause
{
fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
<#mask_type_ident #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f)
}
}
#[automatically_derived]
impl #impl_generics ::fayalite::expr::ValueType for #mask_type_sim_value_ident #type_generics
#where_clause
{
@ -1054,14 +980,6 @@ impl ToTokens for ParsedBundle {
}
}
#[automatically_derived]
impl #impl_generics ::fayalite::__std::fmt::Debug for #sim_value_ident #type_generics
#where_clause
{
fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
<#target #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f)
}
}
#[automatically_derived]
impl #impl_generics ::fayalite::expr::ValueType for #sim_value_ident #type_generics
#where_clause
{
@ -1223,7 +1141,7 @@ impl ToTokens for ParsedBundle {
valueless_eq_body = quote_spanned! {span=>
let __lhs = ::fayalite::expr::ValueType::ty(&__lhs);
let __rhs = ::fayalite::expr::ValueType::ty(&__rhs);
#(#fields_valueless_eq)&*
#(#fields_valueless_eq)|*
};
valueless_ne_body = quote_spanned! {span=>
let __lhs = ::fayalite::expr::ValueType::ty(&__lhs);

295
crates/fayalite-proc-macros-impl/src/hdl_enum.rs
View file

@ -3,9 +3,8 @@
use crate::{
Errors, HdlAttr, PairsIterExt,
hdl_type_common::{
CustomDebugOptions, ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType,
SplitForImpl, TypesParser, WrappedInConst, common_derives, create_struct_debug_impl,
get_target,
ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, SplitForImpl,
TypesParser, WrappedInConst, common_derives, get_target,
},
kw,
};
@ -159,32 +158,15 @@ impl ParsedEnum {
custom_bounds,
no_static: _,
no_runtime_generics: _,
cmp_eq: _,
cmp_eq,
ref get,
custom_debug: _,
custom_sim_display: _,
} = options.body;
if let Some((cmp_eq,)) = cmp_eq {
errors.error(cmp_eq, "#[hdl(cmp_eq)] is not yet implemented for enums");
}
if let Some((get, ..)) = get {
errors.error(get, "#[hdl(get(...))] is not allowed on enums");
}
let CustomDebugOptions {
type_: _,
sim: _,
mask_type,
mask_sim,
} = options.body.custom_debug();
if let Some((mask_type,)) = mask_type {
errors.error(
mask_type,
"#[hdl(custom_debug(mask_type)] is not allowed on enums",
);
}
if let Some((mask_sim,)) = mask_sim {
errors.error(
mask_sim,
"#[hdl(custom_debug(mask_sim)] is not allowed on enums",
);
}
attrs.retain(|attr| {
if attr.path().is_ident("repr") {
errors.error(attr, "#[repr] is not supported on #[hdl] enums");
@ -246,21 +228,12 @@ impl ToTokens for ParsedEnum {
custom_bounds: _,
no_static,
no_runtime_generics,
cmp_eq,
cmp_eq: _, // TODO: implement cmp_eq for enums
get: _,
custom_debug: _,
custom_sim_display,
} = &options.body;
let CustomDebugOptions {
type_: custom_debug_type,
sim: custom_debug_sim,
mask_type: _,
mask_sim: _,
} = options.body.custom_debug();
let target = get_target(target, ident);
let enum_name = ident.to_string();
let mut struct_attrs = attrs.clone();
struct_attrs.push(common_derives(span, false));
struct_attrs.push(common_derives(span));
struct_attrs.push(parse_quote_spanned! {span=>
#[allow(non_snake_case)]
});
@ -300,7 +273,7 @@ impl ToTokens for ParsedEnum {
}
},
));
let type_struct = ItemStruct {
ItemStruct {
attrs: struct_attrs,
vis: vis.clone(),
struct_token: Token![struct](enum_token.span),
@ -315,8 +288,8 @@ impl ToTokens for ParsedEnum {
})
},
semi_token: None,
};
type_struct.to_tokens(tokens);
}
.to_tokens(tokens);
let (impl_generics, type_generics, where_clause) = generics.split_for_impl();
if let (MaybeParsed::Parsed(generics), None) = (generics, no_runtime_generics) {
generics.make_runtime_generics(tokens, vis, ident, &target, |context| {
@ -400,9 +373,6 @@ impl ToTokens for ParsedEnum {
}
.to_tokens(tokens);
}
if custom_debug_type.is_none() {
create_struct_debug_impl(&type_struct, &enum_name, None).to_tokens(tokens);
}
let mut enum_attrs = attrs.clone();
enum_attrs.push(parse_quote_spanned! {span=>
#[allow(dead_code, non_camel_case_types)]
@ -483,6 +453,7 @@ impl ToTokens for ParsedEnum {
let mut enum_attrs = attrs.clone();
enum_attrs.push(parse_quote_spanned! {span=>
#[::fayalite::__std::prelude::v1::derive(
::fayalite::__std::fmt::Debug,
::fayalite::__std::clone::Clone,
)]
});
@ -867,240 +838,6 @@ impl ToTokens for ParsedEnum {
},
)),
);
if custom_debug_sim.is_none() {
let debug_match_arms = Vec::from_iter(
variants
.iter()
.map(
|ParsedVariant {
attrs: _,
options: _,
ident,
field,
}| {
let variant_name = ident.to_string();
if let Some(_) = field {
quote_spanned! {span=>
#sim_value_ident::#ident(field, _) => {
f.debug_tuple(#variant_name).field(field).finish()
}
}
} else {
quote_spanned! {span=>
#sim_value_ident::#ident(_) => {
f.write_str(#variant_name)
}
}
}
},
)
.chain(sim_value_unknown_variant_name.as_ref().map(
|sim_value_unknown_variant_name| {
let sim_value_unknown_variant_name_str =
sim_value_unknown_variant_name.to_string();
quote_spanned! {span=>
#sim_value_ident::#sim_value_unknown_variant_name(_) => {
f.write_str(#sim_value_unknown_variant_name_str)
}
}
},
)),
);
quote_spanned! {span=>
#[automatically_derived]
impl #impl_generics ::fayalite::ty::SimValueDebug for #target #type_generics
#where_clause
{
fn sim_value_debug(
value: &<Self as ::fayalite::ty::Type>::SimValue,
f: &mut ::fayalite::__std::fmt::Formatter<'_>,
) -> ::fayalite::__std::fmt::Result {
match value {
#(#debug_match_arms)*
}
}
}
}
.to_tokens(tokens);
}
if custom_sim_display.is_some() {
quote_spanned! {span=>
#[automatically_derived]
impl #impl_generics ::fayalite::__std::fmt::Display for #sim_value_ident #type_generics
#where_clause
{
fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
<#target #type_generics as ::fayalite::ty::SimValueDisplay>::sim_value_display(self, f)
}
}
}.to_tokens(tokens);
}
if let Some((cmp_eq,)) = cmp_eq {
let mut cmp_eq_where_clause =
Generics::from(generics)
.where_clause
.unwrap_or_else(|| syn::WhereClause {
where_token: Token![where](span),
predicates: Punctuated::new(),
});
let mut variants_value_eq = vec![];
let mut variants_expr_eq = vec![];
let mut fields_valueless_eq = vec![];
for (
variant_index,
ParsedVariant {
attrs: _,
options: variant_options,
ident: variant_ident,
field,
},
) in variants.iter().enumerate()
{
let VariantOptions {} = variant_options.body;
if let Some(ParsedVariantField {
paren_token: _,
attrs: _,
options: field_options,
ty: field_ty,
comma_token: _,
}) = field
{
let FieldOptions {} = field_options.body;
cmp_eq_where_clause
.predicates
.push(parse_quote_spanned! {cmp_eq.span=>
#field_ty: ::fayalite::expr::HdlPartialEqImpl<#field_ty>
});
variants_value_eq.push(quote_spanned! {span=>
(#sim_value_ident::#variant_ident(__lhs_field, _), #sim_value_ident::#variant_ident(__rhs_field, _)) => {
::fayalite::expr::HdlPartialEqImpl::cmp_value_eq(
__lhs.#variant_ident,
::fayalite::__std::borrow::Cow::Borrowed(__lhs_field),
__rhs.#variant_ident,
::fayalite::__std::borrow::Cow::Borrowed(__rhs_field),
)
}
});
variants_expr_eq.push(quote_spanned! {span=>
{
let (#match_variant_ident::#variant_ident(__lhs), __scope) =
::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
::fayalite::__std::iter::Iterator::next(&mut __lhs_match_variant_iter)
.expect("known to have enough variants"),
)
else {
::fayalite::__std::unreachable!();
};
let (#match_variant_ident::#variant_ident(__rhs), __scope) =
::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
::fayalite::__std::iter::Iterator::nth(
&mut ::fayalite::module::match_(__rhs),
#variant_index,
)
.expect("known to have variant"),
)
else {
::fayalite::__std::unreachable!();
};
::fayalite::module::connect(__retval, ::fayalite::expr::HdlPartialEqImpl::cmp_expr_eq(__lhs, __rhs));
}
});
fields_valueless_eq.push(quote_spanned! {span=>
::fayalite::expr::HdlPartialEqImpl::cmp_valueless_eq(
::fayalite::expr::Valueless::new(__lhs.#variant_ident),
::fayalite::expr::Valueless::new(__rhs.#variant_ident),
)
});
} else {
variants_value_eq.push(quote_spanned! {span=>
(#sim_value_ident::#variant_ident(_), #sim_value_ident::#variant_ident(_)) => true,
});
variants_expr_eq.push(quote_spanned! {span=>
{
let (#match_variant_ident::#variant_ident, __scope) =
::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
::fayalite::__std::iter::Iterator::next(&mut __lhs_match_variant_iter)
.expect("known to have enough variants"),
)
else {
::fayalite::__std::unreachable!();
};
let (#match_variant_ident::#variant_ident, __scope) =
::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
::fayalite::__std::iter::Iterator::nth(
&mut ::fayalite::module::match_(__rhs),
#variant_index,
)
.expect("known to have variant"),
)
else {
::fayalite::__std::unreachable!();
};
::fayalite::module::connect(__retval, true);
}
});
}
}
if let Some(sim_value_unknown_variant_name) = &sim_value_unknown_variant_name {
variants_value_eq.push(quote_spanned! {span=>
(#sim_value_ident::#sim_value_unknown_variant_name(__lhs_unknown), #sim_value_ident::#sim_value_unknown_variant_name(__rhs_unknown)) => {
__lhs_unknown == __rhs_unknown
}
});
}
let valueless_eq_body = if fields_valueless_eq.is_empty() {
quote_spanned! {span=>
::fayalite::expr::Valueless::new(::fayalite::int::Bool)
}
} else {
quote_spanned! {span=>
let __lhs = ::fayalite::expr::ValueType::ty(&__lhs);
let __rhs = ::fayalite::expr::ValueType::ty(&__rhs);
#(#fields_valueless_eq)&*
}
};
let cmp_expr_eq_wire_name = format!("{ident}_cmp_eq");
quote_spanned! {span=>
#[automatically_derived]
impl #impl_generics ::fayalite::expr::HdlPartialEqImpl<Self> for #target #type_generics
#cmp_eq_where_clause
{
#[track_caller]
fn cmp_value_eq(
__lhs: Self,
__lhs_value: ::fayalite::__std::borrow::Cow<'_, <Self as ::fayalite::ty::Type>::SimValue>,
__rhs: Self,
__rhs_value: ::fayalite::__std::borrow::Cow<'_, <Self as ::fayalite::ty::Type>::SimValue>,
) -> ::fayalite::__std::primitive::bool {
match (&*__lhs_value, &*__rhs_value) {
#(#variants_value_eq)*
_ => false,
}
}
#[track_caller]
fn cmp_expr_eq(
__lhs: ::fayalite::expr::Expr<Self>,
__rhs: ::fayalite::expr::Expr<Self>,
) -> ::fayalite::expr::Expr<::fayalite::int::Bool> {
let __retval = ::fayalite::module::wire(::fayalite::module::ImplicitName(#cmp_expr_eq_wire_name), ::fayalite::int::Bool);
::fayalite::module::connect(__retval, false);
let mut __lhs_match_variant_iter = ::fayalite::module::match_(__lhs);
#(#variants_expr_eq)*
__retval
}
#[track_caller]
fn cmp_valueless_eq(
__lhs: ::fayalite::expr::Valueless<Self>,
__rhs: ::fayalite::expr::Valueless<Self>,
) -> ::fayalite::expr::Valueless<::fayalite::int::Bool> {
#valueless_eq_body
}
}
}
.to_tokens(tokens);
}
let variants_len = variants.len();
quote_spanned! {span=>
#[automatically_derived]
@ -1197,14 +934,6 @@ impl ToTokens for ParsedEnum {
}
}
#[automatically_derived]
impl #impl_generics ::fayalite::__std::fmt::Debug for #sim_value_ident #type_generics
#where_clause
{
fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
<#target #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f)
}
}
#[automatically_derived]
impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#target #type_generics>
for #sim_value_ident #type_generics
#where_clause

28
crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs
View file

@ -215,8 +215,6 @@ impl ParsedTypeAlias {
no_runtime_generics,
cmp_eq,
get: _,
ref custom_debug,
custom_sim_display,
} = options.body;
if let Some((no_static,)) = no_static {
errors.error(no_static, "no_static is not valid on type aliases");
@ -236,15 +234,6 @@ impl ParsedTypeAlias {
if let Some((cmp_eq,)) = cmp_eq {
errors.error(cmp_eq, "cmp_eq is not valid on type aliases");
}
if let Some((custom_debug, _, _)) = custom_debug {
errors.error(custom_debug, "custom_debug is not valid on type aliases");
}
if let Some((custom_sim_display,)) = custom_sim_display {
errors.error(
custom_sim_display,
"custom_sim_display is not valid on type aliases",
);
}
if let Some((custom_bounds,)) = custom_bounds {
errors.error(
custom_bounds,
@ -298,8 +287,6 @@ impl ParsedTypeAlias {
no_runtime_generics: _,
cmp_eq,
ref mut get,
ref custom_debug,
custom_sim_display,
} = options.body;
if let Some(get) = get.take() {
return Self::parse_phantom_const_accessor(
@ -324,15 +311,6 @@ impl ParsedTypeAlias {
if let Some((cmp_eq,)) = cmp_eq {
errors.error(cmp_eq, "cmp_eq is not valid on type aliases");
}
if let Some((custom_debug, _, _)) = custom_debug {
errors.error(custom_debug, "custom_debug is not valid on type aliases");
}
if let Some((custom_sim_display,)) = custom_sim_display {
errors.error(
custom_sim_display,
"custom_sim_display is not valid on type aliases",
);
}
let generics = if custom_bounds.is_some() {
MaybeParsed::Unrecognized(generics)
} else if let Some(generics) = errors.ok(ParsedGenerics::parse(&mut generics)) {
@ -378,8 +356,6 @@ impl ToTokens for ParsedTypeAlias {
no_runtime_generics,
cmp_eq: _,
get: _,
custom_debug: _,
custom_sim_display: _,
} = &options.body;
let target = get_target(target, ident);
let mut type_attrs = attrs.clone();
@ -426,8 +402,6 @@ impl ToTokens for ParsedTypeAlias {
no_runtime_generics: _,
cmp_eq: _,
get: _,
custom_debug: _,
custom_sim_display: _,
} = &options.body;
let span = ident.span();
let mut type_attrs = attrs.clone();
@ -453,7 +427,7 @@ impl ToTokens for ParsedTypeAlias {
format_ident!("__{}__GenericsAccumulation", ident);
ItemStruct {
attrs: vec![
common_derives(span, true),
common_derives(span),
parse_quote_spanned! {span=>
#[allow(non_camel_case_types)]
},

168
crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
View file

@ -7,10 +7,10 @@ use std::{collections::HashMap, fmt, mem};
use syn::{
AngleBracketedGenericArguments, Attribute, Block, ConstParam, Expr, ExprBlock, ExprGroup,
ExprIndex, ExprParen, ExprPath, ExprTuple, Field, FieldMutability, Fields, FieldsNamed,
FieldsUnnamed, FnArg, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index,
ItemStruct, Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound,
Turbofish, Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath,
TypeTuple, Visibility, WhereClause, WherePredicate,
FieldsUnnamed, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index, ItemStruct,
Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound, Turbofish,
Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath, TypeTuple,
Visibility, WhereClause, WherePredicate,
parse::{Parse, ParseStream},
parse_quote, parse_quote_spanned,
punctuated::{Pair, Punctuated},
@ -18,17 +18,6 @@ use syn::{
token::{Brace, Bracket, Paren},
};
crate::options! {
#[options = CustomDebugOptions]
#[no_ident_fragment]
pub(crate) enum CustomDebugOption {
Type(type_),
Sim(sim),
MaskType(mask_type),
MaskSim(mask_sim),
}
}
crate::options! {
#[options = ItemOptions]
pub(crate) enum ItemOption {
@ -39,8 +28,6 @@ crate::options! {
NoRuntimeGenerics(no_runtime_generics),
CmpEq(cmp_eq),
Get(get, Expr),
CustomDebug(custom_debug, CustomDebugOptions),
CustomSimDisplay(custom_sim_display),
}
}
@ -54,36 +41,8 @@ impl ItemOptions {
{
self.no_static = Some((kw::no_static(custom_bounds.span),));
}
if let Some((kw, _, custom_debug)) = &mut self.custom_debug {
if let CustomDebugOptions {
type_: None,
sim: None,
mask_type: None,
mask_sim: None,
} = custom_debug
{
*custom_debug = CustomDebugOptions {
type_: Some((kw::type_(kw.span),)),
sim: Some((kw::sim(kw.span),)),
mask_type: None,
mask_sim: None,
};
}
}
Ok(())
}
pub(crate) fn custom_debug(&self) -> &CustomDebugOptions {
self.custom_debug.as_ref().map(|v| &v.2).unwrap_or(
const {
&CustomDebugOptions {
type_: None,
sim: None,
mask_type: None,
mask_sim: None,
}
},
)
}
}
pub(crate) struct WrappedInConst<'a> {
@ -125,17 +84,10 @@ pub(crate) fn get_target(target: &Option<(kw::target, Paren, Path)>, item_ident:
}
}
pub(crate) fn common_derives(span: Span, include_debug: bool) -> Attribute {
let debug = include_debug
.then(|| {
quote_spanned! {span=>
::fayalite::__std::fmt::Debug
}
})
.into_iter();
pub(crate) fn common_derives(span: Span) -> Attribute {
parse_quote_spanned! {span=>
#[::fayalite::__std::prelude::v1::derive(
#(#debug,)*
::fayalite::__std::fmt::Debug,
::fayalite::__std::cmp::Eq,
::fayalite::__std::cmp::PartialEq,
::fayalite::__std::hash::Hash,
@ -3023,7 +2975,7 @@ impl ParsedGenerics {
let span = ident.span();
ItemStruct {
attrs: vec![
common_derives(span, true),
common_derives(span),
parse_quote_spanned! {span=>
#[allow(non_camel_case_types)]
},
@ -4781,109 +4733,3 @@ impl ParsedVisibility {
.map(|ord| if ord.is_lt() { self } else { other })
}
}
pub(crate) struct CustomDebugTrait<'a> {
pub(crate) trait_path: &'a Path,
pub(crate) fn_name: &'a Ident,
pub(crate) this_arg: &'a FnArg,
}
#[must_use]
pub(crate) fn create_struct_debug_impl(
item_struct: &ItemStruct,
debug_struct_name: &str,
custom_debug_trait: Option<CustomDebugTrait<'_>>,
) -> TokenStream {
let ident = &item_struct.ident;
let span = ident.span();
let (impl_generics, type_generics, where_clause) = item_struct.generics.split_for_impl();
let trait_path;
let fn_name;
let this_arg;
let CustomDebugTrait {
trait_path,
fn_name,
this_arg,
} = match custom_debug_trait {
Some(v) => v,
None => {
trait_path = parse_quote_spanned! {span=>
::fayalite::__std::fmt::Debug
};
fn_name = parse_quote_spanned! {span=>
fmt
};
this_arg = parse_quote_spanned! {span=>
&self
};
CustomDebugTrait {
trait_path: &trait_path,
fn_name: &fn_name,
this_arg: &this_arg,
}
}
};
let this_arg_name = match this_arg {
FnArg::Receiver(this_arg) => this_arg.self_token.to_token_stream(),
FnArg::Typed(this_arg) => match &*this_arg.pat {
syn::Pat::Ident(pat_ident) => pat_ident.ident.to_token_stream(),
_ => unreachable!(),
},
};
match &item_struct.fields {
Fields::Named(fields) => {
let field_idents = fields
.named
.iter()
.map(|v| v.ident.as_ref().expect("known to have field name"));
let field_names = field_idents.clone().map(|v| v.to_string());
quote_spanned! {span=>
#[automatically_derived]
impl #impl_generics #trait_path for #ident #type_generics
#where_clause
{
fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
let _ = #this_arg_name;
f.debug_struct(#debug_struct_name)
#(.field(#field_names, &#this_arg_name.#field_idents))*
.finish()
}
}
}
}
Fields::Unnamed(fields) => {
let field_members = fields
.unnamed
.iter()
.enumerate()
.map(|(index, _)| syn::Index {
index: index as _,
span,
});
quote_spanned! {span=>
#[automatically_derived]
impl #impl_generics #trait_path for #ident #type_generics
#where_clause
{
fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
let _ = #this_arg_name;
f.debug_tuple(#debug_struct_name)
#(.field(&#this_arg_name.#field_members))*
.finish()
}
}
}
}
Fields::Unit => quote_spanned! {ident.span()=>
#[automatically_derived]
impl #impl_generics #trait_path for #ident #type_generics
#where_clause
{
fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result {
let _ = #this_arg_name;
f.write_str(#debug_struct_name)
}
}
},
}
}

5
crates/fayalite-proc-macros-impl/src/lib.rs
View file

@ -42,7 +42,6 @@ pub(crate) trait CustomToken:
mod kw {
pub(crate) use syn::token::Extern as extern_;
pub(crate) use syn::token::Type as type_;
macro_rules! custom_keyword {
($kw:ident) => {
@ -76,8 +75,6 @@ mod kw {
custom_keyword!(cmp_eq);
custom_keyword!(connect_inexact);
custom_keyword!(custom_bounds);
custom_keyword!(custom_debug);
custom_keyword!(custom_sim_display);
custom_keyword!(flip);
custom_keyword!(get);
custom_keyword!(hdl);
@ -86,8 +83,6 @@ mod kw {
custom_keyword!(input);
custom_keyword!(instance);
custom_keyword!(m);
custom_keyword!(mask_sim);
custom_keyword!(mask_type);
custom_keyword!(memory);
custom_keyword!(memory_array);
custom_keyword!(memory_with_init);

16
crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
View file

@ -1096,9 +1096,11 @@ impl Visitor<'_> {
let (#(#bindings,)*) = {
type __MatchTy<T> = <T as ::fayalite::ty::Type>::SimValue;
let __match_value = #expr;
// use method syntax to deduce what type to convert to
let __match_value = ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value)
.__fayalite_match_sim_value();
let __match_value = {
use ::fayalite::sim::value::match_sim_value::*;
// use method syntax to deduce the correct trait to call
::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value()
};
#let_token #pat #eq_token __match_value #semi_token
(#(#bindings_idents,)*)
};
@ -1170,9 +1172,11 @@ impl Visitor<'_> {
{
type __MatchTy<T> = <T as ::fayalite::ty::Type>::SimValue;
let __match_value = #expr;
// use method syntax to deduce what type to convert to
let __match_value = ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value)
.__fayalite_match_sim_value();
let __match_value = {
use ::fayalite::sim::value::match_sim_value::*;
// use method syntax to deduce the correct trait to call
::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value()
};
#match_token __match_value {
#(#arms)*
}

37
crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs
View file

@ -95,11 +95,11 @@
//! }
//!
//! #[hdl]
//! fn destructure_inner<T: Type>(v: <MyStruct<T> as Type>::SimValue) {
//! fn destructure_to_sim_value<'a, T: Type>(v: impl ToSimValue<Type = MyStruct<T>>) {
//! #[hdl(sim)]
//! let MyStruct::<T> {
//! a,
//! mut b,
//! b,
//! c,
//! } = v;
//!
@ -107,38 +107,5 @@
//! let _: SimValue<UInt<8>> = a;
//! let _: SimValue<Bool> = b;
//! let _: SimValue<T> = c;
//! *b = false; // can modify b since mut was used
//! }
//!
//! #[hdl]
//! fn destructure_inner_ref<'a, T: Type>(v: &'a <MyStruct<T> as Type>::SimValue) {
//! #[hdl(sim)]
//! let MyStruct::<T> {
//! a,
//! b,
//! c,
//! } = v;
//!
//! // that gives these types:
//! let _: &'a SimValue<UInt<8>> = a;
//! let _: &'a SimValue<Bool> = b;
//! let _: &'a SimValue<T> = c;
//! }
//!
//! #[hdl]
//! fn destructure_inner_mut<'a, T: Type>(v: &'a mut <MyStruct<T> as Type>::SimValue) {
//! #[hdl(sim)]
//! let MyStruct::<T> {
//! a,
//! b,
//! c,
//! } = v;
//!
//! **b = true; // you can modify v by modifying b which borrows from it
//!
//! // that gives these types:
//! let _: &'a mut SimValue<UInt<8>> = a;
//! let _: &'a mut SimValue<Bool> = b;
//! let _: &'a mut SimValue<T> = c;
//! }
//! ```

40
crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs
View file

@ -72,47 +72,15 @@
//! }
//!
//! #[hdl]
//! fn match_inner_move<T: Type>(v: <MyEnum<T> as Type>::SimValue) -> String {
//! fn match_to_sim_value<'a, T: Type>(v: impl ToSimValue<Type = MyEnum<T>>) {
//! #[hdl(sim)]
//! match v {
//! MyEnum::<T>::A => String::from("got A"),
//! MyEnum::<T>::B(mut b) => {
//! MyEnum::<T>::A => println!("got A"),
//! MyEnum::<T>::B(b) => {
//! let _: SimValue<Bool> = b; // b has this type
//! let text = format!("got B({b})");
//! *b = true; // can modify b since mut was used
//! text
//! }
//! _ => String::from("something else"),
//! }
//! }
//!
//! #[hdl]
//! fn match_inner_ref<'a, T: Type>(v: &'a <MyEnum<T> as Type>::SimValue) -> u32 {
//! #[hdl(sim)]
//! match v {
//! MyEnum::<T>::A => 1,
//! MyEnum::<T>::B(b) => {
//! let _: &'a SimValue<Bool> = b; // b has this type
//! println!("got B({b})");
//! 5
//! }
//! _ => 42,
//! }
//! }
//!
//! #[hdl]
//! fn match_inner_mut<'a, T: Type>(v: &'a mut <MyEnum<T> as Type>::SimValue) -> Option<&'a mut SimValue<T>> {
//! #[hdl(sim)]
//! match v {
//! MyEnum::<T>::A => None,
//! MyEnum::<T>::B(b) => {
//! println!("got B({b})");
//! **b = true; // you can modify v by modifying b which borrows from it
//! let _: &'a mut SimValue<Bool> = b; // b has this type
//! None
//! }
//! MyEnum::<T>::C(v) => Some(v), // you can return matched values
//! _ => None, // HDL enums can have invalid discriminants, so we need this extra match arm
//! _ => println!("something else"),
//! }
//! }
//! ```

17
crates/fayalite/src/array.rs
View file

@ -13,13 +13,13 @@ use crate::{
source_location::SourceLocation,
ty::{
CanonicalType, MatchVariantWithoutScope, OpaqueSimValueSlice, OpaqueSimValueWriter,
OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, TypeWithDeref,
OpaqueSimValueWritten, StaticType, Type, TypeProperties, TypeWithDeref,
serde_impls::SerdeCanonicalType,
},
util::ConstUsize,
};
use serde::{Deserialize, Deserializer, Serialize, Serializer, de::Error};
use std::{borrow::Cow, fmt, iter::FusedIterator, ops::Index};
use std::{borrow::Cow, iter::FusedIterator, ops::Index};
#[derive(Copy, Clone, PartialEq, Eq, Hash)]
pub struct ArrayType<T: Type = CanonicalType, Len: Size = DynSize> {
@ -28,8 +28,8 @@ pub struct ArrayType<T: Type = CanonicalType, Len: Size = DynSize> {
type_properties: TypeProperties,
}
impl<T: Type, Len: Size> fmt::Debug for ArrayType<T, Len> {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
impl<T: Type, Len: Size> std::fmt::Debug for ArrayType<T, Len> {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
write!(f, "Array<{:?}, {}>", self.element, self.len())
}
}
@ -182,15 +182,6 @@ impl<T: Type + Visit<State>, Len: Size, State: Visitor + ?Sized> Visit<State>
}
}
impl<T: Type, Len: Size> SimValueDebug for ArrayType<T, Len> {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl<T: Type, Len: Size> Type for ArrayType<T, Len> {
type BaseType = Array;
type MaskType = ArrayType<T::MaskType, Len>;

30
crates/fayalite/src/bundle.rs
View file

@ -14,8 +14,8 @@ use crate::{
source_location::SourceLocation,
ty::{
CanonicalType, MatchVariantWithoutScope, OpaqueSimValue, OpaqueSimValueSize,
OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug,
StaticType, Type, TypeProperties, TypeWithDeref, impl_match_variant_as_self,
OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type,
TypeProperties, TypeWithDeref, impl_match_variant_as_self,
},
util::HashMap,
};
@ -271,15 +271,6 @@ impl Type for Bundle {
}
}
impl SimValueDebug for Bundle {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
pub trait BundleType: Type<BaseType = Bundle> {
type Builder: Default;
fn fields(&self) -> Interned<[BundleField]>;
@ -480,14 +471,6 @@ macro_rules! impl_tuples {
#[var($var)]
})*]
}
impl<$($T: Type,)*> SimValueDebug for ($($T,)*) {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl<$($T: Type,)*> Type for ($($T,)*) {
type BaseType = Bundle;
type MaskType = ($($T::MaskType,)*);
@ -790,15 +773,6 @@ impl_tuples! {
]
}
impl<T: ?Sized + Send + Sync + 'static> SimValueDebug for PhantomData<T> {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl<T: ?Sized + Send + Sync + 'static> Type for PhantomData<T> {
type BaseType = Bundle;
type MaskType = ();

14
crates/fayalite/src/clock.rs
View file

@ -1,6 +1,5 @@
// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
use crate::{
expr::{Expr, ValueType},
hdl,
@ -10,12 +9,10 @@ use crate::{
source_location::SourceLocation,
ty::{
CanonicalType, OpaqueSimValueSize, OpaqueSimValueSlice, OpaqueSimValueWriter,
OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties,
impl_match_variant_as_self,
OpaqueSimValueWritten, StaticType, Type, TypeProperties, impl_match_variant_as_self,
},
};
use bitvec::{bits, order::Lsb0};
use std::fmt;
#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)]
pub struct Clock;
@ -72,15 +69,6 @@ impl Type for Clock {
}
}
impl SimValueDebug for Clock {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl Clock {
pub fn type_properties(self) -> TypeProperties {
Self::TYPE_PROPERTIES

221
crates/fayalite/src/enum_.rs
View file

@ -2,7 +2,7 @@
// See Notices.txt for copyright information
use crate::{
expr::{Expr, ToExpr, ValueType, ops::VariantAccess},
expr::{Expr, HdlPartialEq, HdlPartialEqImpl, ToExpr, ValueType, ops::VariantAccess},
hdl,
int::{Bool, UIntValue},
intern::{Intern, Interned},
@ -10,18 +10,18 @@ use crate::{
EnumMatchVariantAndInactiveScopeImpl, EnumMatchVariantsIterImpl, Scope, connect,
enum_match_variants_helper, incomplete_wire, wire,
},
sim::value::{SimValue, ToSimValue, ToSimValueWithType},
sim::value::SimValue,
source_location::SourceLocation,
ty::{
CanonicalType, MatchVariantAndInactiveScope, OpaqueSimValue, OpaqueSimValueSize,
OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug,
StaticType, Type, TypeProperties,
OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type,
TypeProperties,
},
util::HashMap,
};
use bitvec::{order::Lsb0, slice::BitSlice, view::BitView};
use serde::{Deserialize, Serialize};
use std::{convert::Infallible, fmt, iter::FusedIterator, sync::Arc};
use std::{borrow::Cow, convert::Infallible, fmt, iter::FusedIterator, sync::Arc};
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub struct EnumVariant {
@ -410,15 +410,6 @@ impl Type for Enum {
}
}
impl SimValueDebug for Enum {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
#[derive(Clone, PartialEq, Eq, Hash, Debug, Default)]
pub struct EnumPaddingSimValue {
bits: Option<UIntValue>,
@ -732,12 +723,95 @@ pub fn enum_type_to_sim_builder<T: EnumType>(v: T) -> T::SimBuilder {
v.into()
}
#[hdl(cmp_eq)]
#[hdl]
pub enum HdlOption<T: Type> {
HdlNone,
HdlSome(T),
}
impl<Lhs: Type + HdlPartialEqImpl<Rhs>, Rhs: Type> HdlPartialEqImpl<HdlOption<Rhs>>
for HdlOption<Lhs>
{
fn cmp_value_eq(
lhs: Self,
lhs_value: Cow<'_, Self::SimValue>,
rhs: HdlOption<Rhs>,
rhs_value: Cow<'_, <HdlOption<Rhs> as Type>::SimValue>,
) -> bool {
type SimValueMatch<T> = <T as Type>::SimValue;
match (&*lhs_value, &*rhs_value) {
(SimValueMatch::<Self>::HdlNone(_), SimValueMatch::<HdlOption<Rhs>>::HdlNone(_)) => {
true
}
(SimValueMatch::<Self>::HdlSome(..), SimValueMatch::<HdlOption<Rhs>>::HdlNone(_))
| (SimValueMatch::<Self>::HdlNone(_), SimValueMatch::<HdlOption<Rhs>>::HdlSome(..)) => {
false
}
(
SimValueMatch::<Self>::HdlSome(l, _),
SimValueMatch::<HdlOption<Rhs>>::HdlSome(r, _),
) => HdlPartialEqImpl::cmp_value_eq(
lhs.HdlSome,
Cow::Borrowed(&**l),
rhs.HdlSome,
Cow::Borrowed(&**r),
),
}
}
#[hdl]
fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<HdlOption<Rhs>>) -> Expr<Bool> {
#[hdl]
let cmp_eq = wire();
#[hdl]
match lhs {
HdlSome(lhs) =>
{
#[hdl]
match rhs {
HdlSome(rhs) => connect(cmp_eq, lhs.cmp_eq(rhs)),
HdlNone => connect(cmp_eq, false),
}
}
HdlNone =>
{
#[hdl]
match rhs {
HdlSome(_) => connect(cmp_eq, false),
HdlNone => connect(cmp_eq, true),
}
}
}
cmp_eq
}
#[hdl]
fn cmp_expr_ne(lhs: Expr<Self>, rhs: Expr<HdlOption<Rhs>>) -> Expr<Bool> {
#[hdl]
let cmp_ne = wire();
#[hdl]
match lhs {
HdlSome(lhs) =>
{
#[hdl]
match rhs {
HdlSome(rhs) => connect(cmp_ne, lhs.cmp_ne(rhs)),
HdlNone => connect(cmp_ne, true),
}
}
HdlNone =>
{
#[hdl]
match rhs {
HdlSome(_) => connect(cmp_ne, true),
HdlNone => connect(cmp_ne, false),
}
}
}
cmp_ne
}
}
#[allow(non_snake_case)]
pub fn HdlNone<T: StaticType>() -> Expr<HdlOption<T>> {
HdlOption[T::TYPE].HdlNone()
@ -749,123 +823,6 @@ pub fn HdlSome<T: Type>(value: impl ToExpr<Type = T>) -> Expr<HdlOption<T>> {
HdlOption[value.ty()].HdlSome(value)
}
impl<T: Type> From<SimValue<HdlOption<T>>> for Option<SimValue<T>> {
#[hdl]
fn from(value: SimValue<HdlOption<T>>) -> Self {
#[hdl(sim)]
match value {
HdlSome(v) => Some(v),
HdlNone => None,
}
}
}
impl<'a, T: Type> From<&'a SimValue<HdlOption<T>>> for Option<&'a SimValue<T>> {
#[hdl]
fn from(value: &'a SimValue<HdlOption<T>>) -> Self {
#[hdl(sim)]
match value {
HdlSome(v) => Some(v),
HdlNone => None,
}
}
}
impl<'a, T: Type> From<&'a mut SimValue<HdlOption<T>>> for Option<&'a mut SimValue<T>> {
#[hdl]
fn from(value: &'a mut SimValue<HdlOption<T>>) -> Self {
#[hdl(sim)]
match value {
HdlSome(v) => Some(v),
HdlNone => None,
}
}
}
impl<T: ValueType<Type: StaticType<MaskType: StaticType>>> ValueType for Option<T> {
type Type = HdlOption<T::Type>;
type ValueCategory = T::ValueCategory;
fn ty(&self) -> Self::Type {
StaticType::TYPE
}
}
impl<T: Type, V: ToSimValueWithType<T>> ToSimValueWithType<HdlOption<T>> for Option<V> {
#[hdl]
fn to_sim_value_with_type(&self, ty: HdlOption<T>) -> SimValue<HdlOption<T>> {
match self {
Some(v) =>
{
#[hdl(sim)]
ty.HdlSome(v)
}
None =>
{
#[hdl(sim)]
ty.HdlNone()
}
}
}
#[hdl]
fn into_sim_value_with_type(self, ty: HdlOption<T>) -> SimValue<HdlOption<T>> {
match self {
Some(v) =>
{
#[hdl(sim)]
ty.HdlSome(v)
}
None =>
{
#[hdl(sim)]
ty.HdlNone()
}
}
}
}
impl<T: ToSimValue<Type: StaticType<MaskType: StaticType>>> ToSimValue for Option<T> {
#[hdl]
fn to_sim_value(&self) -> SimValue<Self::Type> {
match self {
Some(v) =>
{
#[hdl(sim)]
HdlSome(v)
}
None =>
{
#[hdl(sim)]
HdlNone()
}
}
}
#[hdl]
fn into_sim_value(self) -> SimValue<Self::Type> {
match self {
Some(v) =>
{
#[hdl(sim)]
HdlSome(v)
}
None =>
{
#[hdl(sim)]
HdlNone()
}
}
}
}
impl<T: ToExpr<Type: StaticType<MaskType: StaticType>>> ToExpr for Option<T> {
fn to_expr(&self) -> Expr<Self::Type> {
match self {
Some(v) => HdlSome(v),
None => HdlNone(),
}
}
}
impl<T: Type> HdlOption<T> {
#[track_caller]
pub fn try_map<R: Type, E>(

31
crates/fayalite/src/int.rs
View file

@ -15,8 +15,8 @@ use crate::{
source_location::SourceLocation,
ty::{
CanonicalType, FillInDefaultedGenerics, OpaqueSimValueSize, OpaqueSimValueSlice,
OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, SimValueDisplay, StaticType,
Type, TypeProperties, impl_match_variant_as_self,
OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, TypeProperties,
impl_match_variant_as_self,
},
util::{ConstBool, ConstUsize, GenericConstBool, GenericConstUsize, interned_bit, slice_range},
};
@ -1019,24 +1019,6 @@ macro_rules! impl_int {
}
}
impl<Width: Size> SimValueDebug for $name<Width> {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl<Width: Size> SimValueDisplay for $name<Width> {
fn sim_value_display(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Display::fmt(value, f)
}
}
impl<Width: KnownSize> Default for $name<Width> {
fn default() -> Self {
Self::TYPE
@ -1917,15 +1899,6 @@ impl Type for Bool {
}
}
impl SimValueDebug for Bool {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl StaticType for Bool {
const TYPE: Self = Bool;
const MASK_TYPE: Self::MaskType = Bool;

20
crates/fayalite/src/int/uint_in_range.rs
View file

@ -14,7 +14,7 @@ use crate::{
source_location::SourceLocation,
ty::{
CanonicalType, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten,
SimValueDebug, StaticType, Type, TypeProperties, impl_match_variant_as_self,
StaticType, Type, TypeProperties, impl_match_variant_as_self,
},
};
use bitvec::{order::Lsb0, view::BitView};
@ -94,15 +94,6 @@ impl Type for UIntInRangeMaskType {
}
}
impl SimValueDebug for UIntInRangeMaskType {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl BundleType for UIntInRangeMaskType {
type Builder = NoBuilder;
@ -348,15 +339,6 @@ macro_rules! define_uint_in_range_type {
}
}
impl<Start: Size, End: Size> SimValueDebug for $UIntInRangeType<Start, End> {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl<Start: Size, End: Size> fmt::Debug for $UIntInRangeType<Start, End> {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
let Self { value, range } = self;

11
crates/fayalite/src/phantom_const.rs
View file

@ -9,7 +9,7 @@ use crate::{
source_location::SourceLocation,
ty::{
CanonicalType, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten,
SimValueDebug, StaticType, Type, TypeProperties, impl_match_variant_as_self,
StaticType, Type, TypeProperties, impl_match_variant_as_self,
serde_impls::{SerdeCanonicalType, SerdePhantomConst},
},
};
@ -327,15 +327,6 @@ impl<T: ?Sized + PhantomConstValue> Type for PhantomConst<T> {
}
}
impl<T: ?Sized + PhantomConstValue> SimValueDebug for PhantomConst<T> {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl<T: ?Sized + PhantomConstValue> Default for PhantomConst<T>
where
Interned<T>: Default,

14
crates/fayalite/src/reset.rs
View file

@ -1,6 +1,5 @@
// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
use crate::{
clock::Clock,
expr::{CastToImpl, Expr, ValueType},
@ -9,13 +8,11 @@ use crate::{
source_location::SourceLocation,
ty::{
CanonicalType, OpaqueSimValueSize, OpaqueSimValueSlice, OpaqueSimValueWriter,
OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties,
impl_match_variant_as_self,
OpaqueSimValueWritten, StaticType, Type, TypeProperties, impl_match_variant_as_self,
},
util::ConstUsize,
};
use bitvec::{bits, order::Lsb0};
use std::fmt;
mod sealed {
pub trait ResetTypeSealed {}
@ -103,15 +100,6 @@ macro_rules! reset_type {
}
}
impl SimValueDebug for $name {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl $name {
pub fn type_properties(self) -> TypeProperties {
Self::TYPE_PROPERTIES

49
crates/fayalite/src/sim.rs
View file

@ -828,7 +828,6 @@ where
#[derive(Clone, PartialEq, Eq, Hash, Debug)]
pub(crate) struct SimTrace<K, S> {
kind: K,
maybe_changed: bool,
state: S,
last_state: S,
}
@ -849,14 +848,12 @@ impl<K: fmt::Debug> SimTraceDebug<TraceScalarId> for SimTrace<K, ()> {
fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result {
let Self {
kind,
maybe_changed,
state,
last_state,
} = self;
f.debug_struct("SimTrace")
.field("id", &id)
.field("kind", kind)
.field("maybe_changed", maybe_changed)
.field("state", state)
.field("last_state", last_state)
.finish()
@ -867,14 +864,12 @@ impl<K: fmt::Debug> SimTraceDebug<TraceScalarId> for SimTrace<K, SimTraceState>
fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result {
let Self {
kind,
maybe_changed,
state,
last_state,
} = self;
f.debug_struct("SimTrace")
.field("id", &id)
.field("kind", kind)
.field("maybe_changed", maybe_changed)
.field("state", state)
.field("last_state", last_state)
.finish()
@ -2083,12 +2078,10 @@ impl SimulationImpl {
traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map(
|&SimTrace {
kind,
maybe_changed: _,
state: _,
last_state: _,
}| SimTrace {
kind,
maybe_changed: true,
state: kind.make_state(),
last_state: kind.make_state(),
},
@ -2133,16 +2126,13 @@ impl SimulationImpl {
id,
&SimTrace {
kind,
maybe_changed,
ref state,
ref last_state,
},
) in self.traces.0.iter().enumerate()
{
if ONLY_IF_CHANGED {
if !(maybe_changed && state != last_state) {
continue;
}
if ONLY_IF_CHANGED && state == last_state {
continue;
}
let id = TraceScalarId(id);
match kind {
@ -2203,45 +2193,10 @@ impl SimulationImpl {
fn read_traces<const IS_INITIAL_STEP: bool>(&mut self) {
for &mut SimTrace {
kind,
ref mut maybe_changed,
ref mut state,
ref mut last_state,
} in &mut self.traces.0
{
let new_maybe_changed = match kind {
SimTraceKind::BigUInt { index, ty: _ }
| SimTraceKind::BigSInt { index, ty: _ }
| SimTraceKind::BigBool { index }
| SimTraceKind::BigAsyncReset { index }
| SimTraceKind::BigSyncReset { index }
| SimTraceKind::BigClock { index } => self
.state
.big_slots
.state_index_fetch_and_clear_maybe_modified_flag(index),
SimTraceKind::SmallUInt { index, ty: _ }
| SimTraceKind::SmallSInt { index, ty: _ }
| SimTraceKind::SmallBool { index }
| SimTraceKind::SmallAsyncReset { index }
| SimTraceKind::SmallSyncReset { index }
| SimTraceKind::SmallClock { index }
| SimTraceKind::EnumDiscriminant { index, ty: _ } => self
.state
.small_slots
.state_index_fetch_and_clear_maybe_modified_flag(index),
SimTraceKind::SimOnly { index, ty: _ } => self
.state
.sim_only_slots
.state_index_fetch_and_clear_maybe_modified_flag(index),
SimTraceKind::PhantomConst { ty: _ } => IS_INITIAL_STEP,
};
if !new_maybe_changed && !IS_INITIAL_STEP {
if *maybe_changed {
last_state.clone_from(state);
}
*maybe_changed = false;
continue;
}
*maybe_changed = new_maybe_changed;
if !IS_INITIAL_STEP {
mem::swap(state, last_state);
}

10
crates/fayalite/src/sim/compiler.rs
View file

@ -2234,7 +2234,6 @@ impl Compiler {
let id = TraceScalarId(self.traces.0.len());
self.traces.0.push(SimTrace {
kind,
maybe_changed: true,
state: (),
last_state: (),
});
@ -4088,15 +4087,6 @@ impl Compiler {
let init = self.compiled_expr_to_value(init, reg.source_location());
(reg.clock_domain().rst, init)
});
// next value defaults to current value
self.compile_simple_connect(
[].intern_slice(),
value.into(),
value,
reg.source_location(),
);
self.compile_reg(
clk,
reset_and_init,

53
crates/fayalite/src/sim/interpreter.rs
View file

@ -17,11 +17,12 @@ use bitvec::slice::BitSlice;
use num_bigint::BigInt;
use num_traits::{One, Signed, ToPrimitive, Zero};
use std::{
borrow::BorrowMut,
convert::Infallible,
fmt::{self, Write},
hash::Hash,
marker::PhantomData,
ops::{ControlFlow, Deref, Index, IndexMut},
ops::{ControlFlow, Deref, DerefMut, Index, IndexMut},
};
use vec_map::VecMap;
@ -914,12 +915,6 @@ impl<K: StatePartKind> StatePart<K> {
value: K::borrow_state(&mut self.value),
}
}
pub(crate) fn state_index_fetch_and_clear_maybe_modified_flag(
&mut self,
part_index: StatePartIndex<K>,
) -> bool {
K::state_index_fetch_and_clear_maybe_modified_flag(&mut self.value, part_index)
}
}
#[derive(Clone, PartialEq, Eq, Hash, Debug)]
@ -927,38 +922,56 @@ pub(crate) struct BorrowedStatePart<'a, K: StatePartKind> {
pub(crate) value: K::BorrowedState<'a>,
}
impl<K: StatePartKind> BorrowedStatePart<'_, K> {
impl<
'a,
K: StatePartKind<
BorrowedState<'a>: DerefMut<Target: IndexMut<usize, Output = T> + BorrowMut<[T]>>,
>,
T,
> BorrowedStatePart<'a, K>
{
pub(crate) fn get_disjoint_mut<const N: usize>(
&mut self,
indexes: [StatePartIndex<K>; N],
) -> [&mut K::StateElement; N] {
K::borrowed_state_get_disjoint_mut(&mut self.value, indexes)
) -> [&mut T; N] {
(*self.value)
.borrow_mut()
.get_disjoint_mut(indexes.map(|v| v.value as usize))
.expect("indexes are disjoint")
}
}
impl<K: StatePartKind> Index<StatePartIndex<K>> for StatePart<K> {
type Output = K::StateElement;
impl<K: StatePartKind<State: Deref<Target: Index<usize, Output = T>>>, T> Index<StatePartIndex<K>>
for StatePart<K>
{
type Output = T;
fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
K::state_index(&self.value, index)
&self.value[index.value as usize]
}
}
impl<K: StatePartKind> IndexMut<StatePartIndex<K>> for StatePart<K> {
impl<K: StatePartKind<State: DerefMut<Target: IndexMut<usize, Output = T>>>, T>
IndexMut<StatePartIndex<K>> for StatePart<K>
{
fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
K::state_index_mut(&mut self.value, index)
&mut self.value[index.value as usize]
}
}
impl<K: StatePartKind> Index<StatePartIndex<K>> for BorrowedStatePart<'_, K> {
type Output = K::StateElement;
impl<'a, K: StatePartKind<BorrowedState<'a>: Deref<Target: Index<usize, Output = T>>>, T>
Index<StatePartIndex<K>> for BorrowedStatePart<'a, K>
{
type Output = T;
fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
K::borrowed_state_index(&self.value, index)
&self.value[index.value as usize]
}
}
impl<K: StatePartKind> IndexMut<StatePartIndex<K>> for BorrowedStatePart<'_, K> {
impl<'a, K: StatePartKind<BorrowedState<'a>: DerefMut<Target: IndexMut<usize, Output = T>>>, T>
IndexMut<StatePartIndex<K>> for BorrowedStatePart<'a, K>
{
fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
K::borrowed_state_index_mut(&mut self.value, index)
&mut self.value[index.value as usize]
}
}

263
crates/fayalite/src/sim/interpreter/parts.rs
View file

@ -236,7 +236,6 @@ pub(crate) trait StatePartKind:
type LayoutData: Send + Sync + Eq + Hash + fmt::Debug + 'static + Copy;
type State: fmt::Debug + 'static + Clone;
type BorrowedState<'a>: 'a;
type StateElement;
fn new_state(layout_data: &[Self::LayoutData]) -> Self::State;
fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a>;
fn part_debug_data<BK: InsnsBuildingKind>(
@ -248,30 +247,6 @@ pub(crate) trait StatePartKind:
index: StatePartIndex<Self>,
f: &mut impl fmt::Write,
) -> fmt::Result;
fn state_index<'a>(
state: &'a Self::State,
part_index: StatePartIndex<Self>,
) -> &'a Self::StateElement;
fn state_index_mut<'a>(
state: &'a mut Self::State,
part_index: StatePartIndex<Self>,
) -> &'a mut Self::StateElement;
fn state_index_fetch_and_clear_maybe_modified_flag(
state: &mut Self::State,
part_index: StatePartIndex<Self>,
) -> bool;
fn borrowed_state_index<'a, 'b>(
state: &'a Self::BorrowedState<'b>,
part_index: StatePartIndex<Self>,
) -> &'a Self::StateElement;
fn borrowed_state_index_mut<'a, 'b>(
state: &'a mut Self::BorrowedState<'b>,
part_index: StatePartIndex<Self>,
) -> &'a mut Self::StateElement;
fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>(
state: &'a mut Self::BorrowedState<'b>,
part_indexes: [StatePartIndex<Self>; N],
) -> [&'a mut Self::StateElement; N];
}
macro_rules! make_state_part_kinds {
@ -297,7 +272,6 @@ impl StatePartKind for StatePartKindMemories {
type LayoutData = MemoryData<Interned<BitSlice>>;
type State = Box<[MemoryData<BitBox>]>;
type BorrowedState<'a> = &'a mut [MemoryData<BitBox>];
type StateElement = MemoryData<BitBox>;
fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
layout_data
.iter()
@ -323,88 +297,19 @@ impl StatePartKind for StatePartKindMemories {
) -> fmt::Result {
write!(f, "{:#?}", &state.memories[index])
}
fn state_index<'a>(
state: &'a Self::State,
part_index: StatePartIndex<Self>,
) -> &'a Self::StateElement {
&state[part_index.as_usize()]
}
fn state_index_mut<'a>(
state: &'a mut Self::State,
part_index: StatePartIndex<Self>,
) -> &'a mut Self::StateElement {
&mut state[part_index.as_usize()]
}
fn state_index_fetch_and_clear_maybe_modified_flag(
_state: &mut Self::State,
_part_index: StatePartIndex<Self>,
) -> bool {
true
}
fn borrowed_state_index<'a, 'b>(
state: &'a Self::BorrowedState<'b>,
part_index: StatePartIndex<Self>,
) -> &'a Self::StateElement {
&state[part_index.as_usize()]
}
fn borrowed_state_index_mut<'a, 'b>(
state: &'a mut Self::BorrowedState<'b>,
part_index: StatePartIndex<Self>,
) -> &'a mut Self::StateElement {
&mut state[part_index.as_usize()]
}
fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>(
state: &'a mut Self::BorrowedState<'b>,
part_indexes: [StatePartIndex<Self>; N],
) -> [&'a mut Self::StateElement; N] {
state
.get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize))
.expect("indexes are disjoint")
}
}
#[derive(Copy, Clone, PartialEq, Eq, Hash, Default)]
pub(crate) struct StateAndModified<T, M> {
pub(crate) state: T,
pub(crate) modified: M,
}
impl<T: Deref<Target = [E]>, M: Deref<Target = [bool]>, E: fmt::Debug> fmt::Debug
for StateAndModified<T, M>
{
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
f.debug_list()
.entries(self.state.iter().zip(self.modified.iter().copied()).map(
|(state, modified)| {
fmt::from_fn(move |f| {
state.fmt(f)?;
if modified {
f.write_str(" (modified)")?;
}
Ok(())
})
},
))
.finish()
}
}
impl StatePartKind for StatePartKindSmallSlots {
const NAME: &'static str = "SmallSlots";
type DebugData = SlotDebugData;
type LayoutData = ();
type State = StateAndModified<Box<[Self::StateElement]>, Box<[bool]>>;
type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>;
type StateElement = SmallUInt;
type State = Box<[SmallUInt]>;
type BorrowedState<'a> = &'a mut [SmallUInt];
fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
StateAndModified {
state: vec![0; layout_data.len()].into_boxed_slice(),
modified: vec![false; layout_data.len()].into_boxed_slice(),
}
vec![0; layout_data.len()].into_boxed_slice()
}
fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
let StateAndModified { state, modified } = state;
StateAndModified { state, modified }
state
}
fn part_debug_data<BK: InsnsBuildingKind>(
state_layout: &StateLayout<BK>,
@ -425,69 +330,19 @@ impl StatePartKind for StatePartKindSmallSlots {
write!(f, "{value:#x} {}", value as SmallSInt)?;
Ok(())
}
fn state_index<'a>(
state: &'a Self::State,
part_index: StatePartIndex<Self>,
) -> &'a Self::StateElement {
&state.state[part_index.as_usize()]
}
fn state_index_mut<'a>(
state: &'a mut Self::State,
part_index: StatePartIndex<Self>,
) -> &'a mut Self::StateElement {
state.modified[part_index.as_usize()] = true;
&mut state.state[part_index.as_usize()]
}
fn state_index_fetch_and_clear_maybe_modified_flag(
state: &mut Self::State,
part_index: StatePartIndex<Self>,
) -> bool {
std::mem::replace(&mut state.modified[part_index.as_usize()], false)
}
fn borrowed_state_index<'a, 'b>(
state: &'a Self::BorrowedState<'b>,
part_index: StatePartIndex<Self>,
) -> &'a Self::StateElement {
&state.state[part_index.as_usize()]
}
fn borrowed_state_index_mut<'a, 'b>(
state: &'a mut Self::BorrowedState<'b>,
part_index: StatePartIndex<Self>,
) -> &'a mut Self::StateElement {
state.modified[part_index.as_usize()] = true;
&mut state.state[part_index.as_usize()]
}
fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>(
state: &'a mut Self::BorrowedState<'b>,
part_indexes: [StatePartIndex<Self>; N],
) -> [&'a mut Self::StateElement; N] {
for part_index in part_indexes {
state.modified[part_index.as_usize()] = true;
}
state
.state
.get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize))
.expect("indexes are disjoint")
}
}
impl StatePartKind for StatePartKindBigSlots {
const NAME: &'static str = "BigSlots";
type DebugData = SlotDebugData;
type LayoutData = ();
type State = StateAndModified<Box<[Self::StateElement]>, Box<[bool]>>;
type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>;
type StateElement = BigInt;
type State = Box<[BigInt]>;
type BorrowedState<'a> = &'a mut [BigInt];
fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
let state: Box<[_]> = layout_data.iter().map(|_| BigInt::default()).collect();
StateAndModified {
modified: vec![false; state.len()].into_boxed_slice(),
state,
}
layout_data.iter().map(|_| BigInt::default()).collect()
}
fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
let StateAndModified { state, modified } = state;
StateAndModified { state, modified }
state
}
fn part_debug_data<BK: InsnsBuildingKind>(
state_layout: &StateLayout<BK>,
@ -506,69 +361,19 @@ impl StatePartKind for StatePartKindBigSlots {
) -> fmt::Result {
write!(f, "{:#x}", state.big_slots[index])
}
fn state_index<'a>(
state: &'a Self::State,
part_index: StatePartIndex<Self>,
) -> &'a Self::StateElement {
&state.state[part_index.as_usize()]
}
fn state_index_mut<'a>(
state: &'a mut Self::State,
part_index: StatePartIndex<Self>,
) -> &'a mut Self::StateElement {
state.modified[part_index.as_usize()] = true;
&mut state.state[part_index.as_usize()]
}
fn state_index_fetch_and_clear_maybe_modified_flag(
state: &mut Self::State,
part_index: StatePartIndex<Self>,
) -> bool {
std::mem::replace(&mut state.modified[part_index.as_usize()], false)
}
fn borrowed_state_index<'a, 'b>(
state: &'a Self::BorrowedState<'b>,
part_index: StatePartIndex<Self>,
) -> &'a Self::StateElement {
&state.state[part_index.as_usize()]
}
fn borrowed_state_index_mut<'a, 'b>(
state: &'a mut Self::BorrowedState<'b>,
part_index: StatePartIndex<Self>,
) -> &'a mut Self::StateElement {
state.modified[part_index.as_usize()] = true;
&mut state.state[part_index.as_usize()]
}
fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>(
state: &'a mut Self::BorrowedState<'b>,
part_indexes: [StatePartIndex<Self>; N],
) -> [&'a mut Self::StateElement; N] {
for part_index in part_indexes {
state.modified[part_index.as_usize()] = true;
}
state
.state
.get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize))
.expect("indexes are disjoint")
}
}
impl StatePartKind for StatePartKindSimOnlySlots {
const NAME: &'static str = "SimOnlySlots";
type DebugData = SlotDebugData;
type LayoutData = DynSimOnly;
type State = StateAndModified<Box<[Self::StateElement]>, Box<[bool]>>;
type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>;
type StateElement = DynSimOnlyValue;
type State = Box<[DynSimOnlyValue]>;
type BorrowedState<'a> = &'a mut [DynSimOnlyValue];
fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
let state: Box<[_]> = layout_data.iter().map(|ty| ty.default_value()).collect();
StateAndModified {
modified: vec![false; state.len()].into_boxed_slice(),
state,
}
layout_data.iter().map(|ty| ty.default_value()).collect()
}
fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
let StateAndModified { state, modified } = state;
StateAndModified { state, modified }
state
}
fn part_debug_data<BK: InsnsBuildingKind>(
state_layout: &StateLayout<BK>,
@ -587,50 +392,6 @@ impl StatePartKind for StatePartKindSimOnlySlots {
) -> fmt::Result {
write!(f, "{:?}", state.sim_only_slots[index])
}
fn state_index<'a>(
state: &'a Self::State,
part_index: StatePartIndex<Self>,
) -> &'a Self::StateElement {
&state.state[part_index.as_usize()]
}
fn state_index_mut<'a>(
state: &'a mut Self::State,
part_index: StatePartIndex<Self>,
) -> &'a mut Self::StateElement {
state.modified[part_index.as_usize()] = true;
&mut state.state[part_index.as_usize()]
}
fn state_index_fetch_and_clear_maybe_modified_flag(
state: &mut Self::State,
part_index: StatePartIndex<Self>,
) -> bool {
std::mem::replace(&mut state.modified[part_index.as_usize()], false)
}
fn borrowed_state_index<'a, 'b>(
state: &'a Self::BorrowedState<'b>,
part_index: StatePartIndex<Self>,
) -> &'a Self::StateElement {
&state.state[part_index.as_usize()]
}
fn borrowed_state_index_mut<'a, 'b>(
state: &'a mut Self::BorrowedState<'b>,
part_index: StatePartIndex<Self>,
) -> &'a mut Self::StateElement {
state.modified[part_index.as_usize()] = true;
&mut state.state[part_index.as_usize()]
}
fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>(
state: &'a mut Self::BorrowedState<'b>,
part_indexes: [StatePartIndex<Self>; N],
) -> [&'a mut Self::StateElement; N] {
for part_index in part_indexes {
state.modified[part_index.as_usize()] = true;
}
state
.state
.get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize))
.expect("indexes are disjoint")
}
}
#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]

221
crates/fayalite/src/sim/value.rs
View file

@ -15,8 +15,7 @@ use crate::{
source_location::SourceLocation,
ty::{
CanonicalType, OpaqueSimValue, OpaqueSimValueSize, OpaqueSimValueSlice,
OpaqueSimValueWriter, SimValueDebug, StaticType, Type, TypeProperties,
impl_match_variant_as_self,
OpaqueSimValueWriter, StaticType, Type, TypeProperties, impl_match_variant_as_self,
},
util::{
ConstUsize, HashMap,
@ -552,119 +551,113 @@ impl_sim_value_cmp_as_bool!(AsyncReset);
#[doc(hidden)]
pub mod match_sim_value {
use crate::{sim::value::SimValue, ty::Type};
use std::ops::{Deref, DerefMut};
macro_rules! wrapper {
(
$(pub struct $wrapper:ident<$T:ident>($inner:ty);)*
) => {
$(#[doc(hidden)]
pub struct $wrapper<$T>($inner);
impl<$T> $wrapper<$T> {
#[inline(always)]
pub fn new(value: $T) -> Self {
Self(<$inner>::new(value))
}
}
impl<$T> Deref for $wrapper<$T> {
type Target = $inner;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl<$T> DerefMut for $wrapper<$T> {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
})*
};
}
wrapper! {
pub struct MatchSimValueHelperCheckSimValue<T>(MatchSimValueHelperCheckMutSimValue<T>);
pub struct MatchSimValueHelperCheckMutSimValue<T>(MatchSimValueHelperCheckRefSimValue<T>);
pub struct MatchSimValueHelperCheckRefSimValue<T>(MatchSimValueHelperCheckRefRefSimValue<T>);
pub struct MatchSimValueHelperCheckRefRefSimValue<T>(MatchSimValueHelperCheckRefMutSimValue<T>);
pub struct MatchSimValueHelperCheckRefMutSimValue<T>(MatchSimValueHelperCheckMutRefSimValue<T>);
pub struct MatchSimValueHelperCheckMutRefSimValue<T>(MatchSimValueHelperCheckMutMutSimValue<T>);
pub struct MatchSimValueHelperCheckMutMutSimValue<T>(MatchSimValueHelperIdentity<T>);
}
impl<T: Type> MatchSimValueHelperCheckSimValue<SimValue<T>> {
#[inline(always)]
pub fn __fayalite_match_sim_value(&mut self) -> T::SimValue {
SimValue::into_value(self.take())
}
}
impl<'a, T: Type> MatchSimValueHelperCheckMutSimValue<&'a mut SimValue<T>> {
#[inline(always)]
pub fn __fayalite_match_sim_value(&mut self) -> &'a mut T::SimValue {
self.take()
}
}
impl<'a, T: Type> MatchSimValueHelperCheckRefSimValue<&'a SimValue<T>> {
#[inline(always)]
pub fn __fayalite_match_sim_value(&mut self) -> &'a T::SimValue {
self.take()
}
}
impl<'a, 'b, T: Type> MatchSimValueHelperCheckRefRefSimValue<&'a &'b SimValue<T>> {
#[inline(always)]
pub fn __fayalite_match_sim_value(&mut self) -> &'b T::SimValue {
self.take()
}
}
impl<'a, 'b, T: Type> MatchSimValueHelperCheckRefMutSimValue<&'a &'b mut SimValue<T>> {
#[inline(always)]
pub fn __fayalite_match_sim_value(&mut self) -> &'a T::SimValue {
self.take()
}
}
impl<'a, 'b, T: Type> MatchSimValueHelperCheckMutRefSimValue<&'a mut &'b SimValue<T>> {
#[inline(always)]
pub fn __fayalite_match_sim_value(&mut self) -> &'b T::SimValue {
self.take()
}
}
impl<'a, 'b, T: Type> MatchSimValueHelperCheckMutMutSimValue<&'a mut &'b mut SimValue<T>> {
#[inline(always)]
pub fn __fayalite_match_sim_value(&mut self) -> &'a mut T::SimValue {
self.take()
}
}
use crate::{
sim::value::{SimValue, ToSimValue},
ty::Type,
};
#[doc(hidden)]
pub struct MatchSimValueHelperIdentity<T>(Option<T>);
pub struct MatchSimValueHelper<T>(Option<T>);
impl<T> MatchSimValueHelperIdentity<T> {
fn new(v: T) -> Self {
impl<T> MatchSimValueHelper<T> {
pub fn new(v: T) -> Self {
Self(Some(v))
}
#[inline(always)]
fn take(&mut self) -> T {
self.0.take().expect("known to be Some")
}
#[doc(hidden)]
pub trait MatchSimValue {
type MatchValue;
/// use `self` so it comes first in the method resolution order
fn __fayalite_match_sim_value(self) -> Self::MatchValue
where
Self: Sized;
}
impl<T: Type> MatchSimValue for MatchSimValueHelper<SimValue<T>> {
type MatchValue = T::SimValue;
fn __fayalite_match_sim_value(self) -> Self::MatchValue {
SimValue::into_value(self.0.expect("should be Some"))
}
#[inline(always)]
pub fn __fayalite_match_sim_value(&mut self) -> T {
self.take()
}
impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a SimValue<T>> {
type MatchValue = &'a T::SimValue;
fn __fayalite_match_sim_value(self) -> Self::MatchValue {
SimValue::value(self.0.expect("should be Some"))
}
}
impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a mut SimValue<T>> {
type MatchValue = &'a mut T::SimValue;
fn __fayalite_match_sim_value(self) -> Self::MatchValue {
SimValue::value_mut(self.0.expect("should be Some"))
}
}
impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ &'a T>
where
MatchSimValueHelper<&'a T>: MatchSimValue,
{
type MatchValue = <MatchSimValueHelper<&'a T> as MatchSimValue>::MatchValue;
fn __fayalite_match_sim_value(self) -> Self::MatchValue {
MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v)))
}
}
impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ mut &'a T>
where
MatchSimValueHelper<&'a T>: MatchSimValue,
{
type MatchValue = <MatchSimValueHelper<&'a T> as MatchSimValue>::MatchValue;
fn __fayalite_match_sim_value(self) -> Self::MatchValue {
MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v)))
}
}
impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a &'_ mut T>
where
MatchSimValueHelper<&'a T>: MatchSimValue,
{
type MatchValue = <MatchSimValueHelper<&'a T> as MatchSimValue>::MatchValue;
fn __fayalite_match_sim_value(self) -> Self::MatchValue {
MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &**v)))
}
}
impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a mut &'_ mut T>
where
MatchSimValueHelper<&'a mut T>: MatchSimValue,
{
type MatchValue = <MatchSimValueHelper<&'a mut T> as MatchSimValue>::MatchValue;
fn __fayalite_match_sim_value(self) -> Self::MatchValue {
MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &mut **v)))
}
}
#[doc(hidden)]
pub type MatchSimValueHelper<T> = MatchSimValueHelperCheckSimValue<T>;
pub trait MatchSimValueFallback {
type MatchValue;
/// use `&mut self` so it comes later in the method resolution order than MatchSimValue
fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue;
}
impl<T: ToSimValue> MatchSimValueFallback for MatchSimValueHelper<T> {
type MatchValue = <T::Type as Type>::SimValue;
fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue {
SimValue::into_value(self.0.take().expect("should be Some").into_sim_value())
}
}
}
pub trait ToSimValue: ToSimValueWithType<<Self as ValueType>::Type> + ValueType {
@ -1401,15 +1394,6 @@ impl Type for DynSimOnly {
}
}
impl SimValueDebug for DynSimOnly {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl<T: SimOnlyValueTrait> Type for SimOnly<T> {
type BaseType = DynSimOnly;
type MaskType = Bool;
@ -1475,15 +1459,6 @@ impl<T: SimOnlyValueTrait> Type for SimOnly<T> {
}
}
impl<T: SimOnlyValueTrait> SimValueDebug for SimOnly<T> {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
impl<T: SimOnlyValueTrait> StaticType for SimOnly<T> {
const TYPE: Self = Self::new();

159
crates/fayalite/src/sim/vcd.rs
View file

@ -26,7 +26,6 @@ use std::{
collections::BTreeMap,
fmt::{self, Write as _},
io, mem,
num::NonZeroU64,
};
#[derive(Default, Clone)]
@ -187,26 +186,6 @@ impl<W: io::Write> fmt::Debug for VcdWriterDecls<W> {
}
}
/// pass in scope to ensure it's not available in child scope
fn try_write_vcd_scope<W: io::Write, R>(
writer: &mut W,
scope_type: &str,
scope_name: Interned<str>,
scope: Option<&mut Scope>,
f: impl FnOnce(&mut W, Option<&mut Scope>) -> io::Result<R>,
) -> io::Result<R> {
let Some(scope) = scope else {
return f(writer, None);
};
write_vcd_scope(
writer,
scope_type,
scope_name,
scope,
move |writer, scope| f(writer, Some(scope)),
)
}
/// pass in scope to ensure it's not available in child scope
fn write_vcd_scope<W: io::Write, R>(
writer: &mut W,
@ -258,7 +237,6 @@ trait_arg! {
struct ArgModule<'a> {
properties: &'a mut VcdWriterProperties,
scope: &'a mut Scope,
instance_name: Option<Interned<str>>,
}
impl<'a> ArgModule<'a> {
@ -266,7 +244,6 @@ impl<'a> ArgModule<'a> {
ArgModule {
properties: self.properties,
scope: self.scope,
instance_name: self.instance_name,
}
}
}
@ -290,7 +267,7 @@ struct ArgInType<'a> {
sink_var_type: &'static str,
duplex_var_type: &'static str,
properties: &'a mut VcdWriterProperties,
scope: Option<&'a mut Scope>,
scope: &'a mut Scope,
}
impl<'a> ArgInType<'a> {
@ -300,7 +277,7 @@ impl<'a> ArgInType<'a> {
sink_var_type: self.sink_var_type,
duplex_var_type: self.duplex_var_type,
properties: self.properties,
scope: self.scope.as_deref_mut(),
scope: self.scope,
}
}
}
@ -337,7 +314,7 @@ impl WriteTrace for TraceScalar {
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
#[repr(transparent)]
struct VcdId(NonZeroU64);
struct VcdId(u64);
impl VcdId {
const CHAR_RANGE: std::ops::RangeInclusive<u8> = b'!'..=b'~';
@ -367,14 +344,11 @@ impl VcdId {
};
retval = v;
}
let Some(retval) = NonZeroU64::new(retval) else {
return None;
};
Some(Self(retval))
}
#[must_use]
const fn write(self, out: &mut [u8]) -> usize {
let mut id = self.0.get();
let mut id = self.0;
let mut len = 0;
loop {
let digit = (id % Self::BASE as u64) as u8 + *Self::CHAR_RANGE.start();
@ -389,7 +363,7 @@ impl VcdId {
}
len
}
const MAX_ID_LEN: usize = Self(NonZeroU64::MAX).write(&mut []);
const MAX_ID_LEN: usize = Self(u64::MAX).write(&mut []);
}
/// check that VcdId properly round-trips
@ -449,7 +423,7 @@ impl<T: fmt::Display> fmt::Display for Escaped<T> {
fn write_vcd_var<W: io::Write>(
properties: &mut VcdWriterProperties,
scope: Option<&mut Scope>,
scope: &mut Scope,
memory_element_part_body: MemoryElementPartBody,
writer: &mut W,
var_type: &str,
@ -457,6 +431,8 @@ fn write_vcd_var<W: io::Write>(
location: TraceLocation,
name: Interned<str>,
) -> io::Result<()> {
let path_hash = scope.path_hash.clone().joined(name);
let name = scope.new_identifier(name);
let id = match location {
TraceLocation::Scalar(id) => id.as_usize(),
TraceLocation::Memory(TraceMemoryLocation {
@ -488,21 +464,12 @@ fn write_vcd_var<W: io::Write>(
first_id + *element_index
}
};
if let Some(scope) = scope {
let path_hash = scope.path_hash.clone().joined(name);
let name = scope.new_identifier(name);
let id = properties
.scalar_id_to_vcd_id_map
.builder_get_or_insert(id, &path_hash);
write!(writer, "$var {var_type} {size} ")?;
write_vcd_id(writer, id)?;
writeln!(writer, " {name} $end")
} else {
properties
.scalar_id_to_vcd_id_map
.builder_unused_scalar_id(id);
Ok(())
}
let id = properties
.scalar_id_to_vcd_id_map
.builder_get_or_insert(id, &path_hash);
write!(writer, "$var {var_type} {size} ")?;
write_vcd_id(writer, id)?;
writeln!(writer, " {name} $end")
}
impl WriteTrace for TraceUInt {
@ -745,24 +712,14 @@ impl WriteTrace for TraceScope {
impl WriteTrace for TraceModule {
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
let ArgModule {
properties,
scope,
instance_name,
} = arg.module();
let ArgModule { properties, scope } = arg.module();
let Self { name, children } = self;
write_vcd_scope(
writer,
"module",
instance_name.unwrap_or(name),
scope,
|writer, scope| {
for child in children {
child.write_trace(writer, ArgModuleBody { properties, scope })?;
}
Ok(())
},
)
write_vcd_scope(writer, "module", name, scope, |writer, scope| {
for child in children {
child.write_trace(writer, ArgModuleBody { properties, scope })?;
}
Ok(())
})
}
}
@ -770,7 +727,7 @@ impl WriteTrace for TraceInstance {
fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
let ArgModuleBody { properties, scope } = arg.module_body();
let Self {
name,
name: _,
instance_io,
module,
ty: _,
@ -782,17 +739,10 @@ impl WriteTrace for TraceInstance {
sink_var_type: "wire",
duplex_var_type: "wire",
properties,
scope: None,
scope,
},
)?;
module.write_trace(
writer,
ArgModule {
properties,
scope,
instance_name: Some(name),
},
)
module.write_trace(writer, ArgModule { properties, scope })
}
}
@ -831,7 +781,7 @@ impl WriteTrace for TraceMem {
sink_var_type: "reg",
duplex_var_type: "reg",
properties,
scope: Some(scope),
scope,
},
)
},
@ -863,7 +813,7 @@ impl WriteTrace for TraceMemPort {
sink_var_type: "wire",
duplex_var_type: "wire",
properties,
scope: Some(scope),
scope,
},
)
}
@ -884,7 +834,7 @@ impl WriteTrace for TraceWire {
sink_var_type: "wire",
duplex_var_type: "wire",
properties,
scope: Some(scope),
scope,
},
)
}
@ -905,7 +855,7 @@ impl WriteTrace for TraceReg {
sink_var_type: "reg",
duplex_var_type: "reg",
properties,
scope: Some(scope),
scope,
},
)
}
@ -927,7 +877,7 @@ impl WriteTrace for TraceModuleIO {
sink_var_type: "wire",
duplex_var_type: "wire",
properties,
scope: Some(scope),
scope,
},
)
}
@ -948,7 +898,7 @@ impl WriteTrace for TraceBundle {
ty: _,
flow: _,
} = self;
try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| {
write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
for field in fields {
field.write_trace(
writer,
@ -957,7 +907,7 @@ impl WriteTrace for TraceBundle {
sink_var_type,
duplex_var_type,
properties,
scope: scope.as_deref_mut(),
scope,
},
)?;
}
@ -981,7 +931,7 @@ impl WriteTrace for TraceArray {
ty: _,
flow: _,
} = self;
try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| {
write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
for element in elements {
element.write_trace(
writer,
@ -990,7 +940,7 @@ impl WriteTrace for TraceArray {
sink_var_type,
duplex_var_type,
properties,
scope: scope.as_deref_mut(),
scope,
},
)?;
}
@ -1015,7 +965,7 @@ impl WriteTrace for TraceEnumWithFields {
ty: _,
flow: _,
} = self;
try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| {
write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
discriminant.write_trace(
writer,
ArgInType {
@ -1023,7 +973,7 @@ impl WriteTrace for TraceEnumWithFields {
sink_var_type,
duplex_var_type,
properties,
scope: scope.as_deref_mut(),
scope,
},
)?;
for field in non_empty_fields {
@ -1034,7 +984,7 @@ impl WriteTrace for TraceEnumWithFields {
sink_var_type,
duplex_var_type,
properties,
scope: scope.as_deref_mut(),
scope,
},
)?;
}
@ -1076,7 +1026,6 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
ArgModule {
properties: &mut properties,
scope: &mut Scope::new(PathHash::default()),
instance_name: None,
},
)?;
let ScalarIdToVcdIdMapOrBuilder::Builder(scalar_id_to_vcd_id_map_builder) =
@ -1116,29 +1065,23 @@ struct MemoryProperties {
}
struct ScalarIdToVcdIdMap {
scalar_id_to_vcd_id_map: Box<[Option<VcdId>]>,
scalar_id_to_vcd_id_map: Box<[VcdId]>,
}
#[derive(Default)]
struct ScalarIdToVcdIdMapBuilder {
scalar_id_to_vcd_id_map: BTreeMap<usize, Option<VcdId>>,
scalar_id_to_vcd_id_map: BTreeMap<usize, VcdId>,
lower_half_to_next_upper_half_map: HashMap<u64, u64>,
}
impl ScalarIdToVcdIdMapBuilder {
fn unused_scalar_id(&mut self, scalar_id: usize) {
self.scalar_id_to_vcd_id_map
.entry(scalar_id)
.or_insert(None);
}
/// `VcdId`s are based off of `path_hash` (and not `scalar_id`) since the hash doesn't change
/// when unrelated variables are added/removed, making the generated VCD more friendly for git diff.
fn get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId {
*self
.scalar_id_to_vcd_id_map
.entry(scalar_id)
.or_insert(None)
.get_or_insert_with(|| {
.or_insert_with(|| {
let hash = u128::from_le_bytes(
*path_hash
.0
@ -1151,7 +1094,7 @@ impl ScalarIdToVcdIdMapBuilder {
let next_upper_half = self
.lower_half_to_next_upper_half_map
.entry(lower_half)
.or_insert(if lower_half == 0 { 1 } else { 0 });
.or_insert(0);
let upper_half = *next_upper_half;
*next_upper_half += 1;
let Some(id) = upper_half
@ -1160,7 +1103,7 @@ impl ScalarIdToVcdIdMapBuilder {
else {
panic!("too many VcdIds");
};
VcdId(NonZeroU64::new(id).expect("known to not be zero"))
VcdId(id)
})
}
fn build(self) -> ScalarIdToVcdIdMap {
@ -1186,7 +1129,7 @@ enum ScalarIdToVcdIdMapOrBuilder {
}
impl ScalarIdToVcdIdMapOrBuilder {
fn built_scalar_id_to_vcd_id(&self, scalar_id: usize) -> Option<VcdId> {
fn built_scalar_id_to_vcd_id(&self, scalar_id: usize) -> VcdId {
let Self::Built(v) = self else {
panic!("ScalarIdToVcdIdMap isn't built yet");
};
@ -1198,12 +1141,6 @@ impl ScalarIdToVcdIdMapOrBuilder {
};
v.get_or_insert(scalar_id, path_hash)
}
fn builder_unused_scalar_id(&mut self, scalar_id: usize) {
let Self::Builder(v) = self else {
panic!("ScalarIdToVcdIdMap is already built");
};
v.unused_scalar_id(scalar_id)
}
}
struct VcdWriterProperties {
@ -1228,11 +1165,8 @@ impl<W: io::Write + 'static> VcdWriter<W> {
fn write_string_value_change(
writer: &mut impl io::Write,
value: impl fmt::Display,
id: Option<VcdId>,
id: VcdId,
) -> io::Result<()> {
let Some(id) = id else {
return Ok(());
};
write!(writer, "s{} ", Escaped(value))?;
write_vcd_id(writer, id)?;
writer.write_all(b"\n")
@ -1241,11 +1175,8 @@ fn write_string_value_change(
fn write_bits_value_change(
writer: &mut impl io::Write,
value: &BitSlice,
id: Option<VcdId>,
id: VcdId,
) -> io::Result<()> {
let Some(id) = id else {
return Ok(());
};
match value.len() {
0 => writer.write_all(b"s0 ")?,
1 => writer.write_all(if value[0] { b"1" } else { b"0" })?,
@ -1274,7 +1205,7 @@ fn write_enum_discriminant_value_change(
writer: &mut impl io::Write,
variant_index: usize,
ty: Enum,
id: Option<VcdId>,
id: VcdId,
) -> io::Result<()> {
write_string_value_change(
writer,

29
crates/fayalite/src/ty.rs
View file

@ -367,15 +367,7 @@ impl<D: Type> TypeOrDefault<D> for crate::__ {
}
pub trait Type:
Copy
+ Hash
+ Eq
+ fmt::Debug
+ Send
+ Sync
+ 'static
+ FillInDefaultedGenerics<Type = Self>
+ SimValueDebug
Copy + Hash + Eq + fmt::Debug + Send + Sync + 'static + FillInDefaultedGenerics<Type = Self>
{
type BaseType: BaseType;
type MaskType: Type<MaskType = Self::MaskType>;
@ -410,16 +402,6 @@ pub trait Type:
) -> OpaqueSimValueWritten<'w>;
}
pub trait SimValueDebug {
fn sim_value_debug(value: &<Self as Type>::SimValue, f: &mut fmt::Formatter<'_>) -> fmt::Result
where
Self: Type;
}
pub trait SimValueDisplay: Type {
fn sim_value_display(value: &Self::SimValue, f: &mut fmt::Formatter<'_>) -> fmt::Result;
}
pub trait BaseType:
Type<
BaseType = Self,
@ -508,15 +490,6 @@ impl Type for CanonicalType {
}
}
impl SimValueDebug for CanonicalType {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(value, f)
}
}
#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize, Default)]
#[non_exhaustive]
pub struct OpaqueSimValueSizeRange {

166
crates/fayalite/tests/hdl_types_fmt.rs
View file

@ -1,166 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
use fayalite::{prelude::*, ty::SimValueDebug};
use std::fmt;
#[hdl(outline_generated)]
struct MyStruct0<T, S: Size> {
v: T,
a: ArrayType<UInt<8>, S>,
}
#[hdl]
#[test]
fn check_my_struct0() {
let ty = MyStruct0[UInt[8]][3];
assert_eq!(
format!("{ty:?}"),
"MyStruct0 { v: UInt<8>, a: Array<UInt<8>, 3> }",
);
assert_eq!(
format!("{:?}", ty.mask_type()),
"MaskType<MyStruct0> { v: Bool, a: Array<Bool, 3> }",
);
let v = #[hdl(sim)]
MyStruct0::<_, _> {
v: 0x23u8,
a: [1u8, 2, 3],
};
assert_eq!(
format!("{v:?}"),
"MyStruct0 { v: 0x23_u8, a: [0x1_u8, 0x2_u8, 0x3_u8] }",
);
}
#[hdl(outline_generated, custom_debug())]
struct MyStruct1<T, S: Size> {
v: T,
a: ArrayType<UInt<8>, S>,
}
impl<T: Type, S: Size> fmt::Debug for MyStruct1<T, S> {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
let Self { v, a } = self;
f.debug_struct("Custom<MyStruct1>")
.field("v", v)
.field("a", a)
.finish()
}
}
impl<T: Type, S: Size> SimValueDebug for MyStruct1<T, S> {
#[hdl]
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
#[hdl(sim)]
let Self { v, a } = value;
f.debug_struct("Custom<MyStruct1>")
.field("v", &v)
.field("a", &a)
.finish()
}
}
#[hdl]
#[test]
fn check_my_struct1() {
let ty = MyStruct1[UInt[8]][3];
assert_eq!(
format!("{ty:?}"),
"Custom<MyStruct1> { v: UInt<8>, a: Array<UInt<8>, 3> }",
);
assert_eq!(
format!("{:?}", ty.mask_type()),
"MaskType<MyStruct1> { v: Bool, a: Array<Bool, 3> }",
);
let v = #[hdl(sim)]
MyStruct1::<_, _> {
v: 0x23u8,
a: [1u8, 2, 3],
};
assert_eq!(
format!("{v:?}"),
"Custom<MyStruct1> { v: 0x23_u8, a: [0x1_u8, 0x2_u8, 0x3_u8] }",
);
}
#[hdl(outline_generated)]
enum MyEnum0<T, S: Size> {
Unit,
V(T),
A(ArrayType<UInt<8>, S>),
}
#[hdl]
#[test]
fn check_my_enum0() {
let ty = MyEnum0[UInt[8]][3];
assert_eq!(
format!("{ty:?}"),
"MyEnum0 { Unit: (), V: UInt<8>, A: Array<UInt<8>, 3> }",
);
let v = #[hdl(sim)]
ty.Unit();
assert_eq!(format!("{v:?}"), "Unit");
let v = #[hdl(sim)]
ty.V(0x23u8);
assert_eq!(format!("{v:?}"), "V(0x23_u8)");
let v = #[hdl(sim)]
ty.A([1u8, 2, 3]);
assert_eq!(format!("{v:?}"), "A([0x1_u8, 0x2_u8, 0x3_u8])");
}
#[hdl(outline_generated, custom_debug())]
enum MyEnum1<T, S: Size> {
Unit,
V(T),
A(ArrayType<UInt<8>, S>),
}
impl<T: Type, S: Size> fmt::Debug for MyEnum1<T, S> {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
let Self { Unit, V, A } = self;
f.debug_struct("Custom<MyEnum1>")
.field("Unit", Unit)
.field("V", V)
.field("A", A)
.finish()
}
}
impl<T: Type, S: Size> SimValueDebug for MyEnum1<T, S> {
#[hdl]
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
type SimValueT<T> = <T as Type>::SimValue;
match value {
SimValueT::<Self>::Unit(_) => f.write_str("MyEnum1::Unit"),
SimValueT::<Self>::V(v, _) => f.debug_tuple("MyEnum1::V").field(v).finish(),
SimValueT::<Self>::A(a, _) => f.debug_tuple("MyEnum1::A").field(a).finish(),
SimValueT::<Self>::Unknown(_) => f.write_str("MyEnum1::Unknown"),
}
}
}
#[hdl]
#[test]
fn check_my_enum1() {
let ty = MyEnum1[UInt[8]][3];
assert_eq!(
format!("{ty:?}"),
"Custom<MyEnum1> { Unit: (), V: UInt<8>, A: Array<UInt<8>, 3> }",
);
let v = #[hdl(sim)]
ty.Unit();
assert_eq!(format!("{v:?}"), "MyEnum1::Unit");
let v = #[hdl(sim)]
ty.V(0x23u8);
assert_eq!(format!("{v:?}"), "MyEnum1::V(0x23_u8)");
let v = #[hdl(sim)]
ty.A([1u8, 2, 3]);
assert_eq!(format!("{v:?}"), "MyEnum1::A([0x1_u8, 0x2_u8, 0x3_u8])");
}

362
crates/fayalite/tests/module.rs
View file

@ -13,7 +13,7 @@ use fayalite::{
};
use serde_json::json;
#[hdl(outline_generated, cmp_eq)]
#[hdl(outline_generated)]
pub enum TestEnum {
A,
B(UInt<8>),
@ -679,366 +679,6 @@ circuit check_enum_literals:
};
}
#[hdl_module(outline_generated)]
pub fn check_enum_cmp_eq() {
#[hdl]
let lhs: TestEnum = m.input();
#[hdl]
let rhs: TestEnum = m.input();
#[hdl]
let eq: Bool = m.output();
connect(eq, lhs.cmp_eq(rhs));
}
#[test]
fn test_enum_cmp_eq() {
let _n = SourceLocation::normalize_files_for_tests();
let m = check_enum_cmp_eq();
dbg!(m);
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
assert_export_firrtl! {
m =>
options: ExportOptions {
simplify_enums: None,
..ExportOptions::default()
},
"/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0
circuit check_enum_cmp_eq:
type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|}
module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1]
input lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1]
input rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1]
output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1]
match lhs: @[module-XXXXXXXXXX.rs 5:1]
A:
match rhs: @[module-XXXXXXXXXX.rs 5:1]
A:
connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1]
B(_match_arm_value):
skip
C(_match_arm_value_1):
skip
B(_match_arm_value_2):
match rhs: @[module-XXXXXXXXXX.rs 5:1]
A:
skip
B(_match_arm_value_3):
connect TestEnum_cmp_eq, eq(_match_arm_value_2, _match_arm_value_3) @[module-XXXXXXXXXX.rs 5:1]
C(_match_arm_value_4):
skip
C(_match_arm_value_5):
match rhs: @[module-XXXXXXXXXX.rs 5:1]
A:
skip
B(_match_arm_value_6):
skip
C(_match_arm_value_7):
wire _array_literal_expr: UInt<1>[3]
connect _array_literal_expr[0], eq(_match_arm_value_5[0], _match_arm_value_7[0])
connect _array_literal_expr[1], eq(_match_arm_value_5[1], _match_arm_value_7[1])
connect _array_literal_expr[2], eq(_match_arm_value_5[2], _match_arm_value_7[2])
wire _cast_array_to_bits_expr: UInt<1>[3]
connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
wire _cast_to_bits_expr: UInt<3>
connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1]
connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1]
",
};
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
assert_export_firrtl! {
m =>
options: ExportOptions {
simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody),
..ExportOptions::default()
},
"/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0
circuit check_enum_cmp_eq:
type Ty0 = {|A, B, C|}
type Ty1 = {tag: Ty0, body: UInt<8>}
module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1]
input lhs: Ty1 @[module-XXXXXXXXXX.rs 2:1]
input rhs: Ty1 @[module-XXXXXXXXXX.rs 3:1]
output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1]
match lhs.tag: @[module-XXXXXXXXXX.rs 5:1]
A:
match rhs.tag: @[module-XXXXXXXXXX.rs 5:1]
A:
connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1]
B:
skip
C:
skip
B:
match rhs.tag: @[module-XXXXXXXXXX.rs 5:1]
A:
skip
B:
connect TestEnum_cmp_eq, eq(bits(lhs.body, 7, 0), bits(rhs.body, 7, 0)) @[module-XXXXXXXXXX.rs 5:1]
C:
skip
C:
match rhs.tag: @[module-XXXXXXXXXX.rs 5:1]
A:
skip
B:
skip
C:
wire _array_literal_expr: UInt<1>[3]
wire _cast_bits_to_array_expr: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened[0], bits(bits(lhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0]
connect _cast_bits_to_array_expr_flattened[1], bits(bits(lhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
connect _cast_bits_to_array_expr_flattened[2], bits(bits(lhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
wire _cast_bits_to_array_expr_1: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(rhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0]
connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(rhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
wire _cast_bits_to_array_expr_2: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(lhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0]
connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(lhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1]
connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(lhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2]
wire _cast_bits_to_array_expr_3: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(rhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0]
connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(rhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1]
connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(rhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2]
connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1])
wire _cast_bits_to_array_expr_4: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(lhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0]
connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(lhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1]
connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(lhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2]
wire _cast_bits_to_array_expr_5: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(rhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0]
connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(rhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1]
connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(rhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2]
connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2])
wire _cast_array_to_bits_expr: UInt<1>[3]
connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
wire _cast_to_bits_expr: UInt<3>
connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1]
connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1]
",
};
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
assert_export_firrtl! {
m =>
options: ExportOptions {
simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
..ExportOptions::default()
},
"/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0
circuit check_enum_cmp_eq:
type Ty0 = {tag: UInt<2>, body: UInt<8>}
module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1]
input lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1]
input rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1]
output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1]
when eq(lhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1]
else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
skip
else when eq(lhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
skip
else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
connect TestEnum_cmp_eq, eq(bits(lhs.body, 7, 0), bits(rhs.body, 7, 0)) @[module-XXXXXXXXXX.rs 5:1]
else when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
skip
else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
skip
else:
wire _array_literal_expr: UInt<1>[3]
wire _cast_bits_to_array_expr: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened[0], bits(bits(lhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0]
connect _cast_bits_to_array_expr_flattened[1], bits(bits(lhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
connect _cast_bits_to_array_expr_flattened[2], bits(bits(lhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
wire _cast_bits_to_array_expr_1: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(rhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0]
connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(rhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
wire _cast_bits_to_array_expr_2: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(lhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0]
connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(lhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1]
connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(lhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2]
wire _cast_bits_to_array_expr_3: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(rhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0]
connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(rhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1]
connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(rhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2]
connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1])
wire _cast_bits_to_array_expr_4: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(lhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0]
connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(lhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1]
connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(lhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2]
wire _cast_bits_to_array_expr_5: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(rhs.body, 2, 0), 0, 0)
connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0]
connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(rhs.body, 2, 0), 1, 1)
connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1]
connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(rhs.body, 2, 0), 2, 2)
connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2]
connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2])
wire _cast_array_to_bits_expr: UInt<1>[3]
connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
wire _cast_to_bits_expr: UInt<3>
connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1]
connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1]
",
};
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
assert_export_firrtl! {
m =>
options: ExportOptions {
simplify_enums: Some(SimplifyEnumsKind::ReplaceWithUInt),
..ExportOptions::default()
},
"/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0
circuit check_enum_cmp_eq:
module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1]
input lhs: UInt<10> @[module-XXXXXXXXXX.rs 2:1]
input rhs: UInt<10> @[module-XXXXXXXXXX.rs 3:1]
output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1]
when eq(bits(lhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1]
else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
skip
else when eq(bits(lhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
skip
else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
connect TestEnum_cmp_eq, eq(bits(bits(lhs, 9, 2), 7, 0), bits(bits(rhs, 9, 2), 7, 0)) @[module-XXXXXXXXXX.rs 5:1]
else when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1]
skip
else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1]
skip
else:
wire _array_literal_expr: UInt<1>[3]
wire _cast_bits_to_array_expr: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0)
connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0]
connect _cast_bits_to_array_expr_flattened[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1)
connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
connect _cast_bits_to_array_expr_flattened[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2)
connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
wire _cast_bits_to_array_expr_1: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0)
connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0]
connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1)
connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2)
connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0])
wire _cast_bits_to_array_expr_2: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0)
connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0]
connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1)
connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1]
connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2)
connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2]
wire _cast_bits_to_array_expr_3: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0)
connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0]
connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1)
connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1]
connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2)
connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2]
connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1])
wire _cast_bits_to_array_expr_4: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0)
connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0]
connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1)
connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1]
connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2)
connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2]
wire _cast_bits_to_array_expr_5: UInt<1>[3]
wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3]
connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0)
connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0]
connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1)
connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1]
connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2)
connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2]
connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2])
wire _cast_array_to_bits_expr: UInt<1>[3]
connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
wire _cast_to_bits_expr: UInt<3>
connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1]
connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1]
",
};
}
#[hdl_module(outline_generated)]
pub fn check_struct_enum_match() {
#[hdl]

348
crates/fayalite/tests/sim.rs
View file

@ -7,7 +7,7 @@ use fayalite::{
prelude::*,
reset::ResetType,
sim::vcd::VcdWriterDecls,
util::{RcWriter, ready_valid::queue},
util::RcWriter,
};
use std::{collections::BTreeMap, num::NonZeroUsize, rc::Rc};
@ -2495,349 +2495,3 @@ fn test_sim_read_past() {
panic!();
}
}
#[hdl_module(outline_generated)]
pub fn last_connect() {
#[hdl]
let inp: HdlOption<Array<Bool, 4>> = m.input();
#[hdl]
let out: HdlOption<UInt<8>> = m.output();
connect(out, HdlNone());
#[hdl]
if let HdlSome(v) = inp {
#[hdl]
let w = wire();
connect(out, HdlSome(w));
connect(w, v.len() as u8);
for (i, v) in v.into_iter().enumerate() {
#[hdl]
if v {
connect(w, i as u8);
}
}
}
}
#[hdl]
#[test]
fn test_last_connect() {
let _n = SourceLocation::normalize_files_for_tests();
let mut sim = Simulation::new(last_connect());
let mut writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
let bools = [false, true];
sim.write(sim.io().inp, HdlNone());
sim.advance_time(SimDuration::from_micros(1));
let expected: SimValue<HdlOption<UInt<8>>> = #[hdl(sim)]
HdlNone();
assert_eq!(sim.read(sim.io().out), expected);
for a in bools {
for b in bools {
for c in bools {
for d in bools {
let inp = [a, b, c, d];
sim.write(sim.io().inp, HdlSome(inp));
sim.advance_time(SimDuration::from_micros(1));
let mut expected = inp.len() as u8;
for (i, v) in inp.into_iter().enumerate() {
if v {
expected = i as u8;
}
}
let expected: SimValue<HdlOption<UInt<8>>> = #[hdl(sim)]
HdlSome(expected);
let out = sim.read(sim.io().out);
println!("expected={expected:?} out={out:?} inp={inp:?}");
assert_eq!(expected, out);
}
}
}
}
sim.flush_traces().unwrap();
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
if vcd != include_str!("sim/expected/last_connect.vcd") {
panic!();
}
let sim_debug = format!("{sim:#?}");
println!("#######\n{sim_debug}\n#######");
if sim_debug != include_str!("sim/expected/last_connect.txt") {
panic!();
}
}
#[track_caller]
#[hdl]
fn test_queue_helper(
capacity: usize,
inp_ready_is_comb: bool,
out_valid_is_comb: bool,
expected_vcd: &str,
expected_sim_debug: &str,
) {
let _n = SourceLocation::normalize_files_for_tests();
let mut sim = Simulation::new(queue(
UInt::<8>::new_static(),
NonZeroUsize::new(capacity).expect("capacity should be non-zero"),
inp_ready_is_comb,
out_valid_is_comb,
));
let writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
struct DumpVcdOnDrop {
writer: Option<RcWriter>,
}
impl Drop for DumpVcdOnDrop {
fn drop(&mut self) {
if let Some(mut writer) = self.writer.take() {
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
}
}
}
let mut writer = DumpVcdOnDrop {
writer: Some(writer),
};
sim.write_clock(sim.io().cd.clk, false);
sim.write_reset(sim.io().cd.rst, true);
let mut input_value = 0u8;
let mut expected_output_value = 0u8;
/// deterministic random numbers
fn rand(mut v: u32) -> bool {
// random 32-bit primes
v = v.wrapping_mul(0xF807B7EF).rotate_left(16);
v ^= 0xA1E24BBA; // random 32-bit constant
v = v.wrapping_mul(0xE9D30017).rotate_left(16);
v = v.wrapping_mul(0x3895AFFB).rotate_left(16);
v & 1 != 0
}
for cycle in 0..100u32 {
println!("cycle: {cycle}");
sim.write(
sim.io().inp.data,
if rand(cycle) {
#[hdl(sim)]
HdlSome(input_value)
} else {
#[hdl(sim)]
HdlNone()
},
);
sim.write_bool(sim.io().out.ready, rand(u32::MAX / 2 + cycle));
sim.advance_time(SimDuration::from_nanos(500));
if !sim.read_reset(sim.io().cd.rst) {
let inp_ready = sim.read_bool(sim.io().inp.ready);
if inp_ready {
#[hdl(sim)]
if let HdlSome(v) = sim.read(sim.io().inp.data) {
println!("enqueued {v}, expected {input_value:#x}");
assert_eq!(v.as_int(), input_value);
input_value = input_value.wrapping_add(1);
}
}
let out_valid = #[hdl(sim)]
if let HdlSome(v) = sim.read(sim.io().out.data) {
if sim.read_bool(sim.io().out.ready) {
println!("dequeued {v}, expected {expected_output_value:#x}");
assert_eq!(v.as_int(), expected_output_value);
expected_output_value = expected_output_value.wrapping_add(1);
}
true
} else {
false
};
assert!(inp_ready || out_valid, "queue isn't making progress");
}
sim.write_clock(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_nanos(500));
sim.write_clock(sim.io().cd.clk, false);
sim.write_reset(sim.io().cd.rst, false);
}
sim.flush_traces().unwrap();
let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
if vcd != expected_vcd {
panic!();
}
let sim_debug = format!("{sim:#?}");
println!("#######\n{sim_debug}\n#######");
if sim_debug != expected_sim_debug {
panic!();
}
}
#[test]
fn test_queue_1_false_false() {
test_queue_helper(
1,
false,
false,
include_str!("sim/expected/queue_1_false_false.vcd"),
include_str!("sim/expected/queue_1_false_false.txt"),
);
}
#[test]
fn test_queue_1_false_true() {
test_queue_helper(
1,
false,
true,
include_str!("sim/expected/queue_1_false_true.vcd"),
include_str!("sim/expected/queue_1_false_true.txt"),
);
}
#[test]
fn test_queue_1_true_false() {
test_queue_helper(
1,
true,
false,
include_str!("sim/expected/queue_1_true_false.vcd"),
include_str!("sim/expected/queue_1_true_false.txt"),
);
}
#[test]
fn test_queue_1_true_true() {
test_queue_helper(
1,
true,
true,
include_str!("sim/expected/queue_1_true_true.vcd"),
include_str!("sim/expected/queue_1_true_true.txt"),
);
}
#[test]
fn test_queue_2_false_false() {
test_queue_helper(
2,
false,
false,
include_str!("sim/expected/queue_2_false_false.vcd"),
include_str!("sim/expected/queue_2_false_false.txt"),
);
}
#[test]
fn test_queue_2_false_true() {
test_queue_helper(
2,
false,
true,
include_str!("sim/expected/queue_2_false_true.vcd"),
include_str!("sim/expected/queue_2_false_true.txt"),
);
}
#[test]
fn test_queue_2_true_false() {
test_queue_helper(
2,
true,
false,
include_str!("sim/expected/queue_2_true_false.vcd"),
include_str!("sim/expected/queue_2_true_false.txt"),
);
}
#[test]
fn test_queue_2_true_true() {
test_queue_helper(
2,
true,
true,
include_str!("sim/expected/queue_2_true_true.vcd"),
include_str!("sim/expected/queue_2_true_true.txt"),
);
}
#[test]
fn test_queue_3_false_false() {
test_queue_helper(
3,
false,
false,
include_str!("sim/expected/queue_3_false_false.vcd"),
include_str!("sim/expected/queue_3_false_false.txt"),
);
}
#[test]
fn test_queue_3_false_true() {
test_queue_helper(
3,
false,
true,
include_str!("sim/expected/queue_3_false_true.vcd"),
include_str!("sim/expected/queue_3_false_true.txt"),
);
}
#[test]
fn test_queue_3_true_false() {
test_queue_helper(
3,
true,
false,
include_str!("sim/expected/queue_3_true_false.vcd"),
include_str!("sim/expected/queue_3_true_false.txt"),
);
}
#[test]
fn test_queue_3_true_true() {
test_queue_helper(
3,
true,
true,
include_str!("sim/expected/queue_3_true_true.vcd"),
include_str!("sim/expected/queue_3_true_true.txt"),
);
}
#[test]
fn test_queue_4_false_false() {
test_queue_helper(
4,
false,
false,
include_str!("sim/expected/queue_4_false_false.vcd"),
include_str!("sim/expected/queue_4_false_false.txt"),
);
}
#[test]
fn test_queue_4_false_true() {
test_queue_helper(
4,
false,
true,
include_str!("sim/expected/queue_4_false_true.vcd"),
include_str!("sim/expected/queue_4_false_true.txt"),
);
}
#[test]
fn test_queue_4_true_false() {
test_queue_helper(
4,
true,
false,
include_str!("sim/expected/queue_4_true_false.vcd"),
include_str!("sim/expected/queue_4_true_false.txt"),
);
}
#[test]
fn test_queue_4_true_true() {
test_queue_helper(
4,
true,
true,
include_str!("sim/expected/queue_4_true_true.vcd"),
include_str!("sim/expected/queue_4_true_true.txt"),
);
}

59
crates/fayalite/tests/sim/expected/array_rw.txt
View file

@ -424,8 +424,8 @@ Simulation {
},
small_slots: StatePart {
value: [
16 (modified),
0 (modified),
16,
0,
],
},
big_slots: StatePart {
@ -483,7 +483,7 @@ Simulation {
248,
252,
254,
255 (modified),
255,
],
},
sim_only_slots: StatePart {
@ -1218,7 +1218,6 @@ Simulation {
index: StatePartIndex<BigSlots>(0),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xff,
last_state: 0xff,
},
@ -1228,7 +1227,6 @@ Simulation {
index: StatePartIndex<BigSlots>(1),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x7f,
last_state: 0x7f,
},
@ -1238,7 +1236,6 @@ Simulation {
index: StatePartIndex<BigSlots>(2),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x3f,
last_state: 0x3f,
},
@ -1248,7 +1245,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x1f,
last_state: 0x1f,
},
@ -1258,7 +1254,6 @@ Simulation {
index: StatePartIndex<BigSlots>(4),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x0f,
last_state: 0x0f,
},
@ -1268,7 +1263,6 @@ Simulation {
index: StatePartIndex<BigSlots>(5),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x07,
last_state: 0x07,
},
@ -1278,7 +1272,6 @@ Simulation {
index: StatePartIndex<BigSlots>(6),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x03,
last_state: 0x03,
},
@ -1288,7 +1281,6 @@ Simulation {
index: StatePartIndex<BigSlots>(7),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x01,
last_state: 0x01,
},
@ -1298,7 +1290,6 @@ Simulation {
index: StatePartIndex<BigSlots>(8),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -1308,7 +1299,6 @@ Simulation {
index: StatePartIndex<BigSlots>(9),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x80,
last_state: 0x80,
},
@ -1318,7 +1308,6 @@ Simulation {
index: StatePartIndex<BigSlots>(10),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xc0,
last_state: 0xc0,
},
@ -1328,7 +1317,6 @@ Simulation {
index: StatePartIndex<BigSlots>(11),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xe0,
last_state: 0xe0,
},
@ -1338,7 +1326,6 @@ Simulation {
index: StatePartIndex<BigSlots>(12),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xf0,
last_state: 0xf0,
},
@ -1348,7 +1335,6 @@ Simulation {
index: StatePartIndex<BigSlots>(13),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xf8,
last_state: 0xf8,
},
@ -1358,7 +1344,6 @@ Simulation {
index: StatePartIndex<BigSlots>(14),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xfc,
last_state: 0xfc,
},
@ -1368,7 +1353,6 @@ Simulation {
index: StatePartIndex<BigSlots>(15),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xfe,
last_state: 0xfe,
},
@ -1378,7 +1362,6 @@ Simulation {
index: StatePartIndex<BigSlots>(16),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xff,
last_state: 0xff,
},
@ -1388,7 +1371,6 @@ Simulation {
index: StatePartIndex<BigSlots>(17),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x7f,
last_state: 0x7f,
},
@ -1398,7 +1380,6 @@ Simulation {
index: StatePartIndex<BigSlots>(18),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x3f,
last_state: 0x3f,
},
@ -1408,7 +1389,6 @@ Simulation {
index: StatePartIndex<BigSlots>(19),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x1f,
last_state: 0x1f,
},
@ -1418,7 +1398,6 @@ Simulation {
index: StatePartIndex<BigSlots>(20),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x0f,
last_state: 0x0f,
},
@ -1428,7 +1407,6 @@ Simulation {
index: StatePartIndex<BigSlots>(21),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x07,
last_state: 0x07,
},
@ -1438,7 +1416,6 @@ Simulation {
index: StatePartIndex<BigSlots>(22),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x03,
last_state: 0x03,
},
@ -1448,7 +1425,6 @@ Simulation {
index: StatePartIndex<BigSlots>(23),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x01,
last_state: 0x01,
},
@ -1458,7 +1434,6 @@ Simulation {
index: StatePartIndex<BigSlots>(24),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -1468,7 +1443,6 @@ Simulation {
index: StatePartIndex<BigSlots>(25),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x80,
last_state: 0x80,
},
@ -1478,7 +1452,6 @@ Simulation {
index: StatePartIndex<BigSlots>(26),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xc0,
last_state: 0xc0,
},
@ -1488,7 +1461,6 @@ Simulation {
index: StatePartIndex<BigSlots>(27),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xe0,
last_state: 0xe0,
},
@ -1498,7 +1470,6 @@ Simulation {
index: StatePartIndex<BigSlots>(28),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xf0,
last_state: 0xf0,
},
@ -1508,7 +1479,6 @@ Simulation {
index: StatePartIndex<BigSlots>(29),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xf8,
last_state: 0xf8,
},
@ -1518,7 +1488,6 @@ Simulation {
index: StatePartIndex<BigSlots>(30),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xfc,
last_state: 0xfc,
},
@ -1528,7 +1497,6 @@ Simulation {
index: StatePartIndex<BigSlots>(31),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xfe,
last_state: 0xe1,
},
@ -1538,7 +1506,6 @@ Simulation {
index: StatePartIndex<BigSlots>(32),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -1548,7 +1515,6 @@ Simulation {
index: StatePartIndex<BigSlots>(33),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xff,
last_state: 0xff,
},
@ -1558,7 +1524,6 @@ Simulation {
index: StatePartIndex<BigSlots>(34),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x10,
last_state: 0x0f,
},
@ -1568,7 +1533,6 @@ Simulation {
index: StatePartIndex<BigSlots>(35),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0xe1,
},
@ -1577,7 +1541,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(36),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1587,7 +1550,6 @@ Simulation {
index: StatePartIndex<BigSlots>(37),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xff,
last_state: 0xff,
},
@ -1597,7 +1559,6 @@ Simulation {
index: StatePartIndex<BigSlots>(38),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x7f,
last_state: 0x7f,
},
@ -1607,7 +1568,6 @@ Simulation {
index: StatePartIndex<BigSlots>(39),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x3f,
last_state: 0x3f,
},
@ -1617,7 +1577,6 @@ Simulation {
index: StatePartIndex<BigSlots>(40),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x1f,
last_state: 0x1f,
},
@ -1627,7 +1586,6 @@ Simulation {
index: StatePartIndex<BigSlots>(41),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x0f,
last_state: 0x0f,
},
@ -1637,7 +1595,6 @@ Simulation {
index: StatePartIndex<BigSlots>(42),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x07,
last_state: 0x07,
},
@ -1647,7 +1604,6 @@ Simulation {
index: StatePartIndex<BigSlots>(43),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x03,
last_state: 0x03,
},
@ -1657,7 +1613,6 @@ Simulation {
index: StatePartIndex<BigSlots>(44),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x01,
last_state: 0x01,
},
@ -1667,7 +1622,6 @@ Simulation {
index: StatePartIndex<BigSlots>(45),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -1677,7 +1631,6 @@ Simulation {
index: StatePartIndex<BigSlots>(46),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x80,
last_state: 0x80,
},
@ -1687,7 +1640,6 @@ Simulation {
index: StatePartIndex<BigSlots>(47),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xc0,
last_state: 0xc0,
},
@ -1697,7 +1649,6 @@ Simulation {
index: StatePartIndex<BigSlots>(48),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xe0,
last_state: 0xe0,
},
@ -1707,7 +1658,6 @@ Simulation {
index: StatePartIndex<BigSlots>(49),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xf0,
last_state: 0xf0,
},
@ -1717,7 +1667,6 @@ Simulation {
index: StatePartIndex<BigSlots>(50),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xf8,
last_state: 0xf8,
},
@ -1727,7 +1676,6 @@ Simulation {
index: StatePartIndex<BigSlots>(51),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xfc,
last_state: 0xfc,
},
@ -1737,7 +1685,6 @@ Simulation {
index: StatePartIndex<BigSlots>(52),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xfe,
last_state: 0xe1,
},

6
crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
View file

@ -86,8 +86,8 @@ Simulation {
value: [
1,
0,
1 (modified),
0 (modified),
1,
0,
],
},
sim_only_slots: StatePart {
@ -155,7 +155,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x1,
last_state: 0x0,
},
@ -164,7 +163,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},

3
crates/fayalite/tests/sim/expected/connect_const.txt
View file

@ -63,7 +63,7 @@ Simulation {
big_slots: StatePart {
value: [
5,
5 (modified),
5,
],
},
sim_only_slots: StatePart {
@ -124,7 +124,6 @@ Simulation {
index: StatePartIndex<BigSlots>(0),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x05,
last_state: 0x05,
},

8
crates/fayalite/tests/sim/expected/connect_const_reset.txt
View file

@ -90,9 +90,9 @@ Simulation {
value: [
1,
1,
1 (modified),
1 (modified),
1 (modified),
1,
1,
1,
],
},
sim_only_slots: StatePart {
@ -175,7 +175,6 @@ Simulation {
kind: BigAsyncReset {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -184,7 +183,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},

58
crates/fayalite/tests/sim/expected/counter_async.txt
View file

@ -123,72 +123,68 @@ Simulation {
dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
},
8: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:1:1
9: Add {
8: Add {
dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
rhs: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
10: CastToUInt {
9: CastToUInt {
dest: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
dest_width: 4,
},
// at: module-XXXXXXXXXX.rs:4:1
11: Copy {
10: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
src: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:6:1
12: Copy {
11: Copy {
dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:3:1
13: BranchIfSmallNonZero {
target: 17,
12: BranchIfSmallNonZero {
target: 16,
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
14: BranchIfSmallZero {
target: 18,
13: BranchIfSmallZero {
target: 17,
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
15: Copy {
14: Copy {
dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
},
16: Branch {
target: 18,
15: Branch {
target: 17,
},
17: Copy {
16: Copy {
dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
},
18: XorSmallImmediate {
17: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:1:1
19: Return,
18: Return,
],
..
},
pc: 19,
pc: 18,
memory_write_log: [],
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [
0 (modified),
0 (modified),
1 (modified),
0 (modified),
0,
0,
1,
0,
],
},
big_slots: StatePart {
@ -197,12 +193,12 @@ Simulation {
0,
3,
3,
4 (modified),
3 (modified),
0 (modified),
1 (modified),
4 (modified),
4 (modified),
4,
3,
0,
1,
4,
4,
],
},
sim_only_slots: StatePart {
@ -332,7 +328,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x1,
last_state: 0x0,
},
@ -341,7 +336,6 @@ Simulation {
kind: BigAsyncReset {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -351,7 +345,6 @@ Simulation {
index: StatePartIndex<BigSlots>(2),
ty: UInt<4>,
},
maybe_changed: true,
state: 0x3,
last_state: 0x2,
},
@ -361,7 +354,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<4>,
},
maybe_changed: true,
state: 0x3,
last_state: 0x2,
},

66
crates/fayalite/tests/sim/expected/counter_sync.txt
View file

@ -102,75 +102,71 @@ Simulation {
src: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
dest_width: 4,
},
// at: module-XXXXXXXXXX.rs:4:1
4: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:3:1
4: IsNonZeroDestIsSmall {
5: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
},
5: IsNonZeroDestIsSmall {
6: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
},
6: AndSmall {
7: AndSmall {
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
7: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:4:1
8: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:1:1
9: Const {
8: Const {
dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
value: 0x3,
},
// at: module-XXXXXXXXXX.rs:3:1
10: BranchIfSmallZero {
target: 15,
9: BranchIfSmallZero {
target: 14,
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
11: BranchIfSmallNonZero {
target: 14,
10: BranchIfSmallNonZero {
target: 13,
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
12: Copy {
11: Copy {
dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
},
13: Branch {
target: 15,
12: Branch {
target: 14,
},
14: Copy {
13: Copy {
dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
},
15: XorSmallImmediate {
14: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:1:1
16: Return,
15: Return,
],
..
},
pc: 16,
pc: 15,
memory_write_log: [],
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [
0 (modified),
0 (modified),
1 (modified),
0 (modified),
0,
0,
1,
0,
],
},
big_slots: StatePart {
@ -179,11 +175,11 @@ Simulation {
0,
3,
3,
4 (modified),
3 (modified),
1 (modified),
4 (modified),
4 (modified),
4,
3,
1,
4,
4,
],
},
sim_only_slots: StatePart {
@ -313,7 +309,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x1,
last_state: 0x0,
},
@ -322,7 +317,6 @@ Simulation {
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -332,7 +326,6 @@ Simulation {
index: StatePartIndex<BigSlots>(2),
ty: UInt<4>,
},
maybe_changed: true,
state: 0x3,
last_state: 0x2,
},
@ -342,7 +335,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<4>,
},
maybe_changed: true,
state: 0x3,
last_state: 0x2,
},

6
crates/fayalite/tests/sim/expected/duplicate_names.txt
View file

@ -81,9 +81,9 @@ Simulation {
big_slots: StatePart {
value: [
5,
5 (modified),
5,
6,
6,
6 (modified),
],
},
sim_only_slots: StatePart {
@ -137,7 +137,6 @@ Simulation {
index: StatePartIndex<BigSlots>(0),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x05,
last_state: 0x05,
},
@ -147,7 +146,6 @@ Simulation {
index: StatePartIndex<BigSlots>(2),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x06,
last_state: 0x06,
},

307
crates/fayalite/tests/sim/expected/enums.txt
View file

@ -1012,177 +1012,173 @@ Simulation {
lhs: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
99: Copy {
dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
// at: module-XXXXXXXXXX.rs:1:1
100: Const {
99: Const {
dest: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
value: 0x0,
},
101: Copy {
100: Copy {
dest: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
},
// at: module-XXXXXXXXXX.rs:12:1
102: BranchIfZero {
target: 110,
101: BranchIfZero {
target: 109,
value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:13:1
103: BranchIfZero {
target: 105,
102: BranchIfZero {
target: 104,
value: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:14:1
104: Copy {
103: Copy {
dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
// at: module-XXXXXXXXXX.rs:13:1
105: BranchIfNonZero {
target: 110,
104: BranchIfNonZero {
target: 109,
value: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:15:1
106: BranchIfZero {
target: 108,
105: BranchIfZero {
target: 107,
value: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:16:1
107: Copy {
106: Copy {
dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
// at: module-XXXXXXXXXX.rs:15:1
108: BranchIfNonZero {
target: 110,
107: BranchIfNonZero {
target: 109,
value: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:17:1
109: Copy {
108: Copy {
dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
// at: module-XXXXXXXXXX.rs:10:1
110: Copy {
109: Copy {
dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
},
// at: module-XXXXXXXXXX.rs:1:1
111: Copy {
110: Copy {
dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
},
112: SliceInt {
111: SliceInt {
dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
start: 1,
len: 2,
},
113: SliceInt {
112: SliceInt {
dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
start: 0,
len: 1,
},
114: SliceInt {
113: SliceInt {
dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
start: 1,
len: 1,
},
115: Copy {
114: Copy {
dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
},
116: Copy {
115: Copy {
dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
src: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
},
117: Copy {
116: Copy {
dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: ".1", ty: Bool },
src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:9:1
118: AndBigWithSmallImmediate {
117: AndBigWithSmallImmediate {
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:1:1
119: Copy {
118: Copy {
dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
},
120: SliceInt {
119: SliceInt {
dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
start: 1,
len: 2,
},
121: SliceInt {
120: SliceInt {
dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
start: 0,
len: 1,
},
122: SliceInt {
121: SliceInt {
dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
start: 1,
len: 1,
},
123: Copy {
122: Copy {
dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
},
124: Copy {
123: Copy {
dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
},
125: Copy {
124: Copy {
dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: ".1", ty: Bool },
src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:8:1
126: AndBigWithSmallImmediate {
125: AndBigWithSmallImmediate {
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
lhs: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:11:1
127: BranchIfSmallZero {
target: 132,
126: BranchIfSmallZero {
target: 131,
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
128: BranchIfSmallNonZero {
target: 131,
127: BranchIfSmallNonZero {
target: 130,
value: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
129: Copy {
128: Copy {
dest: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
130: Branch {
target: 132,
129: Branch {
target: 131,
},
131: Copy {
130: Copy {
dest: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
132: XorSmallImmediate {
131: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:1:1
133: Return,
132: Return,
],
..
},
pc: 133,
pc: 132,
memory_write_log: [],
memories: StatePart {
value: [],
@ -1191,10 +1187,10 @@ Simulation {
value: [
0,
0,
0 (modified),
0 (modified),
1 (modified),
0 (modified),
0,
0,
1,
0,
2,
],
},
@ -1207,110 +1203,110 @@ Simulation {
15,
2,
15,
0 (modified),
0,
0,
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0,
0,
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
62 (modified),
62 (modified),
0 (modified),
0 (modified),
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
62,
62,
0,
0,
1,
1,
62,
3,
1,
1,
1,
62 (modified),
3 (modified),
1 (modified),
1 (modified),
1 (modified),
1,
1,
-1,
1 (modified),
1 (modified),
15 (modified),
3 (modified),
1 (modified),
1 (modified),
3 (modified),
-1 (modified),
0 (modified),
0 (modified),
1 (modified),
0 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
2 (modified),
3 (modified),
12 (modified),
13 (modified),
13 (modified),
13 (modified),
2 (modified),
1 (modified),
1 (modified),
-1 (modified),
2 (modified),
1 (modified),
1 (modified),
-1 (modified),
1 (modified),
1 (modified),
1 (modified),
3 (modified),
-1 (modified),
2 (modified),
3 (modified),
3 (modified),
12 (modified),
15 (modified),
60 (modified),
62 (modified),
62 (modified),
62 (modified),
0 (modified),
0 (modified),
0 (modified),
1 (modified),
2 (modified),
3 (modified),
3 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
2 (modified),
3 (modified),
6 (modified),
7 (modified),
7 (modified),
7 (modified),
2 (modified),
3 (modified),
3 (modified),
12 (modified),
15 (modified),
1,
1,
15,
3,
1,
1,
3,
-1,
0,
0,
1,
0,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
2,
3,
12,
13,
13,
13,
2,
1,
1,
-1,
2,
1,
1,
-1,
1,
1,
1,
3,
-1,
2,
3,
3,
12,
15,
60,
62,
62,
62,
0,
0,
0,
1,
2,
3,
3,
1,
1,
1,
1,
1,
2,
3,
6,
7,
7,
7,
2,
3,
3,
12,
15,
],
},
sim_only_slots: StatePart {
@ -1746,7 +1742,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x1,
last_state: 0x0,
},
@ -1755,7 +1750,6 @@ Simulation {
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1764,7 +1758,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: false,
state: 0x1,
last_state: 0x1,
},
@ -1774,7 +1767,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<2>,
},
maybe_changed: false,
state: 0x2,
last_state: 0x2,
},
@ -1784,7 +1776,6 @@ Simulation {
index: StatePartIndex<BigSlots>(4),
ty: UInt<4>,
},
maybe_changed: false,
state: 0xf,
last_state: 0xf,
},
@ -1794,7 +1785,6 @@ Simulation {
index: StatePartIndex<BigSlots>(5),
ty: UInt<2>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x2,
},
@ -1804,7 +1794,6 @@ Simulation {
index: StatePartIndex<BigSlots>(6),
ty: UInt<4>,
},
maybe_changed: true,
state: 0xf,
last_state: 0xf,
},
@ -1817,7 +1806,6 @@ Simulation {
HdlSome(Bundle {0: UInt<1>, 1: Bool}),
},
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1827,7 +1815,6 @@ Simulation {
index: StatePartIndex<BigSlots>(8),
ty: UInt<1>,
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1836,7 +1823,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(9),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1849,7 +1835,6 @@ Simulation {
HdlSome(Bundle {0: UInt<1>, 1: Bool}),
},
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1859,7 +1844,6 @@ Simulation {
index: StatePartIndex<BigSlots>(16),
ty: UInt<1>,
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1868,7 +1852,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(17),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1882,7 +1865,6 @@ Simulation {
C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
},
},
maybe_changed: true,
state: 0x2,
last_state: 0x2,
},
@ -1892,7 +1874,6 @@ Simulation {
index: StatePartIndex<BigSlots>(27),
ty: UInt<1>,
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1901,7 +1882,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(28),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1911,7 +1891,6 @@ Simulation {
index: StatePartIndex<BigSlots>(34),
ty: UInt<1>,
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1921,7 +1900,6 @@ Simulation {
index: StatePartIndex<BigSlots>(35),
ty: UInt<1>,
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1931,7 +1909,6 @@ Simulation {
index: StatePartIndex<BigSlots>(36),
ty: SInt<2>,
},
maybe_changed: true,
state: 0x3,
last_state: 0x3,
},

2
crates/fayalite/tests/sim/expected/extern_module.txt
View file

@ -221,7 +221,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: false,
state: 0x1,
last_state: 0x1,
},
@ -230,7 +229,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x1,
last_state: 0x0,
},

5
crates/fayalite/tests/sim/expected/extern_module2.txt
View file

@ -57,7 +57,7 @@ Simulation {
big_slots: StatePart {
value: [
0,
1 (modified),
1,
101,
],
},
@ -280,7 +280,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -289,7 +288,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -299,7 +297,6 @@ Simulation {
index: StatePartIndex<BigSlots>(2),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x65,
last_state: 0x65,
},

709
crates/fayalite/tests/sim/expected/last_connect.txt
View file

@ -1,709 +0,0 @@
Simulation {
state: State {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 2,
debug_data: [
SlotDebugData {
name: "",
ty: Enum {
HdlNone,
HdlSome,
},
},
SlotDebugData {
name: "",
ty: Enum {
HdlNone,
HdlSome,
},
},
],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 33,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(last_connect: last_connect).last_connect::inp",
ty: Enum {
HdlNone,
HdlSome(Array<Bool, 4>),
},
},
SlotDebugData {
name: "[0]",
ty: Bool,
},
SlotDebugData {
name: "[1]",
ty: Bool,
},
SlotDebugData {
name: "[2]",
ty: Bool,
},
SlotDebugData {
name: "[3]",
ty: Bool,
},
SlotDebugData {
name: "",
ty: UInt<5>,
},
SlotDebugData {
name: "",
ty: UInt<4>,
},
SlotDebugData {
name: "",
ty: UInt<1>,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "",
ty: UInt<1>,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "",
ty: UInt<1>,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "",
ty: UInt<1>,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(last_connect: last_connect).last_connect::out",
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
},
SlotDebugData {
name: "",
ty: UInt<9>,
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<9>,
},
SlotDebugData {
name: "",
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
},
SlotDebugData {
name: "InstantiatedModule(last_connect: last_connect).last_connect::w",
ty: UInt<8>,
},
SlotDebugData {
name: ".0",
ty: UInt<1>,
},
SlotDebugData {
name: ".1",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<1>,
},
SlotDebugData {
name: "",
ty: UInt<9>,
},
SlotDebugData {
name: "",
ty: UInt<9>,
},
SlotDebugData {
name: "",
ty: UInt<9>,
},
SlotDebugData {
name: "",
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
insns: [
// at: module-XXXXXXXXXX.rs:1:1
0: Const {
dest: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
value: 0x3,
},
1: Const {
dest: StatePartIndex<BigSlots>(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> },
value: 0x2,
},
2: Const {
dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
value: 0x1,
},
3: Const {
dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
value: 0x0,
},
4: Const {
dest: StatePartIndex<BigSlots>(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> },
value: 0x4,
},
// at: module-XXXXXXXXXX.rs:8:1
5: Copy {
dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
src: StatePartIndex<BigSlots>(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:1:1
6: Const {
dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
value: 0x1,
},
7: Const {
dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> },
value: 0x0,
},
8: Copy {
dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> },
},
// at: module-XXXXXXXXXX.rs:4:1
9: Copy {
dest: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
},
// at: module-XXXXXXXXXX.rs:1:1
10: Copy {
dest: StatePartIndex<BigSlots>(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> },
src: StatePartIndex<BigSlots>(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array<Bool, 4>)} },
},
11: SliceInt {
dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> },
start: 1,
len: 4,
},
12: SliceInt {
dest: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
start: 0,
len: 1,
},
13: Copy {
dest: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
14: SliceInt {
dest: StatePartIndex<BigSlots>(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
start: 1,
len: 1,
},
15: Copy {
dest: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
16: SliceInt {
dest: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
start: 2,
len: 1,
},
17: Copy {
dest: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
18: SliceInt {
dest: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
start: 3,
len: 1,
},
19: Copy {
dest: StatePartIndex<BigSlots>(14), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
20: Copy {
dest: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool },
src: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
},
21: Copy {
dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool },
src: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "", ty: Bool },
},
22: Copy {
dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool },
src: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "", ty: Bool },
},
23: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool },
src: StatePartIndex<BigSlots>(14), // (0x1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:9:1
24: BranchIfZero {
target: 26,
value: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
25: Copy {
dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:9:1
26: BranchIfZero {
target: 28,
value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
27: Copy {
dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:9:1
28: BranchIfZero {
target: 30,
value: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
29: Copy {
dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
src: StatePartIndex<BigSlots>(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:9:1
30: BranchIfZero {
target: 32,
value: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
31: Copy {
dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
src: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:1:1
32: Copy {
dest: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
33: Copy {
dest: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> },
src: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
},
34: Shl {
dest: StatePartIndex<BigSlots>(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> },
lhs: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> },
rhs: 1,
},
35: Or {
dest: StatePartIndex<BigSlots>(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
lhs: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
rhs: StatePartIndex<BigSlots>(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> },
},
36: CastToUInt {
dest: StatePartIndex<BigSlots>(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
src: StatePartIndex<BigSlots>(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
dest_width: 9,
},
37: Copy {
dest: StatePartIndex<BigSlots>(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
src: StatePartIndex<BigSlots>(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
},
// at: module-XXXXXXXXXX.rs:2:1
38: AndBigWithSmallImmediate {
dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
lhs: StatePartIndex<BigSlots>(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array<Bool, 4>)} },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:5:1
39: BranchIfSmallNeImmediate {
target: 41,
lhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:7:1
40: Copy {
dest: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
src: StatePartIndex<BigSlots>(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
},
// at: module-XXXXXXXXXX.rs:3:1
41: AndBigWithSmallImmediate {
dest: StatePartIndex<SmallSlots>(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
lhs: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:1:1
42: Copy {
dest: StatePartIndex<BigSlots>(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
src: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
},
43: SliceInt {
dest: StatePartIndex<BigSlots>(17), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
src: StatePartIndex<BigSlots>(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
start: 1,
len: 8,
},
44: Return,
],
..
},
pc: 44,
memory_write_log: [],
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [
1,
1,
],
},
big_slots: StatePart {
value: [
31 (modified),
1,
1,
1,
1,
31 (modified),
15 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
1 (modified),
7 (modified),
7 (modified),
3,
0 (modified),
0 (modified),
3,
1 (modified),
3 (modified),
1 (modified),
6 (modified),
7 (modified),
7 (modified),
7 (modified),
4 (modified),
0 (modified),
1 (modified),
2 (modified),
3 (modified),
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::last_connect,
instantiated: Module {
name: last_connect,
..
},
},
main_module: SimulationModuleState {
base_targets: [
Instance {
name: <simulator>::last_connect,
instantiated: Module {
name: last_connect,
..
},
}.inp,
Instance {
name: <simulator>::last_connect,
instantiated: Module {
name: last_connect,
..
},
}.out,
],
uninitialized_ios: {},
io_targets: {
Instance {
name: <simulator>::last_connect,
instantiated: Module {
name: last_connect,
..
},
}.inp,
Instance {
name: <simulator>::last_connect,
instantiated: Module {
name: last_connect,
..
},
}.out,
},
did_initial_settle: true,
clocks_for_past: {},
},
extern_modules: [],
trace_decls: TraceModule {
name: "last_connect",
children: [
TraceModuleIO {
name: "inp",
child: TraceEnumWithFields {
name: "inp",
discriminant: TraceEnumDiscriminant {
location: TraceScalarId(0),
name: "$tag",
ty: Enum {
HdlNone,
HdlSome(Array<Bool, 4>),
},
flow: Source,
},
non_empty_fields: [
TraceArray {
name: "HdlSome",
elements: [
TraceBool {
location: TraceScalarId(1),
name: "[0]",
flow: Source,
},
TraceBool {
location: TraceScalarId(2),
name: "[1]",
flow: Source,
},
TraceBool {
location: TraceScalarId(3),
name: "[2]",
flow: Source,
},
TraceBool {
location: TraceScalarId(4),
name: "[3]",
flow: Source,
},
],
ty: Array<Bool, 4>,
flow: Source,
},
],
ty: Enum {
HdlNone,
HdlSome(Array<Bool, 4>),
},
flow: Source,
},
ty: Enum {
HdlNone,
HdlSome(Array<Bool, 4>),
},
flow: Source,
},
TraceModuleIO {
name: "out",
child: TraceEnumWithFields {
name: "out",
discriminant: TraceEnumDiscriminant {
location: TraceScalarId(5),
name: "$tag",
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
flow: Sink,
},
non_empty_fields: [
TraceUInt {
location: TraceScalarId(6),
name: "HdlSome",
ty: UInt<8>,
flow: Source,
},
],
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
flow: Sink,
},
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
flow: Sink,
},
TraceWire {
name: "w",
child: TraceUInt {
location: TraceScalarId(7),
name: "w",
ty: UInt<8>,
flow: Duplex,
},
ty: UInt<8>,
},
],
},
traces: [
SimTrace {
id: TraceScalarId(0),
kind: EnumDiscriminant {
index: StatePartIndex<SmallSlots>(0),
ty: Enum {
HdlNone,
HdlSome(Array<Bool, 4>),
},
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(1),
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(2),
kind: BigBool {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(3),
kind: BigBool {
index: StatePartIndex<BigSlots>(3),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(4),
kind: BigBool {
index: StatePartIndex<BigSlots>(4),
},
maybe_changed: true,
state: 0x1,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(5),
kind: EnumDiscriminant {
index: StatePartIndex<SmallSlots>(1),
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(6),
kind: BigUInt {
index: StatePartIndex<BigSlots>(17),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x03,
last_state: 0x02,
},
SimTrace {
id: TraceScalarId(7),
kind: BigUInt {
index: StatePartIndex<BigSlots>(20),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x03,
last_state: 0x02,
},
],
trace_memories: {},
trace_writers: [
Running(
VcdWriter {
finished_init: true,
timescale: 1 ps,
..
},
),
],
clocks_triggered: [],
event_queue: EventQueue(EventQueueData {
instant: 17 μs,
events: {},
}),
waiting_sensitivity_sets_by_address: {},
waiting_sensitivity_sets_by_compiled_value: {},
..
}

104
crates/fayalite/tests/sim/expected/last_connect.vcd
View file

@ -1,104 +0,0 @@
$timescale 1 ps $end
$scope module last_connect $end
$scope struct inp $end
$var string 1 !C&}* \$tag $end
$scope struct HdlSome $end
$var wire 1 D_viZ \[0] $end
$var wire 1 b5gFK \[1] $end
$var wire 1 xUBRH \[2] $end
$var wire 1 Gp7Xm \[3] $end
$upscope $end
$upscope $end
$scope struct out $end
$var string 1 ^Z_p3 \$tag $end
$var wire 8 rz~), HdlSome $end
$upscope $end
$var wire 8 dlea> w $end
$upscope $end
$enddefinitions $end
$dumpvars
sHdlNone\x20(0) !C&}*
0D_viZ
0b5gFK
0xUBRH
0Gp7Xm
sHdlNone\x20(0) ^Z_p3
b0 rz~),
b100 dlea>
$end
#1000000
sHdlSome\x20(1) !C&}*
sHdlSome\x20(1) ^Z_p3
b100 rz~),
#2000000
1Gp7Xm
b11 rz~),
b11 dlea>
#3000000
1xUBRH
0Gp7Xm
b10 rz~),
b10 dlea>
#4000000
1Gp7Xm
b11 rz~),
b11 dlea>
#5000000
1b5gFK
0xUBRH
0Gp7Xm
b1 rz~),
b1 dlea>
#6000000
1Gp7Xm
b11 rz~),
b11 dlea>
#7000000
1xUBRH
0Gp7Xm
b10 rz~),
b10 dlea>
#8000000
1Gp7Xm
b11 rz~),
b11 dlea>
#9000000
1D_viZ
0b5gFK
0xUBRH
0Gp7Xm
b0 rz~),
b0 dlea>
#10000000
1Gp7Xm
b11 rz~),
b11 dlea>
#11000000
1xUBRH
0Gp7Xm
b10 rz~),
b10 dlea>
#12000000
1Gp7Xm
b11 rz~),
b11 dlea>
#13000000
1b5gFK
0xUBRH
0Gp7Xm
b1 rz~),
b1 dlea>
#14000000
1Gp7Xm
b11 rz~),
b11 dlea>
#15000000
1xUBRH
0Gp7Xm
b10 rz~),
b10 dlea>
#16000000
1Gp7Xm
b11 rz~),
b11 dlea>
#17000000

368
crates/fayalite/tests/sim/expected/many_memories.txt
View file

File diff suppressed because it is too large Load diff

56
crates/fayalite/tests/sim/expected/memories.txt
View file

@ -522,18 +522,18 @@ Simulation {
},
small_slots: StatePart {
value: [
1 (modified),
0 (modified),
0 (modified),
1 (modified),
2 (modified),
1 (modified),
0 (modified),
0 (modified),
0 (modified),
2 (modified),
2 (modified),
0 (modified),
1,
0,
0,
1,
2,
1,
0,
0,
0,
2,
2,
0,
],
},
big_slots: StatePart {
@ -562,10 +562,10 @@ Simulation {
-32,
1,
1,
208 (modified),
-32 (modified),
1 (modified),
1 (modified),
208,
-32,
1,
1,
],
},
sim_only_slots: StatePart {
@ -1168,7 +1168,6 @@ Simulation {
index: StatePartIndex<BigSlots>(0),
ty: UInt<4>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x2,
},
@ -1177,7 +1176,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1186,7 +1184,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -1196,7 +1193,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xb0,
last_state: 0xb0,
},
@ -1206,7 +1202,6 @@ Simulation {
index: StatePartIndex<BigSlots>(4),
ty: SInt<8>,
},
maybe_changed: true,
state: 0xc0,
last_state: 0xc0,
},
@ -1216,7 +1211,6 @@ Simulation {
index: StatePartIndex<BigSlots>(5),
ty: UInt<4>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x2,
},
@ -1225,7 +1219,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(6),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1234,7 +1227,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(7),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -1244,7 +1236,6 @@ Simulation {
index: StatePartIndex<BigSlots>(8),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xd0,
last_state: 0xd0,
},
@ -1254,7 +1245,6 @@ Simulation {
index: StatePartIndex<BigSlots>(9),
ty: SInt<8>,
},
maybe_changed: true,
state: 0xe0,
last_state: 0xe0,
},
@ -1263,7 +1253,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(10),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1272,7 +1261,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(11),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1282,7 +1270,6 @@ Simulation {
index: StatePartIndex<BigSlots>(12),
ty: UInt<4>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x2,
},
@ -1291,7 +1278,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(13),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1300,7 +1286,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(14),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -1310,7 +1295,6 @@ Simulation {
index: StatePartIndex<BigSlots>(15),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xb0,
last_state: 0xb0,
},
@ -1320,7 +1304,6 @@ Simulation {
index: StatePartIndex<BigSlots>(16),
ty: SInt<8>,
},
maybe_changed: true,
state: 0xc0,
last_state: 0xc0,
},
@ -1330,7 +1313,6 @@ Simulation {
index: StatePartIndex<BigSlots>(17),
ty: UInt<4>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x2,
},
@ -1339,7 +1321,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(18),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1348,7 +1329,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(19),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -1358,7 +1338,6 @@ Simulation {
index: StatePartIndex<BigSlots>(20),
ty: UInt<8>,
},
maybe_changed: true,
state: 0xd0,
last_state: 0xd0,
},
@ -1368,7 +1347,6 @@ Simulation {
index: StatePartIndex<BigSlots>(21),
ty: SInt<8>,
},
maybe_changed: true,
state: 0xe0,
last_state: 0xe0,
},
@ -1377,7 +1355,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(22),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1386,7 +1363,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(23),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},

78
crates/fayalite/tests/sim/expected/memories2.txt
View file

@ -545,15 +545,15 @@ Simulation {
value: [
0,
0,
1 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
1,
0,
0,
0,
0,
0,
0,
0,
0,
],
},
big_slots: StatePart {
@ -568,32 +568,32 @@ Simulation {
0,
0,
0,
0 (modified),
0,
0 (modified),
0,
0 (modified),
0 (modified),
0,
0 (modified),
0 (modified),
0,
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
1 (modified),
0 (modified),
1 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
1 (modified),
1 (modified),
1 (modified),
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
0,
0,
0,
1,
1,
1,
],
},
sim_only_slots: StatePart {
@ -943,7 +943,6 @@ Simulation {
index: StatePartIndex<BigSlots>(0),
ty: UInt<3>,
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -952,7 +951,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -961,7 +959,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -971,7 +968,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<2>,
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -980,7 +976,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(4),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -990,7 +985,6 @@ Simulation {
index: StatePartIndex<BigSlots>(5),
ty: UInt<2>,
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -999,7 +993,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(6),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1009,7 +1002,6 @@ Simulation {
index: StatePartIndex<BigSlots>(7),
ty: UInt<3>,
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1018,7 +1010,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(8),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1027,7 +1018,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(9),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -1040,7 +1030,6 @@ Simulation {
HdlSome(Bool),
},
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1049,7 +1038,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(16),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1058,7 +1046,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(11),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1071,7 +1058,6 @@ Simulation {
HdlSome(Bool),
},
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1080,7 +1066,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(19),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1089,7 +1074,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(13),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},

184
crates/fayalite/tests/sim/expected/memories3.txt
View file

@ -1356,20 +1356,20 @@ Simulation {
},
small_slots: StatePart {
value: [
1 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
1 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
1,
0,
0,
0,
0,
1,
0,
0,
0,
0,
0,
0,
0,
0,
],
},
big_slots: StatePart {
@ -1415,22 +1415,6 @@ Simulation {
0,
0,
0,
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0,
0,
0,
@ -1450,38 +1434,54 @@ Simulation {
0,
0,
0,
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
],
},
sim_only_slots: StatePart {
@ -2391,7 +2391,6 @@ Simulation {
index: StatePartIndex<BigSlots>(0),
ty: UInt<3>,
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2400,7 +2399,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2409,7 +2407,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -2419,7 +2416,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2429,7 +2425,6 @@ Simulation {
index: StatePartIndex<BigSlots>(4),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2439,7 +2434,6 @@ Simulation {
index: StatePartIndex<BigSlots>(5),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2449,7 +2443,6 @@ Simulation {
index: StatePartIndex<BigSlots>(6),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2459,7 +2452,6 @@ Simulation {
index: StatePartIndex<BigSlots>(7),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2469,7 +2461,6 @@ Simulation {
index: StatePartIndex<BigSlots>(8),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2479,7 +2470,6 @@ Simulation {
index: StatePartIndex<BigSlots>(9),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2489,7 +2479,6 @@ Simulation {
index: StatePartIndex<BigSlots>(10),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2499,7 +2488,6 @@ Simulation {
index: StatePartIndex<BigSlots>(11),
ty: UInt<3>,
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2508,7 +2496,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(12),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2517,7 +2504,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(13),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -2527,7 +2513,6 @@ Simulation {
index: StatePartIndex<BigSlots>(14),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2537,7 +2522,6 @@ Simulation {
index: StatePartIndex<BigSlots>(15),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2547,7 +2531,6 @@ Simulation {
index: StatePartIndex<BigSlots>(16),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2557,7 +2540,6 @@ Simulation {
index: StatePartIndex<BigSlots>(17),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2567,7 +2549,6 @@ Simulation {
index: StatePartIndex<BigSlots>(18),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2577,7 +2558,6 @@ Simulation {
index: StatePartIndex<BigSlots>(19),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2587,7 +2567,6 @@ Simulation {
index: StatePartIndex<BigSlots>(20),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2597,7 +2576,6 @@ Simulation {
index: StatePartIndex<BigSlots>(21),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2606,7 +2584,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(22),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2615,7 +2592,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(23),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2624,7 +2600,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(24),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2633,7 +2608,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(25),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2642,7 +2616,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(26),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2651,7 +2624,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(27),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2660,7 +2632,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(28),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2669,7 +2640,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(29),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2679,7 +2649,6 @@ Simulation {
index: StatePartIndex<BigSlots>(30),
ty: UInt<3>,
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2688,7 +2657,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(31),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2697,7 +2665,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(32),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -2707,7 +2674,6 @@ Simulation {
index: StatePartIndex<BigSlots>(33),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2717,7 +2683,6 @@ Simulation {
index: StatePartIndex<BigSlots>(34),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2727,7 +2692,6 @@ Simulation {
index: StatePartIndex<BigSlots>(35),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2737,7 +2701,6 @@ Simulation {
index: StatePartIndex<BigSlots>(36),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2747,7 +2710,6 @@ Simulation {
index: StatePartIndex<BigSlots>(37),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2757,7 +2719,6 @@ Simulation {
index: StatePartIndex<BigSlots>(38),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2767,7 +2728,6 @@ Simulation {
index: StatePartIndex<BigSlots>(39),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2777,7 +2737,6 @@ Simulation {
index: StatePartIndex<BigSlots>(40),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2787,7 +2746,6 @@ Simulation {
index: StatePartIndex<BigSlots>(57),
ty: UInt<3>,
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2796,7 +2754,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(58),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2805,7 +2762,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(59),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -2815,7 +2771,6 @@ Simulation {
index: StatePartIndex<BigSlots>(60),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2825,7 +2780,6 @@ Simulation {
index: StatePartIndex<BigSlots>(61),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2835,7 +2789,6 @@ Simulation {
index: StatePartIndex<BigSlots>(62),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2845,7 +2798,6 @@ Simulation {
index: StatePartIndex<BigSlots>(63),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2855,7 +2807,6 @@ Simulation {
index: StatePartIndex<BigSlots>(64),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2865,7 +2816,6 @@ Simulation {
index: StatePartIndex<BigSlots>(65),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2875,7 +2825,6 @@ Simulation {
index: StatePartIndex<BigSlots>(66),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2885,7 +2834,6 @@ Simulation {
index: StatePartIndex<BigSlots>(67),
ty: UInt<8>,
},
maybe_changed: true,
state: 0x00,
last_state: 0x00,
},
@ -2894,7 +2842,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(68),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2903,7 +2850,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(69),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2912,7 +2858,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(70),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2921,7 +2866,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(71),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2930,7 +2874,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(72),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2939,7 +2882,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(73),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2948,7 +2890,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(74),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -2957,7 +2898,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(75),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},

22
crates/fayalite/tests/sim/expected/mod1.txt
View file

@ -207,11 +207,11 @@ Simulation {
-2,
-2,
15,
-2 (modified),
14 (modified),
5 (modified),
1 (modified),
15 (modified),
-2,
14,
5,
1,
15,
],
},
sim_only_slots: StatePart {
@ -445,7 +445,6 @@ Simulation {
index: StatePartIndex<BigSlots>(0),
ty: UInt<4>,
},
maybe_changed: true,
state: 0xa,
last_state: 0x3,
},
@ -455,7 +454,6 @@ Simulation {
index: StatePartIndex<BigSlots>(1),
ty: SInt<2>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x3,
},
@ -465,7 +463,6 @@ Simulation {
index: StatePartIndex<BigSlots>(2),
ty: SInt<2>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x2,
},
@ -475,7 +472,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<4>,
},
maybe_changed: true,
state: 0xf,
last_state: 0xe,
},
@ -485,7 +481,6 @@ Simulation {
index: StatePartIndex<BigSlots>(8),
ty: UInt<4>,
},
maybe_changed: true,
state: 0xa,
last_state: 0x3,
},
@ -495,7 +490,6 @@ Simulation {
index: StatePartIndex<BigSlots>(9),
ty: SInt<2>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x3,
},
@ -505,7 +499,6 @@ Simulation {
index: StatePartIndex<BigSlots>(10),
ty: SInt<2>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x2,
},
@ -515,7 +508,6 @@ Simulation {
index: StatePartIndex<BigSlots>(11),
ty: UInt<4>,
},
maybe_changed: true,
state: 0xf,
last_state: 0xe,
},
@ -525,7 +517,6 @@ Simulation {
index: StatePartIndex<BigSlots>(4),
ty: UInt<4>,
},
maybe_changed: true,
state: 0xa,
last_state: 0x3,
},
@ -535,7 +526,6 @@ Simulation {
index: StatePartIndex<BigSlots>(5),
ty: SInt<2>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x3,
},
@ -545,7 +535,6 @@ Simulation {
index: StatePartIndex<BigSlots>(6),
ty: SInt<2>,
},
maybe_changed: true,
state: 0x2,
last_state: 0x2,
},
@ -555,7 +544,6 @@ Simulation {
index: StatePartIndex<BigSlots>(7),
ty: UInt<4>,
},
maybe_changed: true,
state: 0xf,
last_state: 0xe,
},

15
crates/fayalite/tests/sim/expected/mod1.vcd
View file

@ -6,12 +6,18 @@ $var wire 2 Q2~aG o $end
$var wire 2 DXK'| i2 $end
$var wire 4 cPuix o2 $end
$upscope $end
$scope module child $end
$scope struct child $end
$var wire 4 ($5K7 i $end
$var wire 2 %6Wv" o $end
$var wire 2 +|-AU i2 $end
$var wire 4 Hw?%j o2 $end
$upscope $end
$scope module mod1_child $end
$var wire 4 4}s%= i $end
$var wire 2 }IY?g o $end
$var wire 2 of42K i2 $end
$var wire 4 D9]&= o2 $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
@ -19,6 +25,10 @@ b11 avK(^
b11 Q2~aG
b10 DXK'|
b1110 cPuix
b11 4}s%=
b11 }IY?g
b10 of42K
b1110 D9]&=
b11 ($5K7
b11 %6Wv"
b10 +|-AU
@ -28,6 +38,9 @@ $end
b1010 avK(^
b10 Q2~aG
b1111 cPuix
b1010 4}s%=
b10 }IY?g
b1111 D9]&=
b1010 ($5K7
b10 %6Wv"
b1111 Hw?%j

26
crates/fayalite/tests/sim/expected/phantom_const.txt
View file

@ -185,11 +185,11 @@ Simulation {
},
small_slots: StatePart {
value: [
1 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
1,
0,
0,
0,
0,
],
},
big_slots: StatePart {
@ -197,11 +197,11 @@ Simulation {
0,
0,
0,
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0,
0,
0,
0,
0,
],
},
sim_only_slots: StatePart {
@ -373,7 +373,6 @@ Simulation {
["a","b"],
),
},
maybe_changed: true,
state: PhantomConst,
last_state: PhantomConst,
},
@ -384,7 +383,6 @@ Simulation {
["a","b"],
),
},
maybe_changed: true,
state: PhantomConst,
last_state: PhantomConst,
},
@ -394,7 +392,6 @@ Simulation {
index: StatePartIndex<BigSlots>(0),
ty: UInt<0>,
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -403,7 +400,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -412,7 +408,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -423,7 +418,6 @@ Simulation {
"mem_element",
),
},
maybe_changed: true,
state: PhantomConst,
last_state: PhantomConst,
},

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crates/fayalite/tests/sim/expected/ripple_counter.txt
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@ -314,56 +314,55 @@ Simulation {
src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
width: 1,
},
// at: module-XXXXXXXXXX.rs:7:1
// at: module-XXXXXXXXXX.rs:8:1
3: Copy {
dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:7:1
4: Copy {
dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
4: Copy {
5: Copy {
dest: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
5: Copy {
6: Copy {
dest: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
src: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
},
// at: module-XXXXXXXXXX.rs:9:1
6: Copy {
7: Copy {
dest: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", ty: Clock },
src: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
},
// at: module-XXXXXXXXXX.rs:6:1
7: Copy {
dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:8:1
8: Copy {
dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:9:1
9: Copy {
dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:11:1
10: Copy {
9: Copy {
dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
src: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
11: Copy {
10: Copy {
dest: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
},
12: NotU {
11: NotU {
dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
width: 1,
},
// at: module-XXXXXXXXXX.rs:8:1
12: Copy {
dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:7:1
13: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
@ -384,272 +383,256 @@ Simulation {
dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", ty: Clock },
src: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock },
},
// at: module-XXXXXXXXXX.rs:6:1
17: Copy {
dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:8:1
18: Copy {
dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:9:1
19: Copy {
dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
src: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:11:1
20: Copy {
18: Copy {
dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
21: Copy {
19: Copy {
dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
},
22: NotU {
20: NotU {
dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
width: 1,
},
// at: module-XXXXXXXXXX.rs:8:1
21: Copy {
dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:7:1
23: Copy {
22: Copy {
dest: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
24: Copy {
23: Copy {
dest: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
25: Copy {
24: Copy {
dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
},
// at: module-XXXXXXXXXX.rs:9:1
26: Copy {
25: Copy {
dest: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", ty: Clock },
src: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
},
// at: module-XXXXXXXXXX.rs:6:1
27: Copy {
dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:8:1
28: Copy {
dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
29: Const {
26: Const {
dest: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
value: 0x0,
},
30: Copy {
27: Copy {
dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
src: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
},
31: Copy {
28: Copy {
dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", ty: Clock },
},
32: Copy {
29: Copy {
dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
},
// at: module-XXXXXXXXXX.rs:6:1
33: IsNonZeroDestIsSmall {
30: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
},
34: AndSmall {
31: AndSmall {
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
35: Copy {
32: Copy {
dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
src: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
},
36: Copy {
33: Copy {
dest: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
},
// at: module-XXXXXXXXXX.rs:6:1
37: IsNonZeroDestIsSmall {
34: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
},
38: AndSmall {
35: AndSmall {
dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
39: Copy {
36: Copy {
dest: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
src: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
},
40: Copy {
37: Copy {
dest: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
},
// at: module-XXXXXXXXXX.rs:6:1
41: IsNonZeroDestIsSmall {
38: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
},
42: AndSmall {
39: AndSmall {
dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
43: Copy {
40: Copy {
dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool },
},
44: Shl {
41: Shl {
dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
lhs: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
rhs: 5,
},
45: Copy {
42: Copy {
dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
},
46: Shl {
43: Shl {
dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
lhs: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
rhs: 4,
},
47: Copy {
44: Copy {
dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
},
48: Shl {
45: Shl {
dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
rhs: 3,
},
49: Copy {
46: Copy {
dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
},
50: Shl {
47: Shl {
dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
lhs: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
rhs: 2,
},
51: Copy {
48: Copy {
dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
},
52: Shl {
49: Shl {
dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
lhs: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
rhs: 1,
},
53: Copy {
50: Copy {
dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
},
54: Or {
51: Or {
dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
lhs: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
rhs: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
},
55: Or {
52: Or {
dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
lhs: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
rhs: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
},
56: Or {
53: Or {
dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
lhs: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
rhs: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
},
57: Or {
54: Or {
dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
lhs: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
rhs: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
},
58: Or {
55: Or {
dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
lhs: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
rhs: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
},
// at: module-XXXXXXXXXX.rs:5:1
59: Copy {
56: Copy {
dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", ty: UInt<6> },
src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
},
// at: module-XXXXXXXXXX.rs:6:1
60: BranchIfSmallZero {
target: 62,
57: BranchIfSmallZero {
target: 59,
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
61: Copy {
58: Copy {
dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
},
62: BranchIfSmallZero {
target: 64,
59: BranchIfSmallZero {
target: 61,
value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
63: Copy {
60: Copy {
dest: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
},
64: BranchIfSmallZero {
target: 66,
61: BranchIfSmallZero {
target: 63,
value: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
65: Copy {
62: Copy {
dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
},
66: XorSmallImmediate {
63: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
67: XorSmallImmediate {
64: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
68: XorSmallImmediate {
65: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:1:1
69: Return,
66: Return,
],
..
},
pc: 69,
pc: 66,
memory_write_log: [],
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [
0 (modified),
0 (modified),
1 (modified),
1 (modified),
0 (modified),
0 (modified),
1 (modified),
0 (modified),
0 (modified),
0,
0,
1,
1,
0,
0,
1,
0,
0,
],
},
big_slots: StatePart {
@ -662,56 +645,56 @@ Simulation {
0,
0,
0,
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0 (modified),
0,
1 (modified),
1 (modified),
0 (modified),
0 (modified),
0 (modified),
1 (modified),
0,
0,
0 (modified),
0,
0 (modified),
0,
1 (modified),
0 (modified),
0 (modified),
0 (modified),
1 (modified),
0,
0,
0 (modified),
0,
0 (modified),
0,
1 (modified),
0 (modified),
0 (modified),
0 (modified),
1 (modified),
0,
0,
0 (modified),
0,
0 (modified),
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
1,
0,
0,
0,
1,
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
1,
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
1,
0,
0,
0,
0,
0,
],
},
sim_only_slots: StatePart {
@ -1284,7 +1267,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: false,
state: 0x1,
last_state: 0x1,
},
@ -1294,7 +1276,6 @@ Simulation {
index: StatePartIndex<BigSlots>(1),
ty: UInt<6>,
},
maybe_changed: false,
state: 0x00,
last_state: 0x00,
},
@ -1303,7 +1284,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1312,7 +1292,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(3),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1321,7 +1300,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(4),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1330,7 +1308,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(5),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1339,7 +1316,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(6),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1348,7 +1324,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(7),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1357,7 +1332,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(24),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1366,7 +1340,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(33),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1375,7 +1348,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(34),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1384,7 +1356,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(31),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1393,7 +1364,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(32),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1402,7 +1372,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(36),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1411,7 +1380,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(44),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1420,7 +1388,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(45),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1429,7 +1396,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(42),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1438,7 +1404,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(43),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1447,7 +1412,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(47),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1456,7 +1420,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(55),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1465,7 +1428,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(56),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1474,7 +1436,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(53),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -1483,7 +1444,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(54),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},

276
crates/fayalite/tests/sim/expected/ripple_counter.vcd
View file

File diff suppressed because it is too large Load diff

139
crates/fayalite/tests/sim/expected/shift_register.txt
View file

@ -103,166 +103,147 @@ Simulation {
dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:11:1
// at: module-XXXXXXXXXX.rs:12:1
1: Copy {
dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:12:1
2: Copy {
dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:9:1
3: Copy {
dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
4: Copy {
2: Copy {
dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:7:1
5: Copy {
dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:8:1
6: Copy {
3: Copy {
dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
4: Copy {
dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:5:1
7: IsNonZeroDestIsSmall {
5: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
},
8: IsNonZeroDestIsSmall {
6: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
},
9: AndSmall {
7: AndSmall {
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
10: Copy {
dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
11: Copy {
dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
12: Const {
8: Const {
dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
value: 0x0,
},
// at: module-XXXXXXXXXX.rs:5:1
13: BranchIfSmallZero {
target: 18,
9: BranchIfSmallZero {
target: 14,
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
14: BranchIfSmallNonZero {
target: 17,
10: BranchIfSmallNonZero {
target: 13,
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
15: Copy {
11: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
},
16: Branch {
target: 18,
12: Branch {
target: 14,
},
17: Copy {
13: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:7:1
18: BranchIfSmallZero {
target: 23,
14: BranchIfSmallZero {
target: 19,
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
19: BranchIfSmallNonZero {
target: 22,
15: BranchIfSmallNonZero {
target: 18,
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
20: Copy {
16: Copy {
dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
},
21: Branch {
target: 23,
17: Branch {
target: 19,
},
22: Copy {
18: Copy {
dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:9:1
23: BranchIfSmallZero {
target: 28,
19: BranchIfSmallZero {
target: 24,
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
24: BranchIfSmallNonZero {
target: 27,
20: BranchIfSmallNonZero {
target: 23,
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
25: Copy {
21: Copy {
dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
},
26: Branch {
target: 28,
22: Branch {
target: 24,
},
27: Copy {
23: Copy {
dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:11:1
28: BranchIfSmallZero {
target: 33,
24: BranchIfSmallZero {
target: 29,
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
29: BranchIfSmallNonZero {
target: 32,
25: BranchIfSmallNonZero {
target: 28,
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
30: Copy {
26: Copy {
dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
},
31: Branch {
target: 33,
27: Branch {
target: 29,
},
32: Copy {
28: Copy {
dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:5:1
33: XorSmallImmediate {
29: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:1:1
34: Return,
30: Return,
],
..
},
pc: 34,
pc: 30,
memory_write_log: [],
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [
0 (modified),
0 (modified),
1 (modified),
0 (modified),
0,
0,
1,
0,
],
},
big_slots: StatePart {
@ -272,14 +253,14 @@ Simulation {
0,
0,
0,
0 (modified),
0 (modified),
0,
0 (modified),
0,
0 (modified),
0,
0 (modified),
0,
0,
0,
0,
0,
],
},
sim_only_slots: StatePart {
@ -458,7 +439,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x1,
last_state: 0x0,
},
@ -467,7 +447,6 @@ Simulation {
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -476,7 +455,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -485,7 +463,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(3),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -494,7 +471,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(4),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -503,7 +479,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(7),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -512,7 +487,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(9),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -521,7 +495,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(11),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},

14
crates/fayalite/tests/sim/expected/sim_fork_join.txt
View file

@ -68,12 +68,12 @@ Simulation {
},
big_slots: StatePart {
value: [
0 (modified),
0,
0,
49 (modified),
50 (modified),
50 (modified),
0,
49,
50,
50,
],
},
sim_only_slots: StatePart {
@ -356,7 +356,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -365,7 +364,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -374,7 +372,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -384,7 +381,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x31,
last_state: 0x31,
},
@ -394,7 +390,6 @@ Simulation {
index: StatePartIndex<BigSlots>(4),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x32,
last_state: 0x32,
},
@ -404,7 +399,6 @@ Simulation {
index: StatePartIndex<BigSlots>(5),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x32,
last_state: 0x32,
},

14
crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt
View file

@ -68,12 +68,12 @@ Simulation {
},
big_slots: StatePart {
value: [
0 (modified),
0,
0,
49 (modified),
50 (modified),
50 (modified),
0,
49,
50,
50,
],
},
sim_only_slots: StatePart {
@ -356,7 +356,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -365,7 +364,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -374,7 +372,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -384,7 +381,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x31,
last_state: 0x31,
},
@ -394,7 +390,6 @@ Simulation {
index: StatePartIndex<BigSlots>(4),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x32,
last_state: 0x32,
},
@ -404,7 +399,6 @@ Simulation {
index: StatePartIndex<BigSlots>(5),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x32,
last_state: 0x32,
},

151
crates/fayalite/tests/sim/expected/sim_only_connects.txt
View file

@ -212,55 +212,55 @@ Simulation {
dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
value: 0x0,
},
// at: module-XXXXXXXXXX.rs:17:1
7: Copy {
dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:16:1
8: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:12:1
7: CloneSimOnly {
9: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:13:1
8: BranchIfZero {
target: 10,
10: BranchIfZero {
target: 12,
value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:15:1
9: CloneSimOnly {
11: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:11:1
10: CloneSimOnly {
12: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:13:1
11: BranchIfZero {
target: 13,
13: BranchIfZero {
target: 15,
value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:14:1
12: CloneSimOnly {
14: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:10:1
13: Copy {
15: Copy {
dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock },
src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.clk", ty: Clock },
},
14: Copy {
16: Copy {
dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset },
src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.rst", ty: SyncReset },
},
// at: module-XXXXXXXXXX.rs:9:1
15: Copy {
dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:17:1
16: Copy {
dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
17: Const {
dest: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
@ -280,110 +280,101 @@ Simulation {
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
21: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:16:1
22: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:7:1
23: CloneSimOnly {
21: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(7), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:18:1
24: CloneSimOnly {
22: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:21:1
25: CloneSimOnly {
23: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:19:1
26: CloneSimOnly {
24: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(13), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:7:1
27: CloneSimOnly {
25: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(6), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
28: Copy {
26: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock },
src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock },
},
29: Copy {
27: Copy {
dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.rst", ty: SyncReset },
src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset },
},
// at: module-XXXXXXXXXX.rs:8:1
30: BranchIfSmallZero {
target: 35,
28: BranchIfSmallZero {
target: 33,
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
31: BranchIfSmallNonZero {
target: 34,
29: BranchIfSmallNonZero {
target: 32,
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
32: CloneSimOnly {
30: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
33: Branch {
target: 35,
31: Branch {
target: 33,
},
34: CloneSimOnly {
32: CloneSimOnly {
dest: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
src: StatePartIndex<SimOnlySlots>(10), // ({}) SlotDebugData { name: "", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
},
// at: module-XXXXXXXXXX.rs:9:1
35: BranchIfSmallZero {
target: 40,
33: BranchIfSmallZero {
target: 38,
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
36: BranchIfSmallNonZero {
target: 39,
34: BranchIfSmallNonZero {
target: 37,
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
37: Copy {
35: Copy {
dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
},
38: Branch {
target: 40,
36: Branch {
target: 38,
},
39: Copy {
37: Copy {
dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
src: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:8:1
40: XorSmallImmediate {
38: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:1:1
41: Return,
39: Return,
],
..
},
pc: 41,
pc: 39,
memory_write_log: [],
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [
0 (modified),
0 (modified),
1 (modified),
0 (modified),
0,
0,
1,
0,
],
},
big_slots: StatePart {
@ -392,15 +383,15 @@ Simulation {
0,
1,
0,
1 (modified),
0,
0,
0 (modified),
1 (modified),
0 (modified),
1,
0,
1 (modified),
0,
0,
1,
0,
1,
0,
1,
0,
],
},
@ -443,8 +434,8 @@ Simulation {
},
{
"extra": "value",
} (modified),
{} (modified),
},
{},
{
"bar": "",
"extra": "value",
@ -1252,7 +1243,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1261,7 +1251,6 @@ Simulation {
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1271,7 +1260,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(0),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"extra": "value",
},
@ -1285,7 +1273,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(1),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"extra": "value",
},
@ -1299,7 +1286,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(2),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"bar": "",
"extra": "value",
@ -1317,7 +1303,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(3),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"bar": "baz",
"extra": "value",
@ -1334,7 +1319,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(4),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1343,7 +1327,6 @@ Simulation {
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(5),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1353,7 +1336,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(6),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"extra": "value",
},
@ -1367,7 +1349,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(7),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"bar": "",
"extra": "value",
@ -1384,7 +1365,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1393,7 +1373,6 @@ Simulation {
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(3),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1403,7 +1382,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(4),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"extra": "value",
},
@ -1417,7 +1395,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(5),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"bar": "",
"extra": "value",
@ -1435,7 +1412,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(8),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"extra": "value",
},
@ -1448,7 +1424,6 @@ Simulation {
kind: BigBool {
index: StatePartIndex<BigSlots>(6),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1457,7 +1432,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(12),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1466,7 +1440,6 @@ Simulation {
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(13),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1476,7 +1449,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(13),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"bar": "",
"extra": "value",
@ -1494,7 +1466,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(14),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"bar": "baz",
"extra": "value",
@ -1511,7 +1482,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(10),
},
maybe_changed: true,
state: 0x1,
last_state: 0x1,
},
@ -1520,7 +1490,6 @@ Simulation {
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(11),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -1530,7 +1499,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(11),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"bar": "",
"extra": "value",
@ -1548,7 +1516,6 @@ Simulation {
index: StatePartIndex<SimOnlySlots>(12),
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
},
maybe_changed: true,
state: {
"bar": "baz",
"extra": "value",

64
crates/fayalite/tests/sim/expected/sim_only_connects.vcd
View file

@ -8,7 +8,7 @@ $var string 1 g:xf? inp $end
$var string 1 [OKKg out1 $end
$var string 1 9pB-> out2 $end
$var string 1 8(7-4 out3 $end
$scope module helper1 $end
$scope struct helper1 $end
$scope struct cd $end
$var wire 1 $Kwp\ clk $end
$var wire 1 nmVq' rst $end
@ -16,9 +16,17 @@ $upscope $end
$var string 1 qS)@z inp $end
$var string 1 ~je// out $end
$upscope $end
$scope module sim_only_connects_helper $end
$scope struct cd $end
$var wire 1 %uCn6 clk $end
$var wire 1 Apu`K rst $end
$upscope $end
$var string 1 $U*lA inp $end
$var string 1 !prwC out $end
$upscope $end
$var string 1 CyjVm delay1 $end
$var reg 1 z~g{\ delay1_empty $end
$scope module helper2 $end
$scope struct helper2 $end
$scope struct cd $end
$var wire 1 Ph.=# clk $end
$var wire 1 !GXK\ rst $end
@ -26,6 +34,14 @@ $upscope $end
$var string 1 /YVv: inp $end
$var string 1 Kk*{# out $end
$upscope $end
$scope module sim_only_connects_helper_2 $end
$scope struct cd $end
$var wire 1 %uCn6" clk $end
$var wire 1 Apu`K" rst $end
$upscope $end
$var string 1 $U*lA" inp $end
$var string 1 !prwC" out $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
@ -35,12 +51,20 @@ s{\"extra\":\x20\"value\"} g:xf?
s{} [OKKg
s{} 9pB->
s{} 8(7-4
0%uCn6
1Apu`K
s{} $U*lA
s{} !prwC
0$Kwp\
1nmVq'
s{} qS)@z
s{} ~je//
s{} CyjVm
0z~g{\
0%uCn6"
1Apu`K"
s{} $U*lA"
s{} !prwC"
0Ph.=#
1!GXK\
s{} /YVv:
@ -49,74 +73,110 @@ $end
#1000000
1tq:(w
s{\"extra\":\x20\"value\"} [OKKg
1%uCn6
s{\"extra\":\x20\"value\"} $U*lA
1$Kwp\
s{\"extra\":\x20\"value\"} qS)@z
1z~g{\
1%uCn6"
1Ph.=#
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 9pB->
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} !prwC
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} ~je//
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} $U*lA"
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} /YVv:
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8(7-4
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} !prwC"
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} Kk*{#
#2000000
0tq:(w
0FVlgb
0%uCn6
0Apu`K
0$Kwp\
0nmVq'
0%uCn6"
0Apu`K"
0Ph.=#
0!GXK\
#3000000
1tq:(w
1%uCn6
1$Kwp\
s{\"extra\":\x20\"value\"} CyjVm
0z~g{\
1%uCn6"
1Ph.=#
#4000000
0tq:(w
0%uCn6
0$Kwp\
0%uCn6"
0Ph.=#
#5000000
1tq:(w
1%uCn6
1$Kwp\
1%uCn6"
1Ph.=#
#6000000
0tq:(w
0%uCn6
0$Kwp\
0%uCn6"
0Ph.=#
#7000000
1tq:(w
1%uCn6
1$Kwp\
1%uCn6"
1Ph.=#
#8000000
0tq:(w
0%uCn6
0$Kwp\
0%uCn6"
0Ph.=#
#9000000
1tq:(w
1%uCn6
1$Kwp\
1%uCn6"
1Ph.=#
#10000000
0tq:(w
0%uCn6
0$Kwp\
0%uCn6"
0Ph.=#
#11000000
1tq:(w
1%uCn6
1$Kwp\
1%uCn6"
1Ph.=#
#12000000
0tq:(w
0%uCn6
0$Kwp\
0%uCn6"
0Ph.=#
#13000000
1tq:(w
1%uCn6
1$Kwp\
1%uCn6"
1Ph.=#
#14000000
0tq:(w
0%uCn6
0$Kwp\
0%uCn6"
0Ph.=#
#15000000
1tq:(w
1%uCn6
1$Kwp\
1%uCn6"
1Ph.=#
#16000000

122
crates/fayalite/tests/sim/expected/sim_read_past.txt
View file

@ -517,67 +517,67 @@ Simulation {
},
small_slots: StatePart {
value: [
1 (modified),
0 (modified),
0 (modified),
1 (modified),
0 (modified),
0 (modified),
1 (modified),
0 (modified),
0 (modified),
1,
0,
0,
1,
0,
0,
1,
0,
0,
],
},
big_slots: StatePart {
value: [
0 (modified),
0,
0,
49 (modified),
50 (modified),
50 (modified),
0 (modified),
1 (modified),
0 (modified),
49 (modified),
49 (modified),
50 (modified),
1 (modified),
0 (modified),
0 (modified),
48 (modified),
49 (modified),
49 (modified),
0 (modified),
0 (modified),
1 (modified),
48 (modified),
49 (modified),
48 (modified),
0 (modified),
1 (modified),
0 (modified),
49 (modified),
49 (modified),
50 (modified),
0 (modified),
0 (modified),
1 (modified),
49 (modified),
49 (modified),
49 (modified),
0 (modified),
0 (modified),
1 (modified),
49 (modified),
50 (modified),
50 (modified),
0 (modified),
1 (modified),
0 (modified),
49 (modified),
49 (modified),
50 (modified),
0,
49,
50,
50,
0,
1,
0,
49,
49,
50,
1,
0,
0,
48,
49,
49,
0,
0,
1,
48,
49,
48,
0,
1,
0,
49,
49,
50,
0,
0,
1,
49,
49,
49,
0,
0,
1,
49,
50,
50,
0,
1,
0,
49,
49,
50,
],
},
sim_only_slots: StatePart {
@ -9500,7 +9500,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -9509,7 +9508,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -9518,7 +9516,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(2),
},
maybe_changed: true,
state: 0x0,
last_state: 0x1,
},
@ -9528,7 +9525,6 @@ Simulation {
index: StatePartIndex<BigSlots>(3),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x31,
last_state: 0x31,
},
@ -9538,7 +9534,6 @@ Simulation {
index: StatePartIndex<BigSlots>(4),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x32,
last_state: 0x32,
},
@ -9548,7 +9543,6 @@ Simulation {
index: StatePartIndex<BigSlots>(5),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x32,
last_state: 0x32,
},
@ -9557,7 +9551,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(6),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -9566,7 +9559,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(7),
},
maybe_changed: false,
state: 0x1,
last_state: 0x1,
},
@ -9575,7 +9567,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(8),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -9585,7 +9576,6 @@ Simulation {
index: StatePartIndex<BigSlots>(9),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x31,
last_state: 0x31,
},
@ -9595,7 +9585,6 @@ Simulation {
index: StatePartIndex<BigSlots>(10),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x31,
last_state: 0x31,
},
@ -9605,7 +9594,6 @@ Simulation {
index: StatePartIndex<BigSlots>(11),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x32,
last_state: 0x32,
},

7
crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt
View file

@ -56,8 +56,8 @@ Simulation {
},
big_slots: StatePart {
value: [
0 (modified),
0 (modified),
0,
0,
3,
],
},
@ -310,7 +310,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -319,7 +318,6 @@ Simulation {
kind: BigAsyncReset {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -329,7 +327,6 @@ Simulation {
index: StatePartIndex<BigSlots>(2),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x03,
last_state: 0x03,
},

7
crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt
View file

@ -56,8 +56,8 @@ Simulation {
},
big_slots: StatePart {
value: [
0 (modified),
0 (modified),
0,
0,
3,
],
},
@ -310,7 +310,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -319,7 +318,6 @@ Simulation {
kind: BigAsyncReset {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -329,7 +327,6 @@ Simulation {
index: StatePartIndex<BigSlots>(2),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x03,
last_state: 0x03,
},

5
crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt
View file

@ -56,7 +56,7 @@ Simulation {
},
big_slots: StatePart {
value: [
0 (modified),
0,
0,
3,
],
@ -310,7 +310,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -319,7 +318,6 @@ Simulation {
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -329,7 +327,6 @@ Simulation {
index: StatePartIndex<BigSlots>(2),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x03,
last_state: 0x03,
},

5
crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt
View file

@ -56,7 +56,7 @@ Simulation {
},
big_slots: StatePart {
value: [
0 (modified),
0,
0,
3,
],
@ -310,7 +310,6 @@ Simulation {
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
maybe_changed: true,
state: 0x0,
last_state: 0x0,
},
@ -319,7 +318,6 @@ Simulation {
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(1),
},
maybe_changed: false,
state: 0x0,
last_state: 0x0,
},
@ -329,7 +327,6 @@ Simulation {
index: StatePartIndex<BigSlots>(2),
ty: UInt<8>,
},
maybe_changed: false,
state: 0x03,
last_state: 0x03,
},

18
crates/fayalite/tests/ui/simvalue_is_not_internable.stderr
View file

@ -75,12 +75,12 @@ note: required because it appears within the type `Vec<DynSimOnlyValue>`
note: required because it appears within the type `OpaqueSimValue`
--> src/ty.rs
|
761 | pub struct OpaqueSimValue {
734 | pub struct OpaqueSimValue {
| ^^^^^^^^^^^^^^
note: required because it appears within the type `value::SimValueInner<()>`
--> src/sim/value.rs
|
52 | struct SimValueInner<T: Type> {
51 | struct SimValueInner<T: Type> {
| ^^^^^^^^^^^^^
note: required because it appears within the type `UnsafeCell<value::SimValueInner<()>>`
--> $RUST/core/src/cell.rs
@ -95,7 +95,7 @@ note: required because it appears within the type `util::alternating_cell::Alter
note: required because it appears within the type `fayalite::prelude::SimValue<()>`
--> src/sim/value.rs
|
161 | pub struct SimValue<T: Type> {
160 | pub struct SimValue<T: Type> {
| ^^^^^^^^
note: required by a bound in `fayalite::intern::Interned`
--> src/intern.rs
@ -214,12 +214,12 @@ note: required because it appears within the type `Vec<DynSimOnlyValue>`
note: required because it appears within the type `OpaqueSimValue`
--> src/ty.rs
|
761 | pub struct OpaqueSimValue {
734 | pub struct OpaqueSimValue {
| ^^^^^^^^^^^^^^
note: required because it appears within the type `value::SimValueInner<()>`
--> src/sim/value.rs
|
52 | struct SimValueInner<T: Type> {
51 | struct SimValueInner<T: Type> {
| ^^^^^^^^^^^^^
note: required because it appears within the type `UnsafeCell<value::SimValueInner<()>>`
--> $RUST/core/src/cell.rs
@ -234,7 +234,7 @@ note: required because it appears within the type `util::alternating_cell::Alter
note: required because it appears within the type `fayalite::prelude::SimValue<()>`
--> src/sim/value.rs
|
161 | pub struct SimValue<T: Type> {
160 | pub struct SimValue<T: Type> {
| ^^^^^^^^
note: required by a bound in `intern_sized`
--> src/intern.rs
@ -326,12 +326,12 @@ note: required because it appears within the type `Vec<DynSimOnlyValue>`
note: required because it appears within the type `OpaqueSimValue`
--> src/ty.rs
|
761 | pub struct OpaqueSimValue {
734 | pub struct OpaqueSimValue {
| ^^^^^^^^^^^^^^
note: required because it appears within the type `value::SimValueInner<()>`
--> src/sim/value.rs
|
52 | struct SimValueInner<T: Type> {
51 | struct SimValueInner<T: Type> {
| ^^^^^^^^^^^^^
note: required because it appears within the type `UnsafeCell<value::SimValueInner<()>>`
--> $RUST/core/src/cell.rs
@ -346,7 +346,7 @@ note: required because it appears within the type `util::alternating_cell::Alter
note: required because it appears within the type `fayalite::prelude::SimValue<()>`
--> src/sim/value.rs
|
161 | pub struct SimValue<T: Type> {
160 | pub struct SimValue<T: Type> {
| ^^^^^^^^
note: required by a bound in `fayalite::intern::Interned`
--> src/intern.rs

8
rocq-demo/.gitignore vendored
View file

@ -1,8 +0,0 @@
# SPDX-License-Identifier: LGPL-3.0-or-later
# See Notices.txt for copyright information
.CoqMakefile.d
*.aux
CoqMakefile
CoqMakefile.conf
*.glob
*.vo*

31
rocq-demo/Makefile
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@ -1,31 +0,0 @@
# SPDX-License-Identifier: LGPL-3.0-or-later
# See Notices.txt for copyright information
#
# Example Makefile wrapper as given on the Rocq documentation
# https://rocq-prover.org/doc/V9.1.0/refman/practical-tools/utilities.html#building-a-rocq-project-with-rocq-makefile-details
# KNOWNTARGETS will not be passed along to CoqMakefile
KNOWNTARGETS := CoqMakefile
# KNOWNFILES will not get implicit targets from the final rule, and so
# depending on them won't invoke the submake
# Warning: These files get declared as PHONY, so any targets depending
# on them always get rebuilt
KNOWNFILES := Makefile _CoqProject
.DEFAULT_GOAL := invoke-coq-makefile
CoqMakefile: Makefile _CoqProject
$(COQBIN)rocq makefile -f _CoqProject -o CoqMakefile
invoke-coq-makefile: CoqMakefile
$(MAKE) --no-print-directory -f CoqMakefile $(filter-out $(KNOWNTARGETS),$(MAKECMDGOALS))
.PHONY: invoke-coq-makefile $(KNOWNFILES)
####################################################################
## Your targets here ##
####################################################################
# This should be the last rule, to handle any targets not declared above
%: invoke-coq-makefile
@true

5
rocq-demo/_CoqProject
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@ -1,5 +0,0 @@
# SPDX-License-Identifier: LGPL-3.0-or-later
# See Notices.txt for copyright information
-Q . RocqDemo
.

2
scripts/check-copyright.sh
View file

@ -50,7 +50,7 @@ function main()
/crates/fayalite/tests/ui/*.stderr|/crates/fayalite/tests/sim/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.txt)
# file that can't contain copyright header
;;
/.forgejo/workflows/*.yml|*/.gitignore|*.toml|*/Makefile|*/_CoqProject)
/.forgejo/workflows/*.yml|*/.gitignore|*.toml)
check_file "$file" "${POUND_HEADER[@]}"
;;
*.md)