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fayalite/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt

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Simulation {
state: State {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 3,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst",
ty: SyncReset,
},
SlotDebugData {
name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::out",
ty: UInt<8>,
},
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
insns: [
// at: module-XXXXXXXXXX.rs:1:1
0: Return,
],
..
},
pc: 0,
memory_write_log: [],
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [],
},
big_slots: StatePart {
value: [
0,
0,
3,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::sim_resettable_counter,
instantiated: Module {
name: sim_resettable_counter,
..
},
},
main_module: SimulationModuleState {
base_targets: [
Instance {
name: <simulator>::sim_resettable_counter,
instantiated: Module {
name: sim_resettable_counter,
..
},
}.cd,
Instance {
name: <simulator>::sim_resettable_counter,
instantiated: Module {
name: sim_resettable_counter,
..
},
}.out,
],
uninitialized_ios: {},
io_targets: {
Instance {
name: <simulator>::sim_resettable_counter,
instantiated: Module {
name: sim_resettable_counter,
..
},
}.cd,
Instance {
name: <simulator>::sim_resettable_counter,
instantiated: Module {
name: sim_resettable_counter,
..
},
}.cd.clk,
Instance {
name: <simulator>::sim_resettable_counter,
instantiated: Module {
name: sim_resettable_counter,
..
},
}.cd.rst,
Instance {
name: <simulator>::sim_resettable_counter,
instantiated: Module {
name: sim_resettable_counter,
..
},
}.out,
},
did_initial_settle: true,
clocks_for_past: {},
},
extern_modules: [
SimulationExternModuleState {
module_state: SimulationModuleState {
base_targets: [
ModuleIO {
name: sim_resettable_counter::cd,
is_input: true,
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
},
..
},
ModuleIO {
name: sim_resettable_counter::out,
is_input: false,
ty: UInt<8>,
..
},
],
uninitialized_ios: {},
io_targets: {
ModuleIO {
name: sim_resettable_counter::cd,
is_input: true,
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
},
..
},
ModuleIO {
name: sim_resettable_counter::cd,
is_input: true,
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
},
..
}.clk,
ModuleIO {
name: sim_resettable_counter::cd,
is_input: true,
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
},
..
}.rst,
ModuleIO {
name: sim_resettable_counter::out,
is_input: false,
ty: UInt<8>,
..
},
},
did_initial_settle: true,
clocks_for_past: {},
},
sim: ExternModuleSimulation {
generator: SimGeneratorFn {
args: (
ModuleIO {
name: sim_resettable_counter::cd,
is_input: true,
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
},
..
},
ModuleIO {
name: sim_resettable_counter::out,
is_input: false,
ty: UInt<8>,
..
},
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: sim_resettable_counter::cd,
is_input: true,
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
},
..
}: ModuleIO {
name: sim_resettable_counter::cd,
is_input: true,
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
},
..
},
ModuleIO {
name: sim_resettable_counter::out,
is_input: false,
ty: UInt<8>,
..
}: ModuleIO {
name: sim_resettable_counter::out,
is_input: false,
ty: UInt<8>,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX.rs:4:1,
),
},
running_generator: Some(
...,
),
},
],
trace_decls: TraceModule {
name: "sim_resettable_counter",
children: [
TraceModuleIO {
name: "cd",
child: TraceBundle {
name: "cd",
fields: [
TraceClock {
location: TraceScalarId(0),
name: "clk",
flow: Source,
},
TraceSyncReset {
location: TraceScalarId(1),
name: "rst",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
},
flow: Source,
},
ty: Bundle {
/* offset = 0 */
clk: Clock,
/* offset = 1 */
rst: SyncReset,
},
flow: Source,
},
TraceModuleIO {
name: "out",
child: TraceUInt {
location: TraceScalarId(2),
name: "out",
ty: UInt<8>,
flow: Sink,
},
ty: UInt<8>,
flow: Sink,
},
],
},
traces: [
SimTrace {
id: TraceScalarId(0),
kind: BigClock {
index: StatePartIndex<BigSlots>(0),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(1),
kind: BigSyncReset {
index: StatePartIndex<BigSlots>(1),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(2),
kind: BigUInt {
index: StatePartIndex<BigSlots>(2),
ty: UInt<8>,
},
state: 0x03,
last_state: 0x03,
},
],
trace_memories: {},
trace_writers: [
Running(
VcdWriter {
finished_init: true,
timescale: 1 ps,
..
},
),
],
clocks_triggered: [],
event_queue: EventQueue(EventQueueData {
instant: 20 μs,
events: {},
}),
waiting_sensitivity_sets_by_address: {
SensitivitySet {
id: 42,
values: {
CompiledValue {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk",
ty: Clock,
},
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
}: OpaqueSimValue {
bits: 0x0_u1,
sim_only_values: [],
},
},
changed: Cell {
value: false,
},
..
},
SensitivitySet {
id: 43,
values: {
CompiledValue {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk",
ty: Clock,
},
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
}: OpaqueSimValue {
bits: 0x0_u1,
sim_only_values: [],
},
},
changed: Cell {
value: false,
},
..
},
},
waiting_sensitivity_sets_by_compiled_value: {
CompiledValue {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk",
ty: Clock,
},
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
}: (
OpaqueSimValue {
bits: 0x0_u1,
sim_only_values: [],
},
{
SensitivitySet {
id: 42,
..
},
SensitivitySet {
id: 43,
..
},
},
),
},
..
}
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