4 commits

Author	SHA1	Message	Date
Jacob Lifshay	d4d9706798	reimplement fayalite::formal and add support to the simulator ... Add support to the simulator for running hdl asserts/assumes and being able to write to the formal global clock/reset and all any/all_const/seq that are used. This allows you to use the exact same HDL code for running a simulation and for running a formal proof.	2026-06-05 00:56:24 -07:00
Jacob Lifshay	26224abe1c	sim: properly update all VCD wires when they share simulation state	2026-05-05 21:12:00 -07:00
Jacob Lifshay	402f457c68	sim: Speed up updating traces by tracking which traces are written to	2026-04-30 19:12:20 -07:00
Jacob Lifshay	2aa41137d4	add simulator tests for queue()	2026-03-24 23:30:15 -07:00