8 commits

Author	SHA1	Message	Date
Jacob Lifshay	5c594cbb68	reimplement fayalite::formal and add support to the simulator ... Add support to the simulator for running hdl asserts/assumes and being able to write to the formal global clock/reset and all any/all_const/seq that are used. This allows you to use the exact same HDL code for running a simulation and for running a formal proof.	2026-06-05 00:46:30 -07:00
Jacob Lifshay	26224abe1c	sim: properly update all VCD wires when they share simulation state	2026-05-05 21:12:00 -07:00
Jacob Lifshay	402f457c68	sim: Speed up updating traces by tracking which traces are written to	2026-04-30 19:12:20 -07:00
Jacob Lifshay	df020e9c9b	add ExternModuleSimulatorState::read_past() and more output when simulator trace is enabled	2025-11-12 22:31:45 -08:00
Jacob Lifshay	c11a1743f9	add sim.fork_join() and fix Simulator to handle running futures with arbitrary wakers	2025-10-30 21:16:05 -07:00
Jacob Lifshay	db9b1c202c	add simulator support for sim-only values	2025-09-08 22:19:43 -07:00
Jacob Lifshay	d1bd176b28	implement simulation of extern modules	2025-03-21 01:47:14 -07:00
Jacob Lifshay	e3a2ccd41c	properly handle duplicate names in vcd	2025-01-09 22:52:22 -08:00