14 commits

Author	SHA1	Message	Date
Jacob Lifshay	e4b886b9b4	reimplement fayalite::formal and add support to the simulator	2026-06-05 00:26:54 -07:00
Jacob Lifshay	26224abe1c	sim: properly update all VCD wires when they share simulation state	2026-05-05 21:12:00 -07:00
Jacob Lifshay	402f457c68	sim: Speed up updating traces by tracking which traces are written to	2026-04-30 19:12:20 -07:00
Jacob Lifshay	a8a541b357	sim/compiler: fix registers so they properly retain their old value when not written	2026-03-24 23:26:47 -07:00
Jacob Lifshay	df020e9c9b	add ExternModuleSimulatorState::read_past() and more output when simulator trace is enabled	2025-11-12 22:31:45 -08:00
Jacob Lifshay	c11a1743f9	add sim.fork_join() and fix Simulator to handle running futures with arbitrary wakers	2025-10-30 21:16:05 -07:00
Jacob Lifshay	db9b1c202c	add simulator support for sim-only values	2025-09-08 22:19:43 -07:00
Jacob Lifshay	d1bd176b28	implement simulation of extern modules	2025-03-21 01:47:14 -07:00
Jacob Lifshay	903ca1bf30	sim: simple memory test works!	2024-12-12 19:47:57 -08:00
Jacob Lifshay	8d030ac65d	sim/interpreter: add addresses to instruction listing	2024-12-12 16:25:38 -08:00
Jacob Lifshay	562c479b62	sim/interpreter: fix StatePartLayout name in debug output	2024-12-12 15:06:17 -08:00
Jacob Lifshay	393f78a14d	sim: add WIP memory test	2024-12-11 23:28:15 -08:00
Jacob Lifshay	3ed7827485	sim: WIP adding memory support	2024-12-05 21:35:23 -08:00
Jacob Lifshay	259bee39c2	tests/sim: split expected output text into separate files	2024-12-05 18:17:13 -08:00