22 commits

Author	SHA1	Message	Date
Jacob Lifshay	7dc4417874	add test_many_memories so we catch if memories are iterated in an inconsistent order like in 838bd469ce	2025-10-24 01:40:30 -07:00
Jacob Lifshay	db9b1c202c	add simulator support for sim-only values	2025-09-08 22:19:43 -07:00
Jacob Lifshay	c4b6a0fee6	add support for #[hdl(sim)] enum_ty.Variant(value) and #[hdl(sim)] EnumTy::Variant(value) and non-sim variants too	2025-04-01 22:16:47 -07:00
Jacob Lifshay	5028401a5a	change SimValue to contain and deref to a value and not just contain bits	2025-03-27 23:44:36 -07:00
Jacob Lifshay	fdc73b5f3b	add ripple counter test to test simulating alternating circuits and extern modules	2025-03-25 18:56:26 -07:00
Jacob Lifshay	a115585d5a	simulator: allow external module generators to wait for value changes and/or clock edges	2025-03-25 18:26:48 -07:00
Jacob Lifshay	ab9ff4f2db	simplify setting an extern module simulation	2025-03-21 17:08:29 -07:00
Jacob Lifshay	d1bd176b28	implement simulation of extern modules	2025-03-21 01:47:14 -07:00
Jacob Lifshay	d4ea826051	sim: fix "label address not set" bug when the last Assignment is conditional	2025-01-15 19:04:40 -08:00
Jacob Lifshay	404a2ee043	tests/sim: add test_array_rw	2025-01-12 21:38:59 -08:00
Jacob Lifshay	e3a2ccd41c	properly handle duplicate names in vcd	2025-01-09 22:52:22 -08:00
Jacob Lifshay	21c73051ec	sim: add SimValue and reading/writing more than just a scalar	2024-12-18 01:39:35 -08:00
Jacob Lifshay	2af38de900	add more memory tests	2024-12-13 15:04:48 -08:00
Jacob Lifshay	c756aeec70	tests/sim: add test for memory rw port	2024-12-12 20:50:41 -08:00
Jacob Lifshay	903ca1bf30	sim: simple memory test works!	2024-12-12 19:47:57 -08:00
Jacob Lifshay	8d030ac65d	sim/interpreter: add addresses to instruction listing	2024-12-12 16:25:38 -08:00
Jacob Lifshay	562c479b62	sim/interpreter: fix StatePartLayout name in debug output	2024-12-12 15:06:17 -08:00
Jacob Lifshay	393f78a14d	sim: add WIP memory test	2024-12-11 23:28:15 -08:00
Jacob Lifshay	8616ee4737	tests/sim: test_enums works!	2024-12-11 00:01:04 -08:00
Jacob Lifshay	ca759168ff	tests/sim: add WIP test for enums	2024-12-10 23:37:26 -08:00
Jacob Lifshay	3ed7827485	sim: WIP adding memory support	2024-12-05 21:35:23 -08:00
Jacob Lifshay	259bee39c2	tests/sim: split expected output text into separate files	2024-12-05 18:17:13 -08:00