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add simulator support for sim-only values

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This commit is contained in:
Jacob Lifshay 2025-09-01 04:46:24 -07:00
parent d3dd66cbf0
commit db9b1c202c
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
52 changed files with 5441 additions and 819 deletions
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9
crates/fayalite/tests/sim/expected/array_rw.txt
View file

@ -239,6 +239,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -480,6 +486,9 @@ Simulation {
255,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::array_rw,

9
crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
View file

@ -30,6 +30,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -84,6 +90,9 @@ Simulation {
0,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::conditional_assignment_last,

9
crates/fayalite/tests/sim/expected/connect_const.txt
View file

@ -22,6 +22,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -60,6 +66,9 @@ Simulation {
5,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::connect_const,

9
crates/fayalite/tests/sim/expected/connect_const_reset.txt
View file

@ -34,6 +34,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -89,6 +95,9 @@ Simulation {
1,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::connect_const_reset,

9
crates/fayalite/tests/sim/expected/counter_async.txt
View file

@ -71,6 +71,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -195,6 +201,9 @@ Simulation {
4,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::counter,

9
crates/fayalite/tests/sim/expected/counter_sync.txt
View file

@ -67,6 +67,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -176,6 +182,9 @@ Simulation {
4,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::counter,

9
crates/fayalite/tests/sim/expected/duplicate_names.txt
View file

@ -30,6 +30,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -80,6 +86,9 @@ Simulation {
6,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::duplicate_names,

9
crates/fayalite/tests/sim/expected/enums.txt
View file

@ -529,6 +529,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -1304,6 +1310,9 @@ Simulation {
15,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::enums,

33
crates/fayalite/tests/sim/expected/extern_module.txt
View file

@ -22,6 +22,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -50,6 +56,9 @@ Simulation {
1,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::extern_module,
@ -146,6 +155,30 @@ Simulation {
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: extern_module::i,
is_input: true,
ty: Bool,
..
}: ModuleIO {
name: extern_module::i,
is_input: true,
ty: Bool,
..
},
ModuleIO {
name: extern_module::o,
is_input: false,
ty: Bool,
..
}: ModuleIO {
name: extern_module::o,
is_input: false,
ty: Bool,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX.rs:4:1,
),

52
crates/fayalite/tests/sim/expected/extern_module2.txt
View file

@ -26,6 +26,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -55,6 +61,9 @@ Simulation {
101,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::extern_module2,
@ -183,6 +192,41 @@ Simulation {
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: extern_module2::clk,
is_input: true,
ty: Clock,
..
}: ModuleIO {
name: extern_module2::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: extern_module2::en,
is_input: true,
ty: Bool,
..
}: ModuleIO {
name: extern_module2::en,
is_input: true,
ty: Bool,
..
},
ModuleIO {
name: extern_module2::o,
is_input: false,
ty: UInt<8>,
..
}: ModuleIO {
name: extern_module2::o,
is_input: false,
ty: UInt<8>,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX.rs:5:1,
),
@ -211,12 +255,19 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
},
@ -224,6 +275,7 @@ Simulation {
ty: Clock,
value: OpaqueSimValue {
bits: 0x1_u1,
sim_only_values: [],
},
},
},

9
crates/fayalite/tests/sim/expected/memories.txt
View file

@ -175,6 +175,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 1,
@ -562,6 +568,9 @@ Simulation {
1,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::memories,

9
crates/fayalite/tests/sim/expected/memories2.txt
View file

@ -224,6 +224,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 1,
@ -590,6 +596,9 @@ Simulation {
1,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::memories2,

9
crates/fayalite/tests/sim/expected/memories3.txt
View file

@ -503,6 +503,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 1,
@ -1478,6 +1484,9 @@ Simulation {
0,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::memories3,

9
crates/fayalite/tests/sim/expected/mod1.txt
View file

@ -82,6 +82,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -208,6 +214,9 @@ Simulation {
15,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::mod1,

105
crates/fayalite/tests/sim/expected/ripple_counter.txt
View file

@ -283,6 +283,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -691,6 +697,9 @@ Simulation {
0,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::ripple_counter,
@ -787,6 +796,30 @@ Simulation {
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
}: ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
}: ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX-2.rs:4:1,
),
@ -815,12 +848,19 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 3, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 33, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
},
@ -828,6 +868,7 @@ Simulation {
ty: Clock,
value: OpaqueSimValue {
bits: 0x0_u1,
sim_only_values: [],
},
},
},
@ -884,6 +925,30 @@ Simulation {
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
}: ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
}: ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX-2.rs:4:1,
),
@ -912,12 +977,19 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 6, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 44, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
},
@ -925,6 +997,7 @@ Simulation {
ty: Clock,
value: OpaqueSimValue {
bits: 0x0_u1,
sim_only_values: [],
},
},
},
@ -981,6 +1054,30 @@ Simulation {
),
f: ...,
},
sim_io_to_generator_map: {
ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
}: ModuleIO {
name: sw_reg::clk,
is_input: true,
ty: Clock,
..
},
ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
}: ModuleIO {
name: sw_reg::o,
is_input: false,
ty: Bool,
..
},
},
source_location: SourceLocation(
module-XXXXXXXXXX-2.rs:4:1,
),
@ -1009,12 +1106,19 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
body: Scalar,
},
range: TypeIndexRange {
small_slots: StatePartIndexRange<SmallSlots> { start: 9, len: 0 },
big_slots: StatePartIndexRange<BigSlots> { start: 55, len: 1 },
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
},
write: None,
},
@ -1022,6 +1126,7 @@ Simulation {
ty: Clock,
value: OpaqueSimValue {
bits: 0x0_u1,
sim_only_values: [],
},
},
},

9
crates/fayalite/tests/sim/expected/shift_register.txt
View file

@ -83,6 +83,12 @@ Simulation {
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
@ -257,6 +263,9 @@ Simulation {
0,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::shift_register,

1636
crates/fayalite/tests/sim/expected/sim_only_connects.txt Normal file
View file

File diff suppressed because it is too large Load diff

185
crates/fayalite/tests/sim/expected/sim_only_connects.vcd Normal file
View file

@ -0,0 +1,185 @@
$timescale 1 ps $end
$scope module sim_only_connects $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$upscope $end
$var string 1 # inp $end
$var string 1 $ out1 $end
$var string 1 % out2 $end
$var string 1 & out3 $end
$scope struct helper1 $end
$scope struct cd $end
$var wire 1 + clk $end
$var wire 1 , rst $end
$upscope $end
$var string 1 - inp $end
$var string 1 . out $end
$upscope $end
$scope module sim_only_connects_helper $end
$scope struct cd $end
$var wire 1 ' clk $end
$var wire 1 ( rst $end
$upscope $end
$var string 1 ) inp $end
$var string 1 * out $end
$upscope $end
$var string 1 / delay1 $end
$var reg 1 0 delay1_empty $end
$scope struct helper2 $end
$scope struct cd $end
$var wire 1 5 clk $end
$var wire 1 6 rst $end
$upscope $end
$var string 1 7 inp $end
$var string 1 8 out $end
$upscope $end
$scope module sim_only_connects_helper_2 $end
$scope struct cd $end
$var wire 1 1 clk $end
$var wire 1 2 rst $end
$upscope $end
$var string 1 3 inp $end
$var string 1 4 out $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
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$end
#1000000
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s{\"extra\":\x20\"value\"} -
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s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 4
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} %
s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} &
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} .
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 3
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 7
s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 8
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s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} &
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8
#4000000
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