forked from libre-chip/fayalite
1636 lines
No EOL
77 KiB
Text
1636 lines
No EOL
77 KiB
Text
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 4,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 14,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.rst",
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ty: SyncReset,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst",
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ty: SyncReset,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.rst",
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ty: SyncReset,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.cd.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.cd.rst",
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ty: SyncReset,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::cd.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::cd.rst",
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ty: SyncReset,
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},
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],
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..
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},
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sim_only_slots: StatePartLayout<SimOnlySlots> {
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len: 15,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out3",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::inp",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::out",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.out",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::inp",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::out",
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ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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},
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],
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layout_data: [
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
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],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:20:1
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0: Copy {
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dest: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.cd.clk", ty: Clock },
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src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.clk", ty: Clock },
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},
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1: Copy {
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dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.cd.rst", ty: SyncReset },
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src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.rst", ty: SyncReset },
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},
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// at: module-XXXXXXXXXX.rs:19:1
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2: CloneSimOnly {
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dest: StatePartIndex<SimOnlySlots>(12), // ({"bar": "baz", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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src: StatePartIndex<SimOnlySlots>(14), // ({"bar": "baz", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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},
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// at: module-XXXXXXXXXX.rs:22:1
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3: CloneSimOnly {
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dest: StatePartIndex<SimOnlySlots>(3), // ({"bar": "baz", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out3", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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src: StatePartIndex<SimOnlySlots>(12), // ({"bar": "baz", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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},
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// at: module-XXXXXXXXXX.rs:19:1
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4: Copy {
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dest: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock },
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src: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.cd.clk", ty: Clock },
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},
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5: Copy {
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dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::cd.rst", ty: SyncReset },
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src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.cd.rst", ty: SyncReset },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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6: Const {
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dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
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value: 0x0,
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},
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// at: module-XXXXXXXXXX.rs:17:1
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7: Copy {
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dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
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src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:16:1
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8: CloneSimOnly {
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dest: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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},
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// at: module-XXXXXXXXXX.rs:12:1
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9: CloneSimOnly {
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dest: StatePartIndex<SimOnlySlots>(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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},
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// at: module-XXXXXXXXXX.rs:13:1
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10: BranchIfZero {
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target: 12,
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value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:15:1
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11: CloneSimOnly {
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dest: StatePartIndex<SimOnlySlots>(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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},
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// at: module-XXXXXXXXXX.rs:11:1
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12: CloneSimOnly {
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dest: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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src: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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},
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// at: module-XXXXXXXXXX.rs:13:1
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13: BranchIfZero {
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target: 15,
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value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:14:1
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14: CloneSimOnly {
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dest: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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src: StatePartIndex<SimOnlySlots>(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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},
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// at: module-XXXXXXXXXX.rs:10:1
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15: Copy {
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dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock },
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src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.clk", ty: Clock },
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},
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16: Copy {
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dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset },
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src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.rst", ty: SyncReset },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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17: Const {
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dest: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
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value: 0x1,
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},
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// at: module-XXXXXXXXXX.rs:8:1
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18: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.rst", ty: SyncReset },
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},
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19: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.clk", ty: Clock },
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},
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20: AndSmall {
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dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:7:1
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21: CloneSimOnly {
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dest: StatePartIndex<SimOnlySlots>(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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src: StatePartIndex<SimOnlySlots>(7), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
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},
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// at: module-XXXXXXXXXX.rs:18:1
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22: CloneSimOnly {
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dest: StatePartIndex<SimOnlySlots>(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
src: StatePartIndex<SimOnlySlots>(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:21:1
|
|
23: CloneSimOnly {
|
|
dest: StatePartIndex<SimOnlySlots>(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
src: StatePartIndex<SimOnlySlots>(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:19:1
|
|
24: CloneSimOnly {
|
|
dest: StatePartIndex<SimOnlySlots>(13), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
src: StatePartIndex<SimOnlySlots>(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:7:1
|
|
25: CloneSimOnly {
|
|
dest: StatePartIndex<SimOnlySlots>(6), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
src: StatePartIndex<SimOnlySlots>(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
},
|
|
26: Copy {
|
|
dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock },
|
|
},
|
|
27: Copy {
|
|
dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.rst", ty: SyncReset },
|
|
src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:8:1
|
|
28: BranchIfSmallZero {
|
|
target: 33,
|
|
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
29: BranchIfSmallNonZero {
|
|
target: 32,
|
|
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
30: CloneSimOnly {
|
|
dest: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
src: StatePartIndex<SimOnlySlots>(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
},
|
|
31: Branch {
|
|
target: 33,
|
|
},
|
|
32: CloneSimOnly {
|
|
dest: StatePartIndex<SimOnlySlots>(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
src: StatePartIndex<SimOnlySlots>(10), // ({}) SlotDebugData { name: "", ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:9:1
|
|
33: BranchIfSmallZero {
|
|
target: 38,
|
|
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
34: BranchIfSmallNonZero {
|
|
target: 37,
|
|
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
35: Copy {
|
|
dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool },
|
|
},
|
|
36: Branch {
|
|
target: 38,
|
|
},
|
|
37: Copy {
|
|
dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:8:1
|
|
38: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
39: Return,
|
|
],
|
|
..
|
|
},
|
|
pc: 39,
|
|
memory_write_log: [],
|
|
memories: StatePart {
|
|
value: [],
|
|
},
|
|
small_slots: StatePart {
|
|
value: [
|
|
0,
|
|
0,
|
|
1,
|
|
0,
|
|
],
|
|
},
|
|
big_slots: StatePart {
|
|
value: [
|
|
1,
|
|
0,
|
|
1,
|
|
0,
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
0,
|
|
1,
|
|
0,
|
|
1,
|
|
0,
|
|
],
|
|
},
|
|
sim_only_slots: StatePart {
|
|
value: [
|
|
{
|
|
"extra": "value",
|
|
},
|
|
{
|
|
"extra": "value",
|
|
},
|
|
{
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
{
|
|
"bar": "baz",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
{
|
|
"extra": "value",
|
|
},
|
|
{
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
{
|
|
"extra": "value",
|
|
},
|
|
{
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
{
|
|
"extra": "value",
|
|
},
|
|
{
|
|
"extra": "value",
|
|
},
|
|
{},
|
|
{
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
{
|
|
"bar": "baz",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
{
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
{
|
|
"bar": "baz",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
],
|
|
},
|
|
},
|
|
io: Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
},
|
|
main_module: SimulationModuleState {
|
|
base_targets: [
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.cd,
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.inp,
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.out1,
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.out2,
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.out3,
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.cd,
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.cd.clk,
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.cd.rst,
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.inp,
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.out1,
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.out2,
|
|
Instance {
|
|
name: <simulator>::sim_only_connects,
|
|
instantiated: Module {
|
|
name: sim_only_connects,
|
|
..
|
|
},
|
|
}.out3,
|
|
},
|
|
did_initial_settle: true,
|
|
},
|
|
extern_modules: [
|
|
SimulationExternModuleState {
|
|
module_state: SimulationModuleState {
|
|
base_targets: [
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::inp,
|
|
is_input: true,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::out,
|
|
is_input: false,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
}.clk,
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
}.rst,
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::inp,
|
|
is_input: true,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::out,
|
|
is_input: false,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
},
|
|
did_initial_settle: true,
|
|
},
|
|
sim: ExternModuleSimulation {
|
|
generator: SimGeneratorFn {
|
|
args: (
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::inp,
|
|
is_input: true,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::out,
|
|
is_input: false,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
),
|
|
f: ...,
|
|
},
|
|
sim_io_to_generator_map: {
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
..
|
|
}: ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::inp,
|
|
is_input: true,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
}: ModuleIO {
|
|
name: sim_only_connects_helper::inp,
|
|
is_input: true,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::out,
|
|
is_input: false,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
}: ModuleIO {
|
|
name: sim_only_connects_helper::out,
|
|
is_input: false,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
},
|
|
source_location: SourceLocation(
|
|
module-XXXXXXXXXX-2.rs:5:1,
|
|
),
|
|
},
|
|
running_generator: Some(
|
|
...,
|
|
),
|
|
wait_targets: {
|
|
Change {
|
|
key: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 6, len: 0 },
|
|
},
|
|
write: None,
|
|
},
|
|
value: SimValue {
|
|
ty: Clock,
|
|
value: OpaqueSimValue {
|
|
bits: 0x1_u1,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
SimulationExternModuleState {
|
|
module_state: SimulationModuleState {
|
|
base_targets: [
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::inp,
|
|
is_input: true,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::out,
|
|
is_input: false,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
}.clk,
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
}.rst,
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::inp,
|
|
is_input: true,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::out,
|
|
is_input: false,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
},
|
|
did_initial_settle: true,
|
|
},
|
|
sim: ExternModuleSimulation {
|
|
generator: SimGeneratorFn {
|
|
args: (
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::inp,
|
|
is_input: true,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::out,
|
|
is_input: false,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
),
|
|
f: ...,
|
|
},
|
|
sim_io_to_generator_map: {
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
..
|
|
}: ModuleIO {
|
|
name: sim_only_connects_helper::cd,
|
|
is_input: true,
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: Reset,
|
|
},
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::inp,
|
|
is_input: true,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
}: ModuleIO {
|
|
name: sim_only_connects_helper::inp,
|
|
is_input: true,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_only_connects_helper::out,
|
|
is_input: false,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
}: ModuleIO {
|
|
name: sim_only_connects_helper::out,
|
|
is_input: false,
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
..
|
|
},
|
|
},
|
|
source_location: SourceLocation(
|
|
module-XXXXXXXXXX-2.rs:5:1,
|
|
),
|
|
},
|
|
running_generator: Some(
|
|
...,
|
|
),
|
|
wait_targets: {
|
|
Change {
|
|
key: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 4, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 12, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 13, len: 0 },
|
|
},
|
|
write: None,
|
|
},
|
|
value: SimValue {
|
|
ty: Clock,
|
|
value: OpaqueSimValue {
|
|
bits: 0x1_u1,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
],
|
|
state_ready_to_run: false,
|
|
trace_decls: TraceModule {
|
|
name: "sim_only_connects",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "cd",
|
|
child: TraceBundle {
|
|
name: "cd",
|
|
fields: [
|
|
TraceClock {
|
|
location: TraceScalarId(0),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
TraceSyncReset {
|
|
location: TraceScalarId(1),
|
|
name: "rst",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Source,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "inp",
|
|
child: TraceSimOnly {
|
|
location: TraceScalarId(2),
|
|
name: "inp",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Source,
|
|
},
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "out1",
|
|
child: TraceSimOnly {
|
|
location: TraceScalarId(3),
|
|
name: "out1",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
TraceModuleIO {
|
|
name: "out2",
|
|
child: TraceSimOnly {
|
|
location: TraceScalarId(4),
|
|
name: "out2",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
TraceModuleIO {
|
|
name: "out3",
|
|
child: TraceSimOnly {
|
|
location: TraceScalarId(5),
|
|
name: "out3",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
TraceInstance {
|
|
name: "helper1",
|
|
instance_io: TraceBundle {
|
|
name: "helper1",
|
|
fields: [
|
|
TraceBundle {
|
|
name: "cd",
|
|
fields: [
|
|
TraceClock {
|
|
location: TraceScalarId(10),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceSyncReset {
|
|
location: TraceScalarId(11),
|
|
name: "rst",
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
TraceSimOnly {
|
|
location: TraceScalarId(12),
|
|
name: "inp",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
TraceSimOnly {
|
|
location: TraceScalarId(13),
|
|
name: "out",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
cd: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
#[hdl(flip)] /* offset = 2 */
|
|
inp: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
/* offset = 2 */
|
|
out: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
flow: Source,
|
|
},
|
|
module: TraceModule {
|
|
name: "sim_only_connects_helper",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "cd",
|
|
child: TraceBundle {
|
|
name: "cd",
|
|
fields: [
|
|
TraceClock {
|
|
location: TraceScalarId(6),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
TraceSyncReset {
|
|
location: TraceScalarId(7),
|
|
name: "rst",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Source,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "inp",
|
|
child: TraceSimOnly {
|
|
location: TraceScalarId(8),
|
|
name: "inp",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Source,
|
|
},
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "out",
|
|
child: TraceSimOnly {
|
|
location: TraceScalarId(9),
|
|
name: "out",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
},
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
cd: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
#[hdl(flip)] /* offset = 2 */
|
|
inp: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
/* offset = 2 */
|
|
out: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
},
|
|
TraceReg {
|
|
name: "delay1",
|
|
child: TraceSimOnly {
|
|
location: TraceScalarId(14),
|
|
name: "delay1",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Duplex,
|
|
},
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
TraceReg {
|
|
name: "delay1_empty",
|
|
child: TraceBool {
|
|
location: TraceScalarId(15),
|
|
name: "delay1_empty",
|
|
flow: Duplex,
|
|
},
|
|
ty: Bool,
|
|
},
|
|
TraceInstance {
|
|
name: "helper2",
|
|
instance_io: TraceBundle {
|
|
name: "helper2",
|
|
fields: [
|
|
TraceBundle {
|
|
name: "cd",
|
|
fields: [
|
|
TraceClock {
|
|
location: TraceScalarId(20),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceSyncReset {
|
|
location: TraceScalarId(21),
|
|
name: "rst",
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
TraceSimOnly {
|
|
location: TraceScalarId(22),
|
|
name: "inp",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
TraceSimOnly {
|
|
location: TraceScalarId(23),
|
|
name: "out",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
cd: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
#[hdl(flip)] /* offset = 2 */
|
|
inp: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
/* offset = 2 */
|
|
out: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
flow: Source,
|
|
},
|
|
module: TraceModule {
|
|
name: "sim_only_connects_helper",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "cd",
|
|
child: TraceBundle {
|
|
name: "cd",
|
|
fields: [
|
|
TraceClock {
|
|
location: TraceScalarId(16),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
TraceSyncReset {
|
|
location: TraceScalarId(17),
|
|
name: "rst",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Source,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "inp",
|
|
child: TraceSimOnly {
|
|
location: TraceScalarId(18),
|
|
name: "inp",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Source,
|
|
},
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "out",
|
|
child: TraceSimOnly {
|
|
location: TraceScalarId(19),
|
|
name: "out",
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
},
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
cd: Bundle {
|
|
/* offset = 0 */
|
|
clk: Clock,
|
|
/* offset = 1 */
|
|
rst: SyncReset,
|
|
},
|
|
#[hdl(flip)] /* offset = 2 */
|
|
inp: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
/* offset = 2 */
|
|
out: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
},
|
|
],
|
|
},
|
|
traces: [
|
|
SimTrace {
|
|
id: TraceScalarId(0),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(0),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(1),
|
|
kind: BigSyncReset {
|
|
index: StatePartIndex<BigSlots>(1),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(2),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(0),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"extra": "value",
|
|
},
|
|
last_state: {
|
|
"extra": "value",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(3),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(1),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"extra": "value",
|
|
},
|
|
last_state: {
|
|
"extra": "value",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(4),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(2),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
last_state: {
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(5),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(3),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"bar": "baz",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
last_state: {
|
|
"bar": "baz",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(6),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(4),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(7),
|
|
kind: BigSyncReset {
|
|
index: StatePartIndex<BigSlots>(5),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(8),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(6),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"extra": "value",
|
|
},
|
|
last_state: {
|
|
"extra": "value",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(9),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(7),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
last_state: {
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(10),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(2),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(11),
|
|
kind: BigSyncReset {
|
|
index: StatePartIndex<BigSlots>(3),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(12),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(4),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"extra": "value",
|
|
},
|
|
last_state: {
|
|
"extra": "value",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(13),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(5),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
last_state: {
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(14),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(8),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"extra": "value",
|
|
},
|
|
last_state: {
|
|
"extra": "value",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(15),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(6),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(16),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(12),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(17),
|
|
kind: BigSyncReset {
|
|
index: StatePartIndex<BigSlots>(13),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(18),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(13),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
last_state: {
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(19),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(14),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"bar": "baz",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
last_state: {
|
|
"bar": "baz",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(20),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(10),
|
|
},
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(21),
|
|
kind: BigSyncReset {
|
|
index: StatePartIndex<BigSlots>(11),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(22),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(11),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
last_state: {
|
|
"bar": "",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(23),
|
|
kind: SimOnly {
|
|
index: StatePartIndex<SimOnlySlots>(12),
|
|
ty: SimOnly<alloc::collections::btree::map::BTreeMap<alloc::string::String, alloc::rc::Rc<str>>>,
|
|
},
|
|
state: {
|
|
"bar": "baz",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
last_state: {
|
|
"bar": "baz",
|
|
"extra": "value",
|
|
"foo": "baz",
|
|
},
|
|
},
|
|
],
|
|
trace_memories: {},
|
|
trace_writers: [
|
|
Running(
|
|
VcdWriter {
|
|
finished_init: true,
|
|
timescale: 1 ps,
|
|
..
|
|
},
|
|
),
|
|
],
|
|
instant: 16 μs,
|
|
clocks_triggered: [
|
|
StatePartIndex<SmallSlots>(1),
|
|
],
|
|
..
|
|
} |