forked from libre-chip/fayalite
		
	rename fire/fire_data to firing/firing_data
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					 1 changed files with 23 additions and 23 deletions
				
			
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			@ -12,28 +12,28 @@ pub struct ReadyValid<T> {
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impl<T: Type> ReadyValid<T> {
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    #[hdl]
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    pub fn fire(expr: Expr<Self>) -> Expr<Bool> {
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    pub fn firing(expr: Expr<Self>) -> Expr<Bool> {
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        #[hdl]
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        let fire: Bool = wire();
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        let firing: Bool = wire();
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        #[hdl]
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        match expr.data {
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            HdlNone => connect(fire, false),
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            HdlSome(_) => connect(fire, expr.ready),
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            HdlNone => connect(firing, false),
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            HdlSome(_) => connect(firing, expr.ready),
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        }
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        fire
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        firing
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    }
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    #[hdl]
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    pub fn fire_data(expr: impl ToExpr<Type = Self>) -> Expr<HdlOption<T>> {
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    pub fn firing_data(expr: impl ToExpr<Type = Self>) -> Expr<HdlOption<T>> {
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        let expr = expr.to_expr();
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        let option_ty = Expr::ty(expr).data;
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        #[hdl]
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        let fire_data = wire(option_ty);
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        connect(fire_data, option_ty.HdlNone());
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        let firing_data = wire(option_ty);
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        connect(firing_data, option_ty.HdlNone());
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        #[hdl]
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        if expr.ready {
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            connect(fire_data, expr.data);
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            connect(firing_data, expr.data);
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        }
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        fire_data
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        firing_data
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    }
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    #[hdl]
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    pub fn map<R: Type>(
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			@ -82,11 +82,11 @@ pub fn queue<T: Type>(
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    let write_port = mem.new_write_port();
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    #[hdl]
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    let inp_fire: Bool = wire();
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    connect(inp_fire, ReadyValid::fire(inp));
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    let inp_firing: Bool = wire();
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    connect(inp_firing, ReadyValid::firing(inp));
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    #[hdl]
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    let out_fire: Bool = wire();
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    connect(out_fire, ReadyValid::fire(out));
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    let out_firing: Bool = wire();
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    connect(out_firing, ReadyValid::firing(out));
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    #[hdl]
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    let indexes_equal: Bool = wire();
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    connect(indexes_equal, inp_index_reg.cmp_eq(out_index_reg));
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			@ -101,7 +101,7 @@ pub fn queue<T: Type>(
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    connect(read_port.en, true);
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    connect(read_port.clk, cd.clk);
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    connect(write_port.addr, inp_index_reg);
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    connect(write_port.en, inp_fire);
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    connect(write_port.en, inp_firing);
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    connect(write_port.clk, cd.clk);
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    connect(write_port.data, HdlOption::unwrap_or(inp.data, ty.uninit()));
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    connect(write_port.mask, splat_mask(ty, true.to_expr()));
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			@ -126,12 +126,12 @@ pub fn queue<T: Type>(
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    }
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    #[hdl]
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    if inp_fire.cmp_ne(out_fire) {
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        connect(maybe_full_reg, inp_fire);
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    if inp_firing.cmp_ne(out_firing) {
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        connect(maybe_full_reg, inp_firing);
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    }
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    #[hdl]
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    if inp_fire {
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    if inp_firing {
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        #[hdl]
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        if inp_index_reg.cmp_eq(capacity.get() - 1) {
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            connect_any(inp_index_reg, 0_hdl_u0);
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			@ -141,7 +141,7 @@ pub fn queue<T: Type>(
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    }
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    #[hdl]
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    if out_fire {
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    if out_firing {
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        #[hdl]
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        if out_index_reg.cmp_eq(capacity.get() - 1) {
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            connect_any(out_index_reg, 0_hdl_u0);
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			@ -258,9 +258,9 @@ mod tests {
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            connect(next_expected_count, expected_count_reg);
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            connect(expected_count_reg, next_expected_count);
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            #[hdl]
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            if ReadyValid::fire(dut.inp) & !ReadyValid::fire(dut.out) {
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            if ReadyValid::firing(dut.inp) & !ReadyValid::firing(dut.out) {
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                connect_any(next_expected_count, expected_count_reg + 1u8);
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            } else if !ReadyValid::fire(dut.inp) & ReadyValid::fire(dut.out) {
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            } else if !ReadyValid::firing(dut.inp) & ReadyValid::firing(dut.out) {
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                connect_any(next_expected_count, expected_count_reg - 1u8);
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            }
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            hdl_assert(cd.clk, expected_count_reg.cmp_eq(dut.count), "");
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			@ -289,7 +289,7 @@ mod tests {
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            let stored_inp_data_reg = reg_builder().clock_domain(cd).reset(0u8);
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            #[hdl]
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            if let HdlSome(data) = ReadyValid::fire_data(dut.inp) {
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            if let HdlSome(data) = ReadyValid::firing_data(dut.inp) {
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                #[hdl]
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                if inp_index_reg.cmp_lt(index_max) {
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                    connect_any(inp_index_reg, inp_index_reg + 1u8);
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			@ -311,7 +311,7 @@ mod tests {
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            let stored_out_data_reg = reg_builder().clock_domain(cd).reset(0u8);
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            #[hdl]
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            if let HdlSome(data) = ReadyValid::fire_data(dut.out) {
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            if let HdlSome(data) = ReadyValid::firing_data(dut.out) {
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                #[hdl]
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                if out_index_reg.cmp_lt(index_max) {
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                    connect_any(out_index_reg, out_index_reg + 1u8);
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