forked from libre-chip/fayalite
tests/sim: split expected output text into separate files
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13 changed files with 3508 additions and 3513 deletions
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130
crates/fayalite/tests/sim/expected/connect_const.txt
Normal file
130
crates/fayalite/tests/sim/expected/connect_const.txt
Normal file
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@ -0,0 +1,130 @@
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Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 2,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<8>,
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},
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],
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..
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},
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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Const {
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dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
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value: 5,
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},
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// at: module-XXXXXXXXXX.rs:3:1
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Copy {
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dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Return,
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],
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..
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},
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pc: 2,
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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5,
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5,
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],
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},
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},
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io: Instance {
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name: <simulator>::connect_const,
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instantiated: Module {
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name: connect_const,
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::connect_const,
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instantiated: Module {
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name: connect_const,
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..
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},
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}.o: CompiledValue {
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layout: CompiledTypeLayout {
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ty: UInt<8>,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
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ty: UInt<8>,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
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write: None,
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},
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},
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made_initial_step: true,
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needs_settle: false,
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trace_decls: TraceModule {
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name: "connect_const",
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children: [
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TraceModuleIO {
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name: "o",
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child: TraceUInt {
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id: TraceScalarId(0),
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name: "o",
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ty: UInt<8>,
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flow: Sink,
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},
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ty: UInt<8>,
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flow: Sink,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: BigUInt {
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index: StatePartIndex<BigSlots>(0),
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ty: UInt<8>,
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},
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state: 0x05,
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last_state: 0x05,
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},
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],
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trace_writers: [],
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instant: 0 s,
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clocks_triggered: [],
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}
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217
crates/fayalite/tests/sim/expected/connect_const_reset.txt
Normal file
217
crates/fayalite/tests/sim/expected/connect_const_reset.txt
Normal file
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@ -0,0 +1,217 @@
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Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 5,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
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ty: AsyncReset,
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},
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SlotDebugData {
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name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: AsyncReset,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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Const {
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dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
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value: 1,
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},
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Copy {
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dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
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src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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Copy {
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dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
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src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Copy {
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dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
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},
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// at: module-XXXXXXXXXX.rs:5:1
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Copy {
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dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
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src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Return,
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],
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..
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},
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pc: 5,
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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1,
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1,
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1,
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1,
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1,
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],
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},
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},
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io: Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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}.bit_out: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Bool,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
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ty: Bool,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
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},
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write: None,
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},
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Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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}.reset_out: CompiledValue {
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layout: CompiledTypeLayout {
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ty: AsyncReset,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
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ty: AsyncReset,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
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write: None,
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},
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},
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made_initial_step: true,
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needs_settle: false,
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trace_decls: TraceModule {
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name: "connect_const_reset",
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children: [
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TraceModuleIO {
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name: "reset_out",
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child: TraceAsyncReset {
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id: TraceScalarId(0),
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name: "reset_out",
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flow: Sink,
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},
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ty: AsyncReset,
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flow: Sink,
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},
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TraceModuleIO {
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name: "bit_out",
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child: TraceBool {
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id: TraceScalarId(1),
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name: "bit_out",
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flow: Sink,
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},
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ty: Bool,
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flow: Sink,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: BigAsyncReset {
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index: StatePartIndex<BigSlots>(0),
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},
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state: 0x1,
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last_state: 0x1,
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},
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SimTrace {
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id: TraceScalarId(1),
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kind: BigBool {
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index: StatePartIndex<BigSlots>(1),
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},
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state: 0x1,
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last_state: 0x1,
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},
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],
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trace_writers: [
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Running(
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VcdWriter {
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finished_init: true,
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timescale: 1 ps,
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..
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},
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),
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],
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instant: 1 μs,
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clocks_triggered: [],
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}
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11
crates/fayalite/tests/sim/expected/connect_const_reset.vcd
Normal file
11
crates/fayalite/tests/sim/expected/connect_const_reset.vcd
Normal file
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$timescale 1 ps $end
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$scope module connect_const_reset $end
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$var wire 1 ! reset_out $end
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$var wire 1 " bit_out $end
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$upscope $end
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$enddefinitions $end
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$dumpvars
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1!
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1"
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$end
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#1000000
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509
crates/fayalite/tests/sim/expected/counter_async.txt
Normal file
509
crates/fayalite/tests/sim/expected/counter_async.txt
Normal file
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@ -0,0 +1,509 @@
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Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 4,
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debug_data: [
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SlotDebugData {
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name: "",
|
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ty: Bool,
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},
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SlotDebugData {
|
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name: "",
|
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ty: Bool,
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},
|
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SlotDebugData {
|
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name: "",
|
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ty: Bool,
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},
|
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SlotDebugData {
|
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name: "",
|
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ty: Bool,
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},
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],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 10,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(counter: counter).counter::cd.clk",
|
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ty: Clock,
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},
|
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SlotDebugData {
|
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name: "InstantiatedModule(counter: counter).counter::cd.rst",
|
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ty: AsyncReset,
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},
|
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SlotDebugData {
|
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name: "InstantiatedModule(counter: counter).counter::count",
|
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ty: UInt<4>,
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},
|
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SlotDebugData {
|
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name: "InstantiatedModule(counter: counter).counter::count_reg",
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ty: UInt<4>,
|
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},
|
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SlotDebugData {
|
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name: "InstantiatedModule(counter: counter).counter::count_reg$next",
|
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ty: UInt<4>,
|
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},
|
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SlotDebugData {
|
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name: "",
|
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ty: UInt<4>,
|
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},
|
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SlotDebugData {
|
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name: "",
|
||||
ty: Bool,
|
||||
},
|
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SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<1>,
|
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},
|
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SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<5>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
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},
|
||||
},
|
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},
|
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insns: [
|
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// at: module-XXXXXXXXXX.rs:1:1
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Const {
|
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dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
|
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value: 1,
|
||||
},
|
||||
Copy {
|
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dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
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src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
|
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},
|
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// at: module-XXXXXXXXXX.rs:3:1
|
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IsNonZeroDestIsSmall {
|
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dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
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Const {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 3,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:3:1
|
||||
BranchIfZero {
|
||||
target: 6,
|
||||
value: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
Add {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
|
||||
lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
rhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
|
||||
dest_width: 4,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:6:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:3:1
|
||||
IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
|
||||
},
|
||||
AndSmall {
|
||||
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
BranchIfSmallNonZero {
|
||||
target: 16,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
BranchIfSmallZero {
|
||||
target: 17,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
},
|
||||
Branch {
|
||||
target: 17,
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
NotSmall {
|
||||
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
Return,
|
||||
],
|
||||
..
|
||||
},
|
||||
pc: 18,
|
||||
small_slots: StatePart {
|
||||
value: [
|
||||
18446744073709551614,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
],
|
||||
},
|
||||
big_slots: StatePart {
|
||||
value: [
|
||||
1,
|
||||
0,
|
||||
3,
|
||||
3,
|
||||
4,
|
||||
3,
|
||||
0,
|
||||
1,
|
||||
4,
|
||||
4,
|
||||
],
|
||||
},
|
||||
},
|
||||
io: Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: AsyncReset,
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 2,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::cd.clk",
|
||||
ty: Clock,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::cd.rst",
|
||||
ty: AsyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: AsyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: AsyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.clk: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.rst: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: AsyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: AsyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.count: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::count",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "counter",
|
||||
children: [
|
||||
TraceModuleIO {
|
||||
name: "cd",
|
||||
child: TraceBundle {
|
||||
name: "cd",
|
||||
fields: [
|
||||
TraceClock {
|
||||
id: TraceScalarId(0),
|
||||
name: "clk",
|
||||
flow: Source,
|
||||
},
|
||||
TraceAsyncReset {
|
||||
id: TraceScalarId(1),
|
||||
name: "rst",
|
||||
flow: Source,
|
||||
},
|
||||
],
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: AsyncReset,
|
||||
},
|
||||
flow: Source,
|
||||
},
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: AsyncReset,
|
||||
},
|
||||
flow: Source,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "count",
|
||||
child: TraceUInt {
|
||||
id: TraceScalarId(2),
|
||||
name: "count",
|
||||
ty: UInt<4>,
|
||||
flow: Sink,
|
||||
},
|
||||
ty: UInt<4>,
|
||||
flow: Sink,
|
||||
},
|
||||
TraceReg {
|
||||
name: "count_reg",
|
||||
child: TraceUInt {
|
||||
id: TraceScalarId(3),
|
||||
name: "count_reg",
|
||||
ty: UInt<4>,
|
||||
flow: Duplex,
|
||||
},
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
},
|
||||
traces: [
|
||||
SimTrace {
|
||||
id: TraceScalarId(0),
|
||||
kind: BigClock {
|
||||
index: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
state: 0x1,
|
||||
last_state: 0x1,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(1),
|
||||
kind: BigAsyncReset {
|
||||
index: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(2),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(2),
|
||||
ty: UInt<4>,
|
||||
},
|
||||
state: 0x3,
|
||||
last_state: 0x2,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(3),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(3),
|
||||
ty: UInt<4>,
|
||||
},
|
||||
state: 0x3,
|
||||
last_state: 0x3,
|
||||
},
|
||||
],
|
||||
trace_writers: [
|
||||
Running(
|
||||
VcdWriter {
|
||||
finished_init: true,
|
||||
timescale: 1 ps,
|
||||
..
|
||||
},
|
||||
),
|
||||
],
|
||||
instant: 66 μs,
|
||||
clocks_triggered: [
|
||||
StatePartIndex<SmallSlots>(1),
|
||||
],
|
||||
}
|
||||
217
crates/fayalite/tests/sim/expected/counter_async.vcd
Normal file
217
crates/fayalite/tests/sim/expected/counter_async.vcd
Normal file
|
|
@ -0,0 +1,217 @@
|
|||
$timescale 1 ps $end
|
||||
$scope module counter $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 1 " rst $end
|
||||
$upscope $end
|
||||
$var wire 4 # count $end
|
||||
$var reg 4 $ count_reg $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
0!
|
||||
0"
|
||||
b0 #
|
||||
b0 $
|
||||
$end
|
||||
#500000
|
||||
1"
|
||||
b11 #
|
||||
b11 $
|
||||
#1000000
|
||||
1!
|
||||
#1500000
|
||||
0"
|
||||
#2000000
|
||||
0!
|
||||
#3000000
|
||||
1!
|
||||
b100 $
|
||||
b100 #
|
||||
#4000000
|
||||
0!
|
||||
#5000000
|
||||
1!
|
||||
b101 $
|
||||
b101 #
|
||||
#6000000
|
||||
0!
|
||||
#7000000
|
||||
1!
|
||||
b110 $
|
||||
b110 #
|
||||
#8000000
|
||||
0!
|
||||
#9000000
|
||||
1!
|
||||
b111 $
|
||||
b111 #
|
||||
#10000000
|
||||
0!
|
||||
#11000000
|
||||
1!
|
||||
b1000 $
|
||||
b1000 #
|
||||
#12000000
|
||||
0!
|
||||
#13000000
|
||||
1!
|
||||
b1001 $
|
||||
b1001 #
|
||||
#14000000
|
||||
0!
|
||||
#15000000
|
||||
1!
|
||||
b1010 $
|
||||
b1010 #
|
||||
#16000000
|
||||
0!
|
||||
#17000000
|
||||
1!
|
||||
b1011 $
|
||||
b1011 #
|
||||
#18000000
|
||||
0!
|
||||
#19000000
|
||||
1!
|
||||
b1100 $
|
||||
b1100 #
|
||||
#20000000
|
||||
0!
|
||||
#21000000
|
||||
1!
|
||||
b1101 $
|
||||
b1101 #
|
||||
#22000000
|
||||
0!
|
||||
#23000000
|
||||
1!
|
||||
b1110 $
|
||||
b1110 #
|
||||
#24000000
|
||||
0!
|
||||
#25000000
|
||||
1!
|
||||
b1111 $
|
||||
b1111 #
|
||||
#26000000
|
||||
0!
|
||||
#27000000
|
||||
1!
|
||||
b0 $
|
||||
b0 #
|
||||
#28000000
|
||||
0!
|
||||
#29000000
|
||||
1!
|
||||
b1 $
|
||||
b1 #
|
||||
#30000000
|
||||
0!
|
||||
#31000000
|
||||
1!
|
||||
b10 $
|
||||
b10 #
|
||||
#32000000
|
||||
0!
|
||||
#33000000
|
||||
1!
|
||||
b11 $
|
||||
b11 #
|
||||
#34000000
|
||||
0!
|
||||
#35000000
|
||||
1!
|
||||
b100 $
|
||||
b100 #
|
||||
#36000000
|
||||
0!
|
||||
#37000000
|
||||
1!
|
||||
b101 $
|
||||
b101 #
|
||||
#38000000
|
||||
0!
|
||||
#39000000
|
||||
1!
|
||||
b110 $
|
||||
b110 #
|
||||
#40000000
|
||||
0!
|
||||
#41000000
|
||||
1!
|
||||
b111 $
|
||||
b111 #
|
||||
#42000000
|
||||
0!
|
||||
#43000000
|
||||
1!
|
||||
b1000 $
|
||||
b1000 #
|
||||
#44000000
|
||||
0!
|
||||
#45000000
|
||||
1!
|
||||
b1001 $
|
||||
b1001 #
|
||||
#46000000
|
||||
0!
|
||||
#47000000
|
||||
1!
|
||||
b1010 $
|
||||
b1010 #
|
||||
#48000000
|
||||
0!
|
||||
#49000000
|
||||
1!
|
||||
b1011 $
|
||||
b1011 #
|
||||
#50000000
|
||||
0!
|
||||
#51000000
|
||||
1!
|
||||
b1100 $
|
||||
b1100 #
|
||||
#52000000
|
||||
0!
|
||||
#53000000
|
||||
1!
|
||||
b1101 $
|
||||
b1101 #
|
||||
#54000000
|
||||
0!
|
||||
#55000000
|
||||
1!
|
||||
b1110 $
|
||||
b1110 #
|
||||
#56000000
|
||||
0!
|
||||
#57000000
|
||||
1!
|
||||
b1111 $
|
||||
b1111 #
|
||||
#58000000
|
||||
0!
|
||||
#59000000
|
||||
1!
|
||||
b0 $
|
||||
b0 #
|
||||
#60000000
|
||||
0!
|
||||
#61000000
|
||||
1!
|
||||
b1 $
|
||||
b1 #
|
||||
#62000000
|
||||
0!
|
||||
#63000000
|
||||
1!
|
||||
b10 $
|
||||
b10 #
|
||||
#64000000
|
||||
0!
|
||||
#65000000
|
||||
1!
|
||||
b11 $
|
||||
b11 #
|
||||
#66000000
|
||||
490
crates/fayalite/tests/sim/expected/counter_sync.txt
Normal file
490
crates/fayalite/tests/sim/expected/counter_sync.txt
Normal file
|
|
@ -0,0 +1,490 @@
|
|||
Simulation {
|
||||
state: State {
|
||||
insns: Insns {
|
||||
state_layout: StateLayout {
|
||||
ty: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 4,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 9,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::cd.clk",
|
||||
ty: Clock,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::cd.rst",
|
||||
ty: SyncReset,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::count",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::count_reg",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::count_reg$next",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<1>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<5>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
},
|
||||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:6:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
Const {
|
||||
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
value: 1,
|
||||
},
|
||||
Add {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
|
||||
lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
rhs: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
|
||||
},
|
||||
CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
|
||||
dest_width: 4,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:3:1
|
||||
IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
Const {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 3,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:3:1
|
||||
IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
|
||||
},
|
||||
AndSmall {
|
||||
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
BranchIfSmallZero {
|
||||
target: 14,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
BranchIfSmallNonZero {
|
||||
target: 13,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
|
||||
},
|
||||
Branch {
|
||||
target: 14,
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
NotSmall {
|
||||
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
Return,
|
||||
],
|
||||
..
|
||||
},
|
||||
pc: 15,
|
||||
small_slots: StatePart {
|
||||
value: [
|
||||
18446744073709551614,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
],
|
||||
},
|
||||
big_slots: StatePart {
|
||||
value: [
|
||||
1,
|
||||
0,
|
||||
3,
|
||||
3,
|
||||
4,
|
||||
3,
|
||||
1,
|
||||
4,
|
||||
4,
|
||||
],
|
||||
},
|
||||
},
|
||||
io: Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: SyncReset,
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 2,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::cd.clk",
|
||||
ty: Clock,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::cd.rst",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.clk: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.cd.rst: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: SyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::counter,
|
||||
instantiated: Module {
|
||||
name: counter,
|
||||
..
|
||||
},
|
||||
}.count: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(counter: counter).counter::count",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "counter",
|
||||
children: [
|
||||
TraceModuleIO {
|
||||
name: "cd",
|
||||
child: TraceBundle {
|
||||
name: "cd",
|
||||
fields: [
|
||||
TraceClock {
|
||||
id: TraceScalarId(0),
|
||||
name: "clk",
|
||||
flow: Source,
|
||||
},
|
||||
TraceSyncReset {
|
||||
id: TraceScalarId(1),
|
||||
name: "rst",
|
||||
flow: Source,
|
||||
},
|
||||
],
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: SyncReset,
|
||||
},
|
||||
flow: Source,
|
||||
},
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: SyncReset,
|
||||
},
|
||||
flow: Source,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "count",
|
||||
child: TraceUInt {
|
||||
id: TraceScalarId(2),
|
||||
name: "count",
|
||||
ty: UInt<4>,
|
||||
flow: Sink,
|
||||
},
|
||||
ty: UInt<4>,
|
||||
flow: Sink,
|
||||
},
|
||||
TraceReg {
|
||||
name: "count_reg",
|
||||
child: TraceUInt {
|
||||
id: TraceScalarId(3),
|
||||
name: "count_reg",
|
||||
ty: UInt<4>,
|
||||
flow: Duplex,
|
||||
},
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
},
|
||||
traces: [
|
||||
SimTrace {
|
||||
id: TraceScalarId(0),
|
||||
kind: BigClock {
|
||||
index: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
state: 0x1,
|
||||
last_state: 0x1,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(1),
|
||||
kind: BigSyncReset {
|
||||
index: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(2),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(2),
|
||||
ty: UInt<4>,
|
||||
},
|
||||
state: 0x3,
|
||||
last_state: 0x2,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(3),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(3),
|
||||
ty: UInt<4>,
|
||||
},
|
||||
state: 0x3,
|
||||
last_state: 0x3,
|
||||
},
|
||||
],
|
||||
trace_writers: [
|
||||
Running(
|
||||
VcdWriter {
|
||||
finished_init: true,
|
||||
timescale: 1 ps,
|
||||
..
|
||||
},
|
||||
),
|
||||
],
|
||||
instant: 66 μs,
|
||||
clocks_triggered: [
|
||||
StatePartIndex<SmallSlots>(1),
|
||||
],
|
||||
}
|
||||
214
crates/fayalite/tests/sim/expected/counter_sync.vcd
Normal file
214
crates/fayalite/tests/sim/expected/counter_sync.vcd
Normal file
|
|
@ -0,0 +1,214 @@
|
|||
$timescale 1 ps $end
|
||||
$scope module counter $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 1 " rst $end
|
||||
$upscope $end
|
||||
$var wire 4 # count $end
|
||||
$var reg 4 $ count_reg $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
0!
|
||||
1"
|
||||
b0 #
|
||||
b0 $
|
||||
$end
|
||||
#1000000
|
||||
1!
|
||||
b11 $
|
||||
b11 #
|
||||
0"
|
||||
#2000000
|
||||
0!
|
||||
#3000000
|
||||
1!
|
||||
b100 $
|
||||
b100 #
|
||||
#4000000
|
||||
0!
|
||||
#5000000
|
||||
1!
|
||||
b101 $
|
||||
b101 #
|
||||
#6000000
|
||||
0!
|
||||
#7000000
|
||||
1!
|
||||
b110 $
|
||||
b110 #
|
||||
#8000000
|
||||
0!
|
||||
#9000000
|
||||
1!
|
||||
b111 $
|
||||
b111 #
|
||||
#10000000
|
||||
0!
|
||||
#11000000
|
||||
1!
|
||||
b1000 $
|
||||
b1000 #
|
||||
#12000000
|
||||
0!
|
||||
#13000000
|
||||
1!
|
||||
b1001 $
|
||||
b1001 #
|
||||
#14000000
|
||||
0!
|
||||
#15000000
|
||||
1!
|
||||
b1010 $
|
||||
b1010 #
|
||||
#16000000
|
||||
0!
|
||||
#17000000
|
||||
1!
|
||||
b1011 $
|
||||
b1011 #
|
||||
#18000000
|
||||
0!
|
||||
#19000000
|
||||
1!
|
||||
b1100 $
|
||||
b1100 #
|
||||
#20000000
|
||||
0!
|
||||
#21000000
|
||||
1!
|
||||
b1101 $
|
||||
b1101 #
|
||||
#22000000
|
||||
0!
|
||||
#23000000
|
||||
1!
|
||||
b1110 $
|
||||
b1110 #
|
||||
#24000000
|
||||
0!
|
||||
#25000000
|
||||
1!
|
||||
b1111 $
|
||||
b1111 #
|
||||
#26000000
|
||||
0!
|
||||
#27000000
|
||||
1!
|
||||
b0 $
|
||||
b0 #
|
||||
#28000000
|
||||
0!
|
||||
#29000000
|
||||
1!
|
||||
b1 $
|
||||
b1 #
|
||||
#30000000
|
||||
0!
|
||||
#31000000
|
||||
1!
|
||||
b10 $
|
||||
b10 #
|
||||
#32000000
|
||||
0!
|
||||
#33000000
|
||||
1!
|
||||
b11 $
|
||||
b11 #
|
||||
#34000000
|
||||
0!
|
||||
#35000000
|
||||
1!
|
||||
b100 $
|
||||
b100 #
|
||||
#36000000
|
||||
0!
|
||||
#37000000
|
||||
1!
|
||||
b101 $
|
||||
b101 #
|
||||
#38000000
|
||||
0!
|
||||
#39000000
|
||||
1!
|
||||
b110 $
|
||||
b110 #
|
||||
#40000000
|
||||
0!
|
||||
#41000000
|
||||
1!
|
||||
b111 $
|
||||
b111 #
|
||||
#42000000
|
||||
0!
|
||||
#43000000
|
||||
1!
|
||||
b1000 $
|
||||
b1000 #
|
||||
#44000000
|
||||
0!
|
||||
#45000000
|
||||
1!
|
||||
b1001 $
|
||||
b1001 #
|
||||
#46000000
|
||||
0!
|
||||
#47000000
|
||||
1!
|
||||
b1010 $
|
||||
b1010 #
|
||||
#48000000
|
||||
0!
|
||||
#49000000
|
||||
1!
|
||||
b1011 $
|
||||
b1011 #
|
||||
#50000000
|
||||
0!
|
||||
#51000000
|
||||
1!
|
||||
b1100 $
|
||||
b1100 #
|
||||
#52000000
|
||||
0!
|
||||
#53000000
|
||||
1!
|
||||
b1101 $
|
||||
b1101 #
|
||||
#54000000
|
||||
0!
|
||||
#55000000
|
||||
1!
|
||||
b1110 $
|
||||
b1110 #
|
||||
#56000000
|
||||
0!
|
||||
#57000000
|
||||
1!
|
||||
b1111 $
|
||||
b1111 #
|
||||
#58000000
|
||||
0!
|
||||
#59000000
|
||||
1!
|
||||
b0 $
|
||||
b0 #
|
||||
#60000000
|
||||
0!
|
||||
#61000000
|
||||
1!
|
||||
b1 $
|
||||
b1 #
|
||||
#62000000
|
||||
0!
|
||||
#63000000
|
||||
1!
|
||||
b10 $
|
||||
b10 #
|
||||
#64000000
|
||||
0!
|
||||
#65000000
|
||||
1!
|
||||
b11 $
|
||||
b11 #
|
||||
#66000000
|
||||
798
crates/fayalite/tests/sim/expected/mod1.txt
Normal file
798
crates/fayalite/tests/sim/expected/mod1.txt
Normal file
|
|
@ -0,0 +1,798 @@
|
|||
Simulation {
|
||||
state: State {
|
||||
insns: Insns {
|
||||
state_layout: StateLayout {
|
||||
ty: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 17,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.i",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.o",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::child.i",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::child.o",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::child.i2",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::child.o2",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
},
|
||||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:2:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:1:1
|
||||
Const {
|
||||
dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 15,
|
||||
},
|
||||
Const {
|
||||
dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
value: 5,
|
||||
},
|
||||
CmpLt {
|
||||
dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
|
||||
},
|
||||
CastToUInt {
|
||||
dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
|
||||
dest_width: 4,
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:7:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:8:1
|
||||
BranchIfZero {
|
||||
target: 11,
|
||||
value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:9:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:2:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
|
||||
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:1:1
|
||||
CastToSInt {
|
||||
dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
|
||||
dest_width: 2,
|
||||
},
|
||||
// at: module-XXXXXXXXXX-2.rs:6:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:2:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:4:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
|
||||
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
Return,
|
||||
],
|
||||
..
|
||||
},
|
||||
pc: 17,
|
||||
small_slots: StatePart {
|
||||
value: [],
|
||||
},
|
||||
big_slots: StatePart {
|
||||
value: [
|
||||
10,
|
||||
-2,
|
||||
-2,
|
||||
15,
|
||||
10,
|
||||
-2,
|
||||
-2,
|
||||
15,
|
||||
10,
|
||||
-2,
|
||||
-2,
|
||||
15,
|
||||
-2,
|
||||
14,
|
||||
5,
|
||||
1,
|
||||
15,
|
||||
],
|
||||
},
|
||||
},
|
||||
io: Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
}.o: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bundle {
|
||||
#[hdl(flip)] /* offset = 0 */
|
||||
i: UInt<4>,
|
||||
/* offset = 4 */
|
||||
o: SInt<2>,
|
||||
#[hdl(flip)] /* offset = 6 */
|
||||
i2: SInt<2>,
|
||||
/* offset = 8 */
|
||||
o2: UInt<4>,
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 4,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.i",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.o",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(2),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(3),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
}.o.i: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
}.o.i2: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
}.o.o: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: SInt<2>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SInt<2>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::mod1,
|
||||
instantiated: Module {
|
||||
name: mod1,
|
||||
..
|
||||
},
|
||||
}.o.o2: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: UInt<4>,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: UInt<4>,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "mod1",
|
||||
children: [
|
||||
TraceModuleIO {
|
||||
name: "o",
|
||||
child: TraceBundle {
|
||||
name: "o",
|
||||
fields: [
|
||||
TraceUInt {
|
||||
id: TraceScalarId(0),
|
||||
name: "i",
|
||||
ty: UInt<4>,
|
||||
flow: Source,
|
||||
},
|
||||
TraceSInt {
|
||||
id: TraceScalarId(1),
|
||||
name: "o",
|
||||
ty: SInt<2>,
|
||||
flow: Sink,
|
||||
},
|
||||
TraceSInt {
|
||||
id: TraceScalarId(2),
|
||||
name: "i2",
|
||||
ty: SInt<2>,
|
||||
flow: Source,
|
||||
},
|
||||
TraceUInt {
|
||||
id: TraceScalarId(3),
|
||||
name: "o2",
|
||||
ty: UInt<4>,
|
||||
flow: Sink,
|
||||
},
|
||||
],
|
||||
ty: Bundle {
|
||||
#[hdl(flip)] /* offset = 0 */
|
||||
i: UInt<4>,
|
||||
/* offset = 4 */
|
||||
o: SInt<2>,
|
||||
#[hdl(flip)] /* offset = 6 */
|
||||
i2: SInt<2>,
|
||||
/* offset = 8 */
|
||||
o2: UInt<4>,
|
||||
},
|
||||
flow: Sink,
|
||||
},
|
||||
ty: Bundle {
|
||||
#[hdl(flip)] /* offset = 0 */
|
||||
i: UInt<4>,
|
||||
/* offset = 4 */
|
||||
o: SInt<2>,
|
||||
#[hdl(flip)] /* offset = 6 */
|
||||
i2: SInt<2>,
|
||||
/* offset = 8 */
|
||||
o2: UInt<4>,
|
||||
},
|
||||
flow: Sink,
|
||||
},
|
||||
TraceInstance {
|
||||
name: "child",
|
||||
instance_io: TraceBundle {
|
||||
name: "child",
|
||||
fields: [
|
||||
TraceUInt {
|
||||
id: TraceScalarId(8),
|
||||
name: "i",
|
||||
ty: UInt<4>,
|
||||
flow: Sink,
|
||||
},
|
||||
TraceSInt {
|
||||
id: TraceScalarId(9),
|
||||
name: "o",
|
||||
ty: SInt<2>,
|
||||
flow: Source,
|
||||
},
|
||||
TraceSInt {
|
||||
id: TraceScalarId(10),
|
||||
name: "i2",
|
||||
ty: SInt<2>,
|
||||
flow: Sink,
|
||||
},
|
||||
TraceUInt {
|
||||
id: TraceScalarId(11),
|
||||
name: "o2",
|
||||
ty: UInt<4>,
|
||||
flow: Source,
|
||||
},
|
||||
],
|
||||
ty: Bundle {
|
||||
#[hdl(flip)] /* offset = 0 */
|
||||
i: UInt<4>,
|
||||
/* offset = 4 */
|
||||
o: SInt<2>,
|
||||
#[hdl(flip)] /* offset = 6 */
|
||||
i2: SInt<2>,
|
||||
/* offset = 8 */
|
||||
o2: UInt<4>,
|
||||
},
|
||||
flow: Source,
|
||||
},
|
||||
module: TraceModule {
|
||||
name: "mod1_child",
|
||||
children: [
|
||||
TraceModuleIO {
|
||||
name: "i",
|
||||
child: TraceUInt {
|
||||
id: TraceScalarId(4),
|
||||
name: "i",
|
||||
ty: UInt<4>,
|
||||
flow: Source,
|
||||
},
|
||||
ty: UInt<4>,
|
||||
flow: Source,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "o",
|
||||
child: TraceSInt {
|
||||
id: TraceScalarId(5),
|
||||
name: "o",
|
||||
ty: SInt<2>,
|
||||
flow: Sink,
|
||||
},
|
||||
ty: SInt<2>,
|
||||
flow: Sink,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "i2",
|
||||
child: TraceSInt {
|
||||
id: TraceScalarId(6),
|
||||
name: "i2",
|
||||
ty: SInt<2>,
|
||||
flow: Source,
|
||||
},
|
||||
ty: SInt<2>,
|
||||
flow: Source,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "o2",
|
||||
child: TraceUInt {
|
||||
id: TraceScalarId(7),
|
||||
name: "o2",
|
||||
ty: UInt<4>,
|
||||
flow: Sink,
|
||||
},
|
||||
ty: UInt<4>,
|
||||
flow: Sink,
|
||||
},
|
||||
],
|
||||
},
|
||||
ty: Bundle {
|
||||
#[hdl(flip)] /* offset = 0 */
|
||||
i: UInt<4>,
|
||||
/* offset = 4 */
|
||||
o: SInt<2>,
|
||||
#[hdl(flip)] /* offset = 6 */
|
||||
i2: SInt<2>,
|
||||
/* offset = 8 */
|
||||
o2: UInt<4>,
|
||||
},
|
||||
},
|
||||
],
|
||||
},
|
||||
traces: [
|
||||
SimTrace {
|
||||
id: TraceScalarId(0),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(0),
|
||||
ty: UInt<4>,
|
||||
},
|
||||
state: 0xa,
|
||||
last_state: 0x3,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(1),
|
||||
kind: BigSInt {
|
||||
index: StatePartIndex<BigSlots>(1),
|
||||
ty: SInt<2>,
|
||||
},
|
||||
state: 0x2,
|
||||
last_state: 0x3,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(2),
|
||||
kind: BigSInt {
|
||||
index: StatePartIndex<BigSlots>(2),
|
||||
ty: SInt<2>,
|
||||
},
|
||||
state: 0x2,
|
||||
last_state: 0x2,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(3),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(3),
|
||||
ty: UInt<4>,
|
||||
},
|
||||
state: 0xf,
|
||||
last_state: 0xe,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(4),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(8),
|
||||
ty: UInt<4>,
|
||||
},
|
||||
state: 0xa,
|
||||
last_state: 0x3,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(5),
|
||||
kind: BigSInt {
|
||||
index: StatePartIndex<BigSlots>(9),
|
||||
ty: SInt<2>,
|
||||
},
|
||||
state: 0x2,
|
||||
last_state: 0x3,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(6),
|
||||
kind: BigSInt {
|
||||
index: StatePartIndex<BigSlots>(10),
|
||||
ty: SInt<2>,
|
||||
},
|
||||
state: 0x2,
|
||||
last_state: 0x2,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(7),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(11),
|
||||
ty: UInt<4>,
|
||||
},
|
||||
state: 0xf,
|
||||
last_state: 0xe,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(8),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(4),
|
||||
ty: UInt<4>,
|
||||
},
|
||||
state: 0xa,
|
||||
last_state: 0x3,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(9),
|
||||
kind: BigSInt {
|
||||
index: StatePartIndex<BigSlots>(5),
|
||||
ty: SInt<2>,
|
||||
},
|
||||
state: 0x2,
|
||||
last_state: 0x3,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(10),
|
||||
kind: BigSInt {
|
||||
index: StatePartIndex<BigSlots>(6),
|
||||
ty: SInt<2>,
|
||||
},
|
||||
state: 0x2,
|
||||
last_state: 0x2,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(11),
|
||||
kind: BigUInt {
|
||||
index: StatePartIndex<BigSlots>(7),
|
||||
ty: UInt<4>,
|
||||
},
|
||||
state: 0xf,
|
||||
last_state: 0xe,
|
||||
},
|
||||
],
|
||||
trace_writers: [
|
||||
Running(
|
||||
VcdWriter {
|
||||
finished_init: true,
|
||||
timescale: 1 ps,
|
||||
..
|
||||
},
|
||||
),
|
||||
],
|
||||
instant: 2 μs,
|
||||
clocks_triggered: [],
|
||||
}
|
||||
47
crates/fayalite/tests/sim/expected/mod1.vcd
Normal file
47
crates/fayalite/tests/sim/expected/mod1.vcd
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
$timescale 1 ps $end
|
||||
$scope module mod1 $end
|
||||
$scope struct o $end
|
||||
$var wire 4 ! i $end
|
||||
$var wire 2 " o $end
|
||||
$var wire 2 # i2 $end
|
||||
$var wire 4 $ o2 $end
|
||||
$upscope $end
|
||||
$scope struct child $end
|
||||
$var wire 4 ) i $end
|
||||
$var wire 2 * o $end
|
||||
$var wire 2 + i2 $end
|
||||
$var wire 4 , o2 $end
|
||||
$upscope $end
|
||||
$scope module mod1_child $end
|
||||
$var wire 4 % i $end
|
||||
$var wire 2 & o $end
|
||||
$var wire 2 ' i2 $end
|
||||
$var wire 4 ( o2 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
b11 !
|
||||
b11 "
|
||||
b10 #
|
||||
b1110 $
|
||||
b11 %
|
||||
b11 &
|
||||
b10 '
|
||||
b1110 (
|
||||
b11 )
|
||||
b11 *
|
||||
b10 +
|
||||
b1110 ,
|
||||
$end
|
||||
#1000000
|
||||
b1010 !
|
||||
b10 "
|
||||
b1111 $
|
||||
b1010 %
|
||||
b10 &
|
||||
b1111 (
|
||||
b1010 )
|
||||
b10 *
|
||||
b1111 ,
|
||||
#2000000
|
||||
670
crates/fayalite/tests/sim/expected/shift_register.txt
Normal file
670
crates/fayalite/tests/sim/expected/shift_register.txt
Normal file
|
|
@ -0,0 +1,670 @@
|
|||
Simulation {
|
||||
state: State {
|
||||
insns: Insns {
|
||||
state_layout: StateLayout {
|
||||
ty: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 4,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 13,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
|
||||
ty: Clock,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
|
||||
ty: SyncReset,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3",
|
||||
ty: Bool,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
},
|
||||
insns: [
|
||||
// at: module-XXXXXXXXXX.rs:13:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:12:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:10:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:8:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:6:1
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:5:1
|
||||
IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
Const {
|
||||
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
value: 0,
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:5:1
|
||||
IsNonZeroDestIsSmall {
|
||||
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
|
||||
},
|
||||
AndSmall {
|
||||
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
BranchIfSmallZero {
|
||||
target: 14,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
BranchIfSmallNonZero {
|
||||
target: 13,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
|
||||
},
|
||||
Branch {
|
||||
target: 14,
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:7:1
|
||||
BranchIfSmallZero {
|
||||
target: 19,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
BranchIfSmallNonZero {
|
||||
target: 18,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
|
||||
},
|
||||
Branch {
|
||||
target: 19,
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:9:1
|
||||
BranchIfSmallZero {
|
||||
target: 24,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
BranchIfSmallNonZero {
|
||||
target: 23,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
|
||||
},
|
||||
Branch {
|
||||
target: 24,
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:11:1
|
||||
BranchIfSmallZero {
|
||||
target: 29,
|
||||
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
BranchIfSmallNonZero {
|
||||
target: 28,
|
||||
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
|
||||
},
|
||||
Branch {
|
||||
target: 29,
|
||||
},
|
||||
Copy {
|
||||
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
|
||||
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:5:1
|
||||
NotSmall {
|
||||
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
|
||||
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
|
||||
},
|
||||
// at: module-XXXXXXXXXX.rs:1:1
|
||||
Return,
|
||||
],
|
||||
..
|
||||
},
|
||||
pc: 30,
|
||||
small_slots: StatePart {
|
||||
value: [
|
||||
18446744073709551614,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
],
|
||||
},
|
||||
big_slots: StatePart {
|
||||
value: [
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
],
|
||||
},
|
||||
},
|
||||
io: Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
},
|
||||
uninitialized_inputs: {},
|
||||
io_targets: {
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.cd: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: SyncReset,
|
||||
},
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 2,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
|
||||
ty: Clock,
|
||||
},
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Bundle {
|
||||
fields: [
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
CompiledBundleField {
|
||||
offset: TypeIndex {
|
||||
small_slots: StatePartIndex<SmallSlots>(0),
|
||||
big_slots: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
ty: CompiledTypeLayout {
|
||||
ty: SyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
},
|
||||
],
|
||||
},
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.cd.clk: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Clock,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: Clock,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.cd.rst: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: SyncReset,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "",
|
||||
ty: SyncReset,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.d: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bool,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
Instance {
|
||||
name: <simulator>::shift_register,
|
||||
instantiated: Module {
|
||||
name: shift_register,
|
||||
..
|
||||
},
|
||||
}.q: CompiledValue {
|
||||
layout: CompiledTypeLayout {
|
||||
ty: Bool,
|
||||
layout: TypeLayout {
|
||||
small_slots: StatePartAllocationLayout<SmallSlots> {
|
||||
len: 0,
|
||||
debug_data: [],
|
||||
..
|
||||
},
|
||||
big_slots: StatePartAllocationLayout<BigSlots> {
|
||||
len: 1,
|
||||
debug_data: [
|
||||
SlotDebugData {
|
||||
name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
..
|
||||
},
|
||||
},
|
||||
body: Scalar,
|
||||
},
|
||||
range: TypeIndexRange {
|
||||
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
||||
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
||||
},
|
||||
write: None,
|
||||
},
|
||||
},
|
||||
made_initial_step: true,
|
||||
needs_settle: false,
|
||||
trace_decls: TraceModule {
|
||||
name: "shift_register",
|
||||
children: [
|
||||
TraceModuleIO {
|
||||
name: "cd",
|
||||
child: TraceBundle {
|
||||
name: "cd",
|
||||
fields: [
|
||||
TraceClock {
|
||||
id: TraceScalarId(0),
|
||||
name: "clk",
|
||||
flow: Source,
|
||||
},
|
||||
TraceSyncReset {
|
||||
id: TraceScalarId(1),
|
||||
name: "rst",
|
||||
flow: Source,
|
||||
},
|
||||
],
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: SyncReset,
|
||||
},
|
||||
flow: Source,
|
||||
},
|
||||
ty: Bundle {
|
||||
/* offset = 0 */
|
||||
clk: Clock,
|
||||
/* offset = 1 */
|
||||
rst: SyncReset,
|
||||
},
|
||||
flow: Source,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "d",
|
||||
child: TraceBool {
|
||||
id: TraceScalarId(2),
|
||||
name: "d",
|
||||
flow: Source,
|
||||
},
|
||||
ty: Bool,
|
||||
flow: Source,
|
||||
},
|
||||
TraceModuleIO {
|
||||
name: "q",
|
||||
child: TraceBool {
|
||||
id: TraceScalarId(3),
|
||||
name: "q",
|
||||
flow: Sink,
|
||||
},
|
||||
ty: Bool,
|
||||
flow: Sink,
|
||||
},
|
||||
TraceReg {
|
||||
name: "reg0",
|
||||
child: TraceBool {
|
||||
id: TraceScalarId(4),
|
||||
name: "reg0",
|
||||
flow: Duplex,
|
||||
},
|
||||
ty: Bool,
|
||||
},
|
||||
TraceReg {
|
||||
name: "reg1",
|
||||
child: TraceBool {
|
||||
id: TraceScalarId(5),
|
||||
name: "reg1",
|
||||
flow: Duplex,
|
||||
},
|
||||
ty: Bool,
|
||||
},
|
||||
TraceReg {
|
||||
name: "reg2",
|
||||
child: TraceBool {
|
||||
id: TraceScalarId(6),
|
||||
name: "reg2",
|
||||
flow: Duplex,
|
||||
},
|
||||
ty: Bool,
|
||||
},
|
||||
TraceReg {
|
||||
name: "reg3",
|
||||
child: TraceBool {
|
||||
id: TraceScalarId(7),
|
||||
name: "reg3",
|
||||
flow: Duplex,
|
||||
},
|
||||
ty: Bool,
|
||||
},
|
||||
],
|
||||
},
|
||||
traces: [
|
||||
SimTrace {
|
||||
id: TraceScalarId(0),
|
||||
kind: BigClock {
|
||||
index: StatePartIndex<BigSlots>(0),
|
||||
},
|
||||
state: 0x1,
|
||||
last_state: 0x1,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(1),
|
||||
kind: BigSyncReset {
|
||||
index: StatePartIndex<BigSlots>(1),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(2),
|
||||
kind: BigBool {
|
||||
index: StatePartIndex<BigSlots>(2),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(3),
|
||||
kind: BigBool {
|
||||
index: StatePartIndex<BigSlots>(3),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(4),
|
||||
kind: BigBool {
|
||||
index: StatePartIndex<BigSlots>(4),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(5),
|
||||
kind: BigBool {
|
||||
index: StatePartIndex<BigSlots>(7),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(6),
|
||||
kind: BigBool {
|
||||
index: StatePartIndex<BigSlots>(9),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
SimTrace {
|
||||
id: TraceScalarId(7),
|
||||
kind: BigBool {
|
||||
index: StatePartIndex<BigSlots>(11),
|
||||
},
|
||||
state: 0x0,
|
||||
last_state: 0x0,
|
||||
},
|
||||
],
|
||||
trace_writers: [
|
||||
Running(
|
||||
VcdWriter {
|
||||
finished_init: true,
|
||||
timescale: 1 ps,
|
||||
..
|
||||
},
|
||||
),
|
||||
],
|
||||
instant: 66 μs,
|
||||
clocks_triggered: [
|
||||
StatePartIndex<SmallSlots>(1),
|
||||
],
|
||||
}
|
||||
193
crates/fayalite/tests/sim/expected/shift_register.vcd
Normal file
193
crates/fayalite/tests/sim/expected/shift_register.vcd
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
$timescale 1 ps $end
|
||||
$scope module shift_register $end
|
||||
$scope struct cd $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 1 " rst $end
|
||||
$upscope $end
|
||||
$var wire 1 # d $end
|
||||
$var wire 1 $ q $end
|
||||
$var reg 1 % reg0 $end
|
||||
$var reg 1 & reg1 $end
|
||||
$var reg 1 ' reg2 $end
|
||||
$var reg 1 ( reg3 $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
0!
|
||||
1"
|
||||
0#
|
||||
0$
|
||||
0%
|
||||
0&
|
||||
0'
|
||||
0(
|
||||
$end
|
||||
#1000000
|
||||
1!
|
||||
#1100000
|
||||
0"
|
||||
#2000000
|
||||
0!
|
||||
#3000000
|
||||
1!
|
||||
#4000000
|
||||
0!
|
||||
1#
|
||||
#5000000
|
||||
1!
|
||||
1%
|
||||
#6000000
|
||||
0!
|
||||
#7000000
|
||||
1!
|
||||
1&
|
||||
#8000000
|
||||
0!
|
||||
0#
|
||||
#9000000
|
||||
1!
|
||||
0%
|
||||
1'
|
||||
#10000000
|
||||
0!
|
||||
#11000000
|
||||
1!
|
||||
0&
|
||||
1(
|
||||
1$
|
||||
#12000000
|
||||
0!
|
||||
1#
|
||||
#13000000
|
||||
1!
|
||||
1%
|
||||
0'
|
||||
#14000000
|
||||
0!
|
||||
0#
|
||||
#15000000
|
||||
1!
|
||||
0%
|
||||
1&
|
||||
0(
|
||||
0$
|
||||
#16000000
|
||||
0!
|
||||
1#
|
||||
#17000000
|
||||
1!
|
||||
1%
|
||||
0&
|
||||
1'
|
||||
#18000000
|
||||
0!
|
||||
#19000000
|
||||
1!
|
||||
1&
|
||||
0'
|
||||
1(
|
||||
1$
|
||||
#20000000
|
||||
0!
|
||||
#21000000
|
||||
1!
|
||||
1'
|
||||
0(
|
||||
0$
|
||||
#22000000
|
||||
0!
|
||||
#23000000
|
||||
1!
|
||||
1(
|
||||
1$
|
||||
#24000000
|
||||
0!
|
||||
0#
|
||||
#25000000
|
||||
1!
|
||||
0%
|
||||
#26000000
|
||||
0!
|
||||
#27000000
|
||||
1!
|
||||
0&
|
||||
#28000000
|
||||
0!
|
||||
#29000000
|
||||
1!
|
||||
0'
|
||||
#30000000
|
||||
0!
|
||||
#31000000
|
||||
1!
|
||||
0(
|
||||
0$
|
||||
#32000000
|
||||
0!
|
||||
#33000000
|
||||
1!
|
||||
#34000000
|
||||
0!
|
||||
#35000000
|
||||
1!
|
||||
#36000000
|
||||
0!
|
||||
#37000000
|
||||
1!
|
||||
#38000000
|
||||
0!
|
||||
#39000000
|
||||
1!
|
||||
#40000000
|
||||
0!
|
||||
#41000000
|
||||
1!
|
||||
#42000000
|
||||
0!
|
||||
#43000000
|
||||
1!
|
||||
#44000000
|
||||
0!
|
||||
#45000000
|
||||
1!
|
||||
#46000000
|
||||
0!
|
||||
#47000000
|
||||
1!
|
||||
#48000000
|
||||
0!
|
||||
#49000000
|
||||
1!
|
||||
#50000000
|
||||
0!
|
||||
#51000000
|
||||
1!
|
||||
#52000000
|
||||
0!
|
||||
#53000000
|
||||
1!
|
||||
#54000000
|
||||
0!
|
||||
#55000000
|
||||
1!
|
||||
#56000000
|
||||
0!
|
||||
#57000000
|
||||
1!
|
||||
#58000000
|
||||
0!
|
||||
#59000000
|
||||
1!
|
||||
#60000000
|
||||
0!
|
||||
#61000000
|
||||
1!
|
||||
#62000000
|
||||
0!
|
||||
#63000000
|
||||
1!
|
||||
#64000000
|
||||
0!
|
||||
#65000000
|
||||
1!
|
||||
#66000000
|
||||
Loading…
Add table
Add a link
Reference in a new issue