fayalite/crates/fayalite/tests/sim/expected/shift_register.vcd

194 lines
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$timescale 1 ps $end
$scope module shift_register $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$upscope $end
$var wire 1 # d $end
$var wire 1 $ q $end
$var reg 1 % reg0 $end
$var reg 1 & reg1 $end
$var reg 1 ' reg2 $end
$var reg 1 ( reg3 $end
$upscope $end
$enddefinitions $end
$dumpvars
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$end
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