decode some more add instructions

decodes an addi instruction
WIP adding simple power isa decoder
2026-01-15 16:10:03 -08:00 · 2026-01-14 21:41:25 -08:00 · 2026-01-12 07:10:58 -08:00 · 2026-01-12 03:31:06 -08:00 · 2026-01-09 02:05:08 -08:00 · 2026-01-09 02:03:59 -08:00
30 changed files with 315028 additions and 2059 deletions
--- a/.forgejo/workflows/deps.yml
+++ b/.forgejo/workflows/deps.yml
@ -1,77 +0,0 @@
-# SPDX-License-Identifier: LGPL-3.0-or-later
-# See Notices.txt for copyright information
-on:
-  workflow_call:
-    outputs:
-      cache-primary-key:
-        value: ${{ jobs.deps.outputs.cache-primary-key }}
-
-jobs:
-  deps:
-    runs-on: debian-12
-    outputs:
-      cache-primary-key: ${{ steps.restore-deps.outputs.cache-primary-key }}
-    steps:
-      - uses: https://git.libre-chip.org/mirrors/checkout@v3
-        with:
-          fetch-depth: 0
-      - uses: https://git.libre-chip.org/mirrors/cache/restore@v3
-        id: restore-deps
-        with:
-          path: deps
-          key: ${{ github.repository }}-deps-${{ runner.os }}-${{ hashFiles('.forgejo/workflows/deps.yml') }}
-          lookup-only: true
-      - name: Install Apt packages
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        run: |
-          apt-get update -qq
-          apt-get install -qq \
-            bison \
-            build-essential \
-            ccache \
-            clang \
-            cvc5 \
-            flex \
-            gawk \
-            g++ \
-            git \
-            libboost-filesystem-dev \
-            libboost-python-dev \
-            libboost-system-dev \
-            libffi-dev \
-            libreadline-dev \
-            lld \
-            pkg-config \
-            python3 \
-            python3-click \
-            tcl-dev \
-            zlib1g-dev
-      - name: Install Firtool
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        run: |
-          mkdir -p deps
-          wget -O deps/firrtl.tar.gz https://github.com/llvm/circt/releases/download/firtool-1.86.0/firrtl-bin-linux-x64.tar.gz
-          sha256sum -c - <<<'bf6f4ab18ae76f135c944efbd81e25391c31c1bd0617c58ab0592640abefee14  deps/firrtl.tar.gz'
-          tar -C deps -xvaf deps/firrtl.tar.gz
-          rm -rf deps/firtool
-          mv deps/firtool-1.86.0 deps/firtool
-      - name: Get SymbiYosys
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        run: |
-          git clone --depth=1 --branch=yosys-0.45 https://git.libre-chip.org/mirrors/sby deps/sby
-      - name: Build Z3
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        run: |
-          git clone --depth=1 --recursive --branch=z3-4.13.3 https://git.libre-chip.org/mirrors/z3 deps/z3
-          (cd deps/z3; PYTHON=python3 ./configure --prefix=/usr/local)
-          make -C deps/z3/build -j"$(nproc)"
-      - name: Build Yosys
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        run: |
-          git clone --depth=1 --recursive --branch=0.45 https://git.libre-chip.org/mirrors/yosys deps/yosys
-          make -C deps/yosys -j"$(nproc)"
-      - uses: https://git.libre-chip.org/mirrors/cache/save@v3
-        if: steps.restore-deps.outputs.cache-hit != 'true'
-        with:
-          path: deps
-          key: ${{ steps.restore-deps.outputs.cache-primary-key }}
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@ -3,56 +3,16 @@
 on: [push, pull_request]

 jobs:
-  deps:
-    runs-on: debian-12
-    uses: ./.forgejo/workflows/deps.yml
  test:
    runs-on: debian-12
-    needs: deps
+    container:
+      image: git.libre-chip.org/libre-chip/fayalite-deps:latest
    steps:
-      - uses: https://git.libre-chip.org/mirrors/checkout@v3
+      - uses: actions/checkout@v3
        with:
          fetch-depth: 0
      - run: |
          scripts/check-copyright.sh
-      - run: |
-          apt-get update -qq
-          apt-get install -qq \
-            bison \
-            build-essential \
-            ccache \
-            clang \
-            cvc5 \
-            flex \
-            gawk \
-            git \
-            libboost-filesystem-dev \
-            libboost-python-dev \
-            libboost-system-dev \
-            libffi-dev \
-            libreadline-dev \
-            lld \
-            pkg-config \
-            python3 \
-            python3-click \
-            tcl-dev \
-            z3 \
-            zlib1g-dev
-      - run: |
-          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.89.0
-          source "$HOME/.cargo/env"
-          echo "$PATH" >> "$GITHUB_PATH"
-      - uses: https://git.libre-chip.org/mirrors/cache/restore@v3
-        with:
-          path: deps
-          key: ${{ needs.deps.outputs.cache-primary-key }}
-          fail-on-cache-miss: true
-      - run: |
-          make -C deps/z3/build install
-          make -C deps/sby install
-          make -C deps/yosys install
-          export PATH="$(realpath deps/firtool/bin):$PATH"
-          echo "$PATH" >> "$GITHUB_PATH"
      - uses: https://git.libre-chip.org/mirrors/rust-cache@v2
        with:
          save-if: ${{ github.ref == 'refs/heads/master' }}
--- a/Cargo.lock
+++ b/Cargo.lock
@ -1,17 +1,20 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
-version = 3
+version = 4

 [[package]]
-name = "ahash"
-version = "0.8.11"
+name = "adler2"
+version = "2.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e89da841a80418a9b391ebaea17f5c112ffaaa96f621d2c285b5174da76b9011"
+checksum = "320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa"
+
+[[package]]
+name = "aho-corasick"
+version = "1.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301"
 dependencies = [
- "cfg-if",
- "once_cell",
- "version_check",
- "zerocopy",
+ "memchr",
 ]

 [[package]]
@ -93,6 +96,36 @@ version = "0.2.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "4c7f02d4ea65f2c1853089ffd8d2787bdbc63de2f0d29dedbcf8ccdfa0ccd4cf"

+[[package]]
+name = "base16ct"
+version = "1.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fd307490d624467aa6f74b0eabb77633d1f758a7b25f12bceb0b22e08d9726f6"
+
+[[package]]
+name = "base64"
+version = "0.22.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "72b3254f16251a8381aa12e40e3c4d2f0199f8c6508fbecb9d91f575e0fbb8c6"
+
+[[package]]
+name = "bindgen"
+version = "0.71.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5f58bf3d7db68cfbac37cfc485a8d711e87e064c3d0fe0435b92f7a407f9d6b3"
+dependencies = [
+ "bitflags",
+ "cexpr",
+ "clang-sys",
+ "itertools",
+ "proc-macro2",
+ "quote",
+ "regex",
+ "rustc-hash",
+ "shlex",
+ "syn",
+]
+
 [[package]]
 name = "bitflags"
 version = "2.6.0"
@ -136,20 +169,47 @@ dependencies = [
 ]

 [[package]]
-name = "cc"
-version = "1.1.28"
+name = "bytes"
+version = "1.11.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2e80e3b6a3ab07840e1cae9b0666a63970dc28e8ed5ffbcdacbfc760c281bfc1"
+checksum = "b35204fbdc0b3f4446b89fc1ac2cf84a8a68971995d0bf2e925ec7cd960f9cb3"
+
+[[package]]
+name = "cc"
+version = "1.2.51"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a0aeaff4ff1a90589618835a598e545176939b97874f7abc7851caa0618f203"
 dependencies = [
+ "find-msvc-tools",
 "shlex",
 ]

+[[package]]
+name = "cexpr"
+version = "0.6.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6fac387a98bb7c37292057cffc56d62ecb629900026402633ae9160df93a8766"
+dependencies = [
+ "nom",
+]
+
 [[package]]
 name = "cfg-if"
 version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"

+[[package]]
+name = "clang-sys"
+version = "1.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0b023947811758c97c59bf9d1c188fd619ad4718dcaa767947df1cadb14f39f4"
+dependencies = [
+ "glob",
+ "libc",
+ "libloading",
+]
+
 [[package]]
 name = "clap"
 version = "4.5.20"
@ -172,6 +232,15 @@ dependencies = [
 "strsim",
 ]

+[[package]]
+name = "clap_complete"
+version = "4.5.59"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2348487adcd4631696ced64ccdb40d38ac4d31cae7f2eec8817fcea1b9d1c43c"
+dependencies = [
+ "clap",
+]
+
 [[package]]
 name = "clap_derive"
 version = "4.5.18"
@ -206,7 +275,17 @@ checksum = "7c74b8349d32d297c9134b8c88677813a227df8f779daa29bfc29c183fe3dca6"
 name = "cpu"
 version = "0.1.0"
 dependencies = [
+ "base16ct 1.0.0",
 "fayalite",
+ "hex-literal",
+ "parse_powerisa_pdf",
+ "regex",
+ "roxmltree",
+ "serde",
+ "sha2",
+ "simple-mermaid",
+ "ureq",
+ "which",
 ]

 [[package]]
@ -218,6 +297,15 @@ dependencies = [
 "libc",
 ]

+[[package]]
+name = "crc32fast"
+version = "1.5.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511"
+dependencies = [
+ "cfg-if",
+]
+
 [[package]]
 name = "crypto-common"
 version = "0.1.6"
@ -273,12 +361,12 @@ checksum = "5443807d6dff69373d433ab9ef5378ad8df50ca6298caf15de6e52e24aaf54d5"

 [[package]]
 name = "errno"
-version = "0.3.9"
+version = "0.3.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "534c5cf6194dfab3db3242765c03bbe257cf92f22b38f6bc0c58d59108a820ba"
+checksum = "39cab71617ae0d63f51a36d69f866391735b51691dbda63cf6f96d042b63efeb"
 dependencies = [
 "libc",
- "windows-sys 0.52.0",
+ "windows-sys 0.61.2",
 ]

 [[package]]
@ -300,20 +388,22 @@ checksum = "e8c02a5121d4ea3eb16a80748c74f5549a5665e4c21333c6098f283870fbdea6"
 [[package]]
 name = "fayalite"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#bd75fdfefd642f6dd2210cfb003fa63f9dce114e"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#c97b44d9d646a4aa64fcc046538fc2354bb708ee"
 dependencies = [
+ "base64",
 "bitvec",
 "blake3",
 "clap",
+ "clap_complete",
 "ctor",
 "eyre",
 "fayalite-proc-macros",
 "fayalite-visit-gen",
- "hashbrown",
+ "hashbrown 0.15.5",
 "jobslot",
 "num-bigint",
 "num-traits",
- "os_pipe",
+ "ordered-float",
 "petgraph",
 "serde",
 "serde_json",
@ -325,7 +415,7 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#bd75fdfefd642f6dd2210cfb003fa63f9dce114e"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#c97b44d9d646a4aa64fcc046538fc2354bb708ee"
 dependencies = [
 "fayalite-proc-macros-impl",
 ]
@ -333,9 +423,9 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros-impl"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#bd75fdfefd642f6dd2210cfb003fa63f9dce114e"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#c97b44d9d646a4aa64fcc046538fc2354bb708ee"
 dependencies = [
- "base16ct",
+ "base16ct 0.2.0",
 "num-bigint",
 "prettyplease",
 "proc-macro2",
@ -348,7 +438,7 @@ dependencies = [
 [[package]]
 name = "fayalite-visit-gen"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#bd75fdfefd642f6dd2210cfb003fa63f9dce114e"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#c97b44d9d646a4aa64fcc046538fc2354bb708ee"
 dependencies = [
 "indexmap",
 "prettyplease",
@ -360,12 +450,34 @@ dependencies = [
 "thiserror",
 ]

+[[package]]
+name = "find-msvc-tools"
+version = "0.1.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "645cbb3a84e60b7531617d5ae4e57f7e27308f6445f5abf653209ea76dec8dff"
+
 [[package]]
 name = "fixedbitset"
 version = "0.5.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "1d674e81391d1e1ab681a28d99df07927c6d4aa5b027d7da16ba32d1d21ecd99"

+[[package]]
+name = "flate2"
+version = "1.1.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bfe33edd8e85a12a67454e37f8c75e730830d83e313556ab9ebf9ee7fbeb3bfb"
+dependencies = [
+ "crc32fast",
+ "miniz_oxide",
+]
+
+[[package]]
+name = "foldhash"
+version = "0.1.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2"
+
 [[package]]
 name = "funty"
 version = "2.0.0"
@ -384,9 +496,9 @@ dependencies = [

 [[package]]
 name = "getrandom"
-version = "0.2.15"
+version = "0.2.16"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c4567c8db10ae91089c99af84c68c38da3ec2f087c3f82960bcdbf3656b6f4d7"
+checksum = "335ff9f135e4384c8150d6f27c6daed433577f86b4750418338c01a1a2528592"
 dependencies = [
 "cfg-if",
 "libc",
@ -394,21 +506,52 @@ dependencies = [
 ]

 [[package]]
-name = "hashbrown"
-version = "0.14.5"
+name = "getrandom"
+version = "0.3.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e5274423e17b7c9fc20b6e7e208532f9b19825d82dfd615708b70edd83df41f1"
+checksum = "899def5c37c4fd7b2664648c28120ecec138e4d395b459e5ca34f9cce2dd77fd"
 dependencies = [
- "ahash",
- "allocator-api2",
+ "cfg-if",
+ "libc",
+ "r-efi",
+ "wasip2",
 ]

+[[package]]
+name = "glob"
+version = "0.3.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0cc23270f6e1808e30a928bdc84dea0b9b4136a8bc82338574f23baf47bbd280"
+
+[[package]]
+name = "hashbrown"
+version = "0.15.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9229cfe53dfd69f0609a49f65461bd93001ea1ef889cd5529dd176593f5338a1"
+dependencies = [
+ "allocator-api2",
+ "equivalent",
+ "foldhash",
+]
+
+[[package]]
+name = "hashbrown"
+version = "0.16.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100"
+
 [[package]]
 name = "heck"
 version = "0.5.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "2304e00983f87ffb38b55b444b5e3b60a884b5d30c0fca7d82fe33449bbe55ea"

+[[package]]
+name = "hex-literal"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e712f64ec3850b98572bffac52e2c6f282b29fe6c5fa6d42334b30be438d95c1"
+
 [[package]]
 name = "home"
 version = "0.5.9"
@ -418,6 +561,22 @@ dependencies = [
 "windows-sys 0.52.0",
 ]

+[[package]]
+name = "http"
+version = "1.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e3ba2a386d7f85a81f119ad7498ebe444d2e22c2af0b86b069416ace48b3311a"
+dependencies = [
+ "bytes",
+ "itoa",
+]
+
+[[package]]
+name = "httparse"
+version = "1.10.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6dbf3de79e51f3d586ab4cb9d5c3e2c14aa28ed23d180cf89b4df0454a69cc87"
+
 [[package]]
 name = "indenter"
 version = "0.3.3"
@ -426,13 +585,14 @@ checksum = "ce23b50ad8242c51a442f3ff322d56b02f08852c77e4c0b4d3fd684abc89c683"

 [[package]]
 name = "indexmap"
-version = "2.5.0"
+version = "2.13.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "68b900aa2f7301e21c36462b170ee99994de34dff39a4a6a528e80e7376d07e5"
+checksum = "7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017"
 dependencies = [
 "equivalent",
- "hashbrown",
+ "hashbrown 0.16.1",
 "serde",
+ "serde_core",
 ]

 [[package]]
@ -441,6 +601,15 @@ version = "1.70.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7943c866cc5cd64cbc25b2e01621d07fa8eb2a1a23160ee81ce38704e97b8ecf"

+[[package]]
+name = "itertools"
+version = "0.13.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "413ee7dfc52ee1a4949ceeb7dbc8a33f2d6c088194d9f922fb8318faf1f01186"
+dependencies = [
+ "either",
+]
+
 [[package]]
 name = "itoa"
 version = "1.0.11"
@ -449,23 +618,39 @@ checksum = "49f1f14873335454500d59611f1cf4a4b0f786f9ac11f4312a78e4cf2566695b"

 [[package]]
 name = "jobslot"
-version = "0.2.19"
+version = "0.2.23"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "fe10868679d7a24c2c67d862d0e64a342ce9aef7cdde9ce8019bd35d353d458d"
+checksum = "58715c67c327da7f1558708348d68c207fd54900c4ae0529e29305d04d795b8c"
 dependencies = [
 "cfg-if",
 "derive_destructure2",
- "getrandom",
+ "getrandom 0.3.4",
 "libc",
 "scopeguard",
- "windows-sys 0.59.0",
+ "windows-sys 0.61.2",
 ]

 [[package]]
 name = "libc"
-version = "0.2.159"
+version = "0.2.180"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "561d97a539a36e26a9a5fad1ea11a3039a67714694aaa379433e580854bc3dc5"
+checksum = "bcc35a38544a891a5f7c865aca548a982ccb3b8650a5b06d0fd33a10283c56fc"
+
+[[package]]
+name = "libloading"
+version = "0.8.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d7c4b02199fee7c5d21a5ae7d8cfa79a6ef5bb2fc834d6e9058e89c825efdc55"
+dependencies = [
+ "cfg-if",
+ "windows-link",
+]
+
+[[package]]
+name = "libm"
+version = "0.2.15"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f9fbbcab51052fe104eb5e5d351cf728d30a5be1fe14d9be8a3b097481fb97de"

 [[package]]
 name = "linux-raw-sys"
@ -473,12 +658,57 @@ version = "0.4.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "78b3ae25bc7c8c38cec158d1f2757ee79e9b3740fbc7ccf0e59e4b08d793fa89"

+[[package]]
+name = "log"
+version = "0.4.29"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5e5032e24019045c762d3c0f28f5b6b8bbf38563a65908389bf7978758920897"
+
 [[package]]
 name = "memchr"
 version = "2.7.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "78ca9ab1a0babb1e7d5695e3530886289c18cf2f87ec19a575a0abdce112e3a3"

+[[package]]
+name = "minimal-lexical"
+version = "0.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "68354c5c6bd36d73ff3feceb05efa59b6acb7626617f4962be322a825e61f79a"
+
+[[package]]
+name = "miniz_oxide"
+version = "0.8.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316"
+dependencies = [
+ "adler2",
+ "simd-adler32",
+]
+
+[[package]]
+name = "mupdf-sys"
+version = "0.5.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "13e9a0d4e844ab50315d43312f3d62f72c77205b07c8ee21cbd4b52bdc2a9910"
+dependencies = [
+ "bindgen",
+ "cc",
+ "pkg-config",
+ "regex",
+ "zerocopy",
+]
+
+[[package]]
+name = "nom"
+version = "7.1.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d273983c5a657a70a3e8f2a01329822f3b8c8172b73826411a55751e404a0a4a"
+dependencies = [
+ "memchr",
+ "minimal-lexical",
+]
+
 [[package]]
 name = "num-bigint"
 version = "0.4.6"
@ -514,24 +744,51 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "1261fe7e33c73b354eab43b1273a57c8f967d0391e80353e51f764ac02cf6775"

 [[package]]
-name = "os_pipe"
-version = "1.2.1"
+name = "ordered-float"
+version = "5.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5ffd2b0a5634335b135d5728d84c5e0fd726954b87111f7506a61c502280d982"
+checksum = "7f4779c6901a562440c3786d08192c6fbda7c1c2060edd10006b05ee35d10f2d"
 dependencies = [
- "libc",
- "windows-sys 0.59.0",
+ "num-traits",
+ "rand",
+ "serde",
 ]

+[[package]]
+name = "parse_powerisa_pdf"
+version = "0.1.0"
+source = "git+https://git.libre-chip.org/libre-chip/parse_powerisa_pdf.git?branch=master#38a1fb328bd44f26389c28fbf66716154f4113dc"
+dependencies = [
+ "indexmap",
+ "libm",
+ "mupdf-sys",
+ "quick-xml",
+]
+
+[[package]]
+name = "percent-encoding"
+version = "2.3.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9b4f627cb1b25917193a259e49bdad08f671f8d9708acfd5fe0a8c1455d87220"
+
 [[package]]
 name = "petgraph"
-version = "0.6.5"
-source = "git+https://github.com/programmerjake/petgraph.git?rev=258ea8071209a924b73fe96f9f87a3b7b45cbc9f#258ea8071209a924b73fe96f9f87a3b7b45cbc9f"
+version = "0.8.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8701b58ea97060d5e5b155d383a69952a60943f0e6dfe30b04c287beb0b27455"
 dependencies = [
 "fixedbitset",
+ "hashbrown 0.15.5",
 "indexmap",
+ "serde",
 ]

+[[package]]
+name = "pkg-config"
+version = "0.3.32"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7edddbd0b52d732b21ad9a5fab5c704c14cd949e5e9a1ec5929a24fded1b904c"
+
 [[package]]
 name = "prettyplease"
 version = "0.2.22"
@ -551,6 +808,15 @@ dependencies = [
 "unicode-ident",
 ]

+[[package]]
+name = "quick-xml"
+version = "0.38.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b66c2058c55a409d601666cffe35f04333cf1013010882cec174a7467cd4e21c"
+dependencies = [
+ "memchr",
+]
+
 [[package]]
 name = "quote"
 version = "1.0.37"
@ -560,12 +826,95 @@ dependencies = [
 "proc-macro2",
 ]

+[[package]]
+name = "r-efi"
+version = "5.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f"
+
 [[package]]
 name = "radium"
 version = "0.7.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "dc33ff2d4973d518d823d61aa239014831e521c75da58e3df4840d3f47749d09"

+[[package]]
+name = "rand"
+version = "0.8.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "34af8d1a0e25924bc5b7c43c079c942339d8f0a8b57c39049bef581b46327404"
+dependencies = [
+ "rand_core",
+ "serde",
+]
+
+[[package]]
+name = "rand_core"
+version = "0.6.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c"
+dependencies = [
+ "serde",
+]
+
+[[package]]
+name = "regex"
+version = "1.12.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "843bc0191f75f3e22651ae5f1e72939ab2f72a4bc30fa80a066bd66edefc24d4"
+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-automata",
+ "regex-syntax",
+]
+
+[[package]]
+name = "regex-automata"
+version = "0.4.13"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5276caf25ac86c8d810222b3dbb938e512c55c6831a10f3e6ed1c93b84041f1c"
+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-syntax",
+]
+
+[[package]]
+name = "regex-syntax"
+version = "0.8.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a2d987857b319362043e95f5353c0535c1f58eec5336fdfcf626430af7def58"
+
+[[package]]
+name = "ring"
+version = "0.17.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a4689e6c2294d81e88dc6261c768b63bc4fcdb852be6d1352498b114f61383b7"
+dependencies = [
+ "cc",
+ "cfg-if",
+ "getrandom 0.2.16",
+ "libc",
+ "untrusted",
+ "windows-sys 0.52.0",
+]
+
+[[package]]
+name = "roxmltree"
+version = "0.21.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f1964b10c76125c36f8afe190065a4bf9a87bf324842c05701330bba9f1cacbb"
+dependencies = [
+ "memchr",
+]
+
+[[package]]
+name = "rustc-hash"
+version = "2.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "357703d41365b4b27c590e3ed91eabb1b663f07c4c084095e60cbed4362dff0d"
+
 [[package]]
 name = "rustix"
 version = "0.38.37"
@ -579,6 +928,41 @@ dependencies = [
 "windows-sys 0.52.0",
 ]

+[[package]]
+name = "rustls"
+version = "0.23.36"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c665f33d38cea657d9614f766881e4d510e0eda4239891eea56b4cadcf01801b"
+dependencies = [
+ "log",
+ "once_cell",
+ "ring",
+ "rustls-pki-types",
+ "rustls-webpki",
+ "subtle",
+ "zeroize",
+]
+
+[[package]]
+name = "rustls-pki-types"
+version = "1.13.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "21e6f2ab2928ca4291b86736a8bd920a277a399bba1589409d72154ff87c1282"
+dependencies = [
+ "zeroize",
+]
+
+[[package]]
+name = "rustls-webpki"
+version = "0.103.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2ffdfa2f5286e2247234e03f680868ac2815974dc39e00ea15adc445d0aafe52"
+dependencies = [
+ "ring",
+ "rustls-pki-types",
+ "untrusted",
+]
+
 [[package]]
 name = "ryu"
 version = "1.0.18"
@ -593,18 +977,28 @@ checksum = "94143f37725109f92c262ed2cf5e59bce7498c01bcc1502d7b9afe439a4e9f49"

 [[package]]
 name = "serde"
-version = "1.0.210"
+version = "1.0.228"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c8e3592472072e6e22e0a54d5904d9febf8508f65fb8552499a1abc7d1078c3a"
+checksum = "9a8e94ea7f378bd32cbbd37198a4a91436180c5bb472411e48b5ec2e2124ae9e"
+dependencies = [
+ "serde_core",
+ "serde_derive",
+]
+
+[[package]]
+name = "serde_core"
+version = "1.0.228"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "41d385c7d4ca58e59fc732af25c3983b67ac852c1a25000afe1175de458b67ad"
 dependencies = [
 "serde_derive",
 ]

 [[package]]
 name = "serde_derive"
-version = "1.0.210"
+version = "1.0.228"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "243902eda00fad750862fc144cea25caca5e20d615af0a81bee94ca738f1df1f"
+checksum = "d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79"
 dependencies = [
 "proc-macro2",
 "quote",
@ -626,9 +1020,9 @@ dependencies = [

 [[package]]
 name = "sha2"
-version = "0.10.8"
+version = "0.10.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "793db75ad2bcafc3ffa7c68b215fee268f537982cd901d132f89c6343f3a3dc8"
+checksum = "a7507d819769d01a365ab707794a4084392c824f54a7a6a7862f8c3d0892b283"
 dependencies = [
 "cfg-if",
 "cpufeatures",
@ -641,12 +1035,30 @@ version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64"

+[[package]]
+name = "simd-adler32"
+version = "0.3.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e320a6c5ad31d271ad523dcf3ad13e2767ad8b1cb8f047f75a8aeaf8da139da2"
+
+[[package]]
+name = "simple-mermaid"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "589144a964b4b30fe3a83b4bb1a09e2475aac194ec832a046a23e75bddf9eb29"
+
 [[package]]
 name = "strsim"
 version = "0.11.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"

+[[package]]
+name = "subtle"
+version = "2.6.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292"
+
 [[package]]
 name = "syn"
 version = "2.0.96"
@ -709,6 +1121,47 @@ version = "1.0.13"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "e91b56cd4cadaeb79bbf1a5645f6b4f8dc5bde8834ad5894a8db35fda9efa1fe"

+[[package]]
+name = "untrusted"
+version = "0.9.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8ecb6da28b8a351d773b68d5825ac39017e680750f980f3a1a85cd8dd28a47c1"
+
+[[package]]
+name = "ureq"
+version = "3.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d39cb1dbab692d82a977c0392ffac19e188bd9186a9f32806f0aaa859d75585a"
+dependencies = [
+ "base64",
+ "flate2",
+ "log",
+ "percent-encoding",
+ "rustls",
+ "rustls-pki-types",
+ "ureq-proto",
+ "utf-8",
+ "webpki-roots",
+]
+
+[[package]]
+name = "ureq-proto"
+version = "0.5.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d81f9efa9df032be5934a46a068815a10a042b494b6a58cb0a1a97bb5467ed6f"
+dependencies = [
+ "base64",
+ "http",
+ "httparse",
+ "log",
+]
+
+[[package]]
+name = "utf-8"
+version = "0.7.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "09cc8ee72d2a9becf2f2febe0205bbed8fc6615b7cb429ad062dc7b7ddd036a9"
+
 [[package]]
 name = "utf8parse"
 version = "0.2.2"
@ -729,9 +1182,27 @@ checksum = "0b928f33d975fc6ad9f86c8f283853ad26bdd5b10b7f1542aa2fa15e2289105a"

 [[package]]
 name = "wasi"
-version = "0.11.0+wasi-snapshot-preview1"
+version = "0.11.1+wasi-snapshot-preview1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9c8d87e72b64a3b4db28d11ce29237c246188f4f51057d65a7eab63b7987e423"
+checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b"
+
+[[package]]
+name = "wasip2"
+version = "1.0.1+wasi-0.2.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0562428422c63773dad2c345a1882263bbf4d65cf3f42e90921f787ef5ad58e7"
+dependencies = [
+ "wit-bindgen",
+]
+
+[[package]]
+name = "webpki-roots"
+version = "1.0.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "12bed680863276c63889429bfd6cab3b99943659923822de1c8a39c49e4d722c"
+dependencies = [
+ "rustls-pki-types",
+]

 [[package]]
 name = "which"
@ -741,10 +1212,17 @@ checksum = "b4ee928febd44d98f2f459a4a79bd4d928591333a494a10a868418ac1b39cf1f"
 dependencies = [
 "either",
 "home",
+ "regex",
 "rustix",
 "winsafe",
 ]

+[[package]]
+name = "windows-link"
+version = "0.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5"
+
 [[package]]
 name = "windows-sys"
 version = "0.52.0"
@ -763,6 +1241,15 @@ dependencies = [
 "windows-targets",
 ]

+[[package]]
+name = "windows-sys"
+version = "0.61.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc"
+dependencies = [
+ "windows-link",
+]
+
 [[package]]
 name = "windows-targets"
 version = "0.52.6"
@ -833,6 +1320,12 @@ version = "0.0.19"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "d135d17ab770252ad95e9a872d365cf3090e3be864a34ab46f48555993efc904"

+[[package]]
+name = "wit-bindgen"
+version = "0.46.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f17a85883d4e6d00e8a97c586de764dabcc06133f7f1d55dce5cdc070ad7fe59"
+
 [[package]]
 name = "wyz"
 version = "0.5.1"
@ -844,20 +1337,26 @@ dependencies = [

 [[package]]
 name = "zerocopy"
-version = "0.7.35"
+version = "0.8.27"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1b9b4fd18abc82b8136838da5d50bae7bdea537c574d8dc1a34ed098d6c166f0"
+checksum = "0894878a5fa3edfd6da3f88c4805f4c8558e2b996227a3d864f47fe11e38282c"
 dependencies = [
 "zerocopy-derive",
 ]

 [[package]]
 name = "zerocopy-derive"
-version = "0.7.35"
+version = "0.8.27"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "fa4f8080344d4671fb4e831a13ad1e68092748387dfc4f55e356242fae12ce3e"
+checksum = "88d2b8d9c68ad2b9e4340d7832716a4d21a22a1154777ad56ea55c51a9cf3831"
 dependencies = [
 "proc-macro2",
 "quote",
 "syn",
 ]
+
+[[package]]
+name = "zeroize"
+version = "1.8.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b97154e67e32c85465826e8bcc1c59429aaaf107c1e4a9e53c8d8ccd5eff88d0"
--- a/Cargo.toml
+++ b/Cargo.toml
@ -14,7 +14,16 @@ categories = []
 rust-version = "1.89.0"

 [workspace.dependencies]
+base16ct = "1.0.0"
 fayalite = { git = "https://git.libre-chip.org/libre-chip/fayalite.git", version = "0.3.0", branch = "master" }
+hex-literal = "1.1.0"
+parse_powerisa_pdf = { git = "https://git.libre-chip.org/libre-chip/parse_powerisa_pdf.git", version = "0.1.0", branch = "master" }
+roxmltree = "0.21.1"
+serde = { version = "1.0.202", features = ["derive"] }
+sha2 = "0.10.9"
+simple-mermaid = "0.2.0"
+ureq = "3.1.4"
+which = { version = "6.0.3", features = ["regex"] }

 [profile.dev]
 opt-level = 1
--- a/README.md
+++ b/README.md
@ -0,0 +1,15 @@
+<!--
+SPDX-License-Identifier: LGPL-3.0-or-later
+See Notices.txt for copyright information
+-->
+# Libre-Chip's CPU
+
+<https://libre-chip.org/first_arch/index.html>
+
+# Funding
+
+## NLnet Grants
+
+* [Libre-Chip CPU with proof of No Spectre bugs](https://nlnet.nl/project/Libre-Chip-proof/) 2024-12-324 [(progress)](https://git.libre-chip.org/libre-chip/grant-tracking/src/branch/master/nlnet-2024-12-324/progress.md)
+
+This project was funded through the [NGI0 Commons Fund](https://nlnet.nl/commonsfund), a fund established by [NLnet](https://nlnet.nl/) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) programme, under the aegis of [DG Communications Networks, Content and Technology](https://commission.europa.eu/about-european-commission/departments-and-executive-agencies/communications-networks-content-and-technology_en) under grant agreement &numero; [101135429](https://cordis.europa.eu/project/id/101135429). Additional funding is made available by the [Swiss State Secretariat for Education, Research and Innovation](https://www.sbfi.admin.ch/sbfi/en/home.html) (SERI).
--- a/crates/cpu/Cargo.toml
+++ b/crates/cpu/Cargo.toml
@ -16,3 +16,20 @@ version.workspace = true

 [dependencies]
 fayalite.workspace = true
+roxmltree.workspace = true
+serde.workspace = true
+simple-mermaid.workspace = true
+
+[build-dependencies]
+base16ct.workspace = true
+hex-literal.workspace = true
+parse_powerisa_pdf.workspace = true
+sha2.workspace = true
+ureq.workspace = true
+
+[dev-dependencies]
+base16ct.workspace = true
+hex-literal.workspace = true
+regex = "1.12.2"
+sha2.workspace = true
+which.workspace = true
--- a/crates/cpu/README.md
+++ b/crates/cpu/README.md
@ -0,0 +1 @@
+../../README.md
--- a/crates/cpu/build.rs
+++ b/crates/cpu/build.rs
@ -0,0 +1,96 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use parse_powerisa_pdf::parse_powerisa_pdf_and_generate_xml;
+use sha2::{Digest, Sha256};
+use std::{
+    error::Error,
+    io::{ErrorKind, Read},
+    path::Path,
+};
+
+const EXPECTED_FILE_SIZE: u64 = 6425593;
+const EXPECTED_FILE_HASH: &[u8; 32] =
+    &hex_literal::hex!("56372d23ece7e9e2c1b381a639443982a3e16e38109df1c141d655b779b61fdb");
+
+fn verify_powerisa_file(file: impl std::io::Read) -> Result<Vec<u8>, Box<dyn Error>> {
+    let mut buf = Vec::with_capacity(usize::try_from(EXPECTED_FILE_SIZE)? + 1);
+    file.take(EXPECTED_FILE_SIZE + 1).read_to_end(&mut buf)?;
+    if buf.len() > EXPECTED_FILE_SIZE as usize {
+        Err(format!("file is bigger than the expected length {EXPECTED_FILE_SIZE}").into())
+    } else if buf.len() < EXPECTED_FILE_SIZE as usize {
+        Err(format!(
+            "file is smaller than the expected length {EXPECTED_FILE_SIZE}: actual length {}",
+            buf.len()
+        )
+        .into())
+    } else {
+        let hash = Sha256::digest(&buf);
+        let hash = &*hash;
+        if hash != EXPECTED_FILE_HASH {
+            Err(format!(
+                "file's SHA256 hash doesn't match the expected hash: expected: {:x} got: {:x}",
+                base16ct::HexDisplay(EXPECTED_FILE_HASH),
+                base16ct::HexDisplay(hash)
+            )
+            .into())
+        } else {
+            Ok(buf)
+        }
+    }
+}
+
+fn is_powerisa_pdf(path: impl AsRef<Path>) -> Result<bool, Box<dyn Error>> {
+    let path = path.as_ref();
+    let metadata = match std::fs::metadata(path) {
+        Err(e) if e.kind() == ErrorKind::NotFound => return Ok(false),
+        v => v?,
+    };
+    if !metadata.is_file() {
+        return Ok(false);
+    }
+    let file = std::fs::File::open(path)?;
+    verify_powerisa_file(file)?;
+    Ok(true)
+}
+
+fn out_dir() -> String {
+    std::env::var("OUT_DIR").expect("OUT_DIR env var is not set or invalid")
+}
+
+fn get_powerisa_pdf_name_and_dir<'a>(
+    out_dir: &'a str,
+) -> Result<(&'static str, &'a Path), Box<dyn Error>> {
+    const FILE_NAME: &str = "OPF_PowerISA_v3.1C.pdf";
+    let out_dir = Path::new(out_dir);
+    if is_powerisa_pdf(FILE_NAME)? {
+        println!("cargo::rerun-if-changed={FILE_NAME}");
+        return Ok((FILE_NAME, Path::new(".")));
+    }
+    let full_path = out_dir.join(FILE_NAME);
+    let full_path = full_path
+        .into_os_string()
+        .into_string()
+        .expect("should be valid UTF-8");
+    if is_powerisa_pdf(&full_path)? {
+        println!("cargo::rerun-if-changed={full_path}");
+        return Ok((FILE_NAME, out_dir));
+    }
+    const URL: &str = "https://libre-chip.org/OPF_PowerISA_v3.1C.pdf";
+    println!("cargo::warning={FILE_NAME} not found locally, downloading from {URL}");
+    let buf = verify_powerisa_file(ureq::get(URL).call()?.into_body().into_reader())?;
+    std::fs::write(&full_path, buf)?;
+    println!("cargo::rerun-if-changed={full_path}");
+    Ok((FILE_NAME, out_dir))
+}
+
+fn main() -> Result<(), Box<dyn Error>> {
+    let out_dir = out_dir();
+    let (pdf_name, pdf_dir) = get_powerisa_pdf_name_and_dir(&out_dir)?;
+    let old_dir = std::env::current_dir()?;
+    std::env::set_current_dir(pdf_dir)?;
+    let xml = parse_powerisa_pdf_and_generate_xml(pdf_name, None, false)?;
+    std::env::set_current_dir(old_dir)?;
+    std::fs::write(Path::new(&out_dir).join("powerisa-instructions.xml"), xml)?;
+    Ok(())
+}
--- a/crates/cpu/src/config.rs
+++ b/crates/cpu/src/config.rs
@ -8,9 +8,10 @@ use crate::{
    },
 };
 use fayalite::prelude::*;
+use serde::{Deserialize, Serialize};
 use std::num::NonZeroUsize;

-#[derive(Clone, Eq, PartialEq, Hash, Debug)]
+#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)]
 #[non_exhaustive]
 pub struct UnitConfig {
    pub kind: UnitKind,
@ -27,12 +28,15 @@ impl UnitConfig {
    }
 }

-#[derive(Clone, Eq, PartialEq, Hash, Debug)]
+#[derive(Clone, Eq, PartialEq, Hash, Debug, Serialize, Deserialize)]
 #[non_exhaustive]
 pub struct CpuConfig {
    pub units: Vec<UnitConfig>,
    pub out_reg_num_width: usize,
    pub fetch_width: NonZeroUsize,
+    pub max_branches_per_fetch: NonZeroUsize,
+    pub max_fetches_in_flight: NonZeroUsize,
+    pub log2_fetch_width_in_bytes: u8,
    /// default value for [`UnitConfig::max_in_flight`]
    pub default_unit_max_in_flight: NonZeroUsize,
    pub rob_size: NonZeroUsize,
@ -46,6 +50,19 @@ impl CpuConfig {
        };
        v
    };
+    pub const DEFAULT_MAX_BRANCHES_PER_FETCH: NonZeroUsize = {
+        let Some(v) = NonZeroUsize::new(1) else {
+            unreachable!();
+        };
+        v
+    };
+    pub const DEFAULT_MAX_FETCHES_IN_FLIGHT: NonZeroUsize = {
+        let Some(v) = NonZeroUsize::new(16) else {
+            unreachable!();
+        };
+        v
+    };
+    pub const DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3;
    pub const DEFAULT_UNIT_MAX_IN_FLIGHT: NonZeroUsize = {
        let Some(v) = NonZeroUsize::new(8) else {
            unreachable!();
@ -57,6 +74,9 @@ impl CpuConfig {
            units,
            out_reg_num_width: Self::DEFAULT_OUT_REG_NUM_WIDTH,
            fetch_width: Self::DEFAULT_FETCH_WIDTH,
+            max_branches_per_fetch: Self::DEFAULT_MAX_BRANCHES_PER_FETCH,
+            max_fetches_in_flight: Self::DEFAULT_MAX_FETCHES_IN_FLIGHT,
+            log2_fetch_width_in_bytes: Self::DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES,
            default_unit_max_in_flight: Self::DEFAULT_UNIT_MAX_IN_FLIGHT,
            rob_size,
        }
@ -116,4 +136,42 @@ impl CpuConfig {
        UnitToRegAlloc[mop_ty][extra_out_ty][self.unit_num_width()][self.out_reg_num_width]
            [self.non_const_unit_nums().len()]
    }
+    pub fn fetch_width_in_bytes(&self) -> usize {
+        1usize
+            .checked_shl(self.log2_fetch_width_in_bytes.into())
+            .expect("log2_fetch_width_in_bytes is too big")
+    }
 }
+
+#[hdl(get(|c| c.fetch_width.get()))]
+pub type CpuConfigFetchWidth<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.fetch_width.get() * 2))]
+pub type TwiceCpuConfigFetchWidth<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.max_branches_per_fetch.get()))]
+pub type CpuConfigMaxBranchesPerFetch<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.max_fetches_in_flight.get()))]
+pub type CpuConfigMaxFetchesInFlight<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.log2_fetch_width_in_bytes.into()))]
+pub type CpuConfigLog2FetchWidthInBytes<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.fetch_width_in_bytes()))]
+pub type CpuConfigFetchWidthInBytes<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+#[hdl(get(|c| c.rob_size.get()))]
+pub type CpuConfigRobSize<C: PhantomConstGet<CpuConfig>> = DynSize;
+
+pub trait PhantomConstCpuConfig:
+    PhantomConstGet<CpuConfig>
+    + Into<PhantomConst<CpuConfig>>
+    + From<PhantomConst<CpuConfig>>
+    + Type
+    + ToSimValue<Type = Self>
+    + ToExpr<Type = Self>
+{
+}
+
+impl PhantomConstCpuConfig for PhantomConst<CpuConfig> {}
--- a/crates/cpu/src/decoder.rs
+++ b/crates/cpu/src/decoder.rs
@ -0,0 +1,4 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+pub mod simple_power_isa;
--- a/crates/cpu/src/decoder/simple_power_isa.rs
+++ b/crates/cpu/src/decoder/simple_power_isa.rs
--- a/crates/cpu/src/instruction.rs
+++ b/crates/cpu/src/instruction.rs
@ -2,11 +2,13 @@
 // See Notices.txt for copyright information
 use crate::{unit::UnitMOp, util::range_u32_len};
 use fayalite::{
-    expr::ops::{ArrayLiteral, ExprPartialEq},
+    expr::{HdlPartialEqImpl, ops::ArrayLiteral},
    intern::Interned,
+    module::wire_with_loc,
    prelude::*,
+    ty::StaticType,
 };
-use std::{fmt, marker::PhantomData, ops::Range};
+use std::{borrow::Cow, fmt, marker::PhantomData, ops::Range};

 pub mod power_isa;

@ -171,13 +173,37 @@ pub enum OutputIntegerMode {
    SignExt8,
 }

-impl ExprPartialEq<Self> for OutputIntegerMode {
-    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
+impl HdlPartialEqImpl<Self> for OutputIntegerMode {
+    #[track_caller]
+    fn cmp_value_eq(
+        lhs: Self,
+        lhs_value: Cow<'_, Self::SimValue>,
+        rhs: Self,
+        rhs_value: Cow<'_, Self::SimValue>,
+    ) -> bool {
+        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
+            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
    }

-    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_ne(rhs.cast_to_bits())
+    #[track_caller]
+    fn cmp_sim_value_eq(
+        lhs: Cow<'_, SimValue<Self>>,
+        rhs: Cow<'_, SimValue<Self>>,
+    ) -> SimValue<Bool> {
+        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
+    }
+
+    #[track_caller]
+    fn cmp_sim_value_ne(
+        lhs: Cow<'_, SimValue<Self>>,
+        rhs: Cow<'_, SimValue<Self>>,
+    ) -> SimValue<Bool> {
+        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
+    }
+
+    #[track_caller]
+    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
    }
 }

@ -289,8 +315,8 @@ impl<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize
        let dest = dest.to_expr();
        let src_in = src.to_expr();
        let imm = imm.to_expr();
-        assert_eq!(Expr::ty(imm), Self::imm_ty());
-        let src_reg_ty = Expr::ty(src_in).element();
+        assert_eq!(imm.ty(), Self::imm_ty());
+        let src_reg_ty = src_in.ty().element();
        let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty());
        let mut src = [0_hdl_u0.cast_to(src_reg_ty); COMMON_MOP_SRC_LEN];
        for i in 0..SrcCount::VALUE {
@ -334,9 +360,9 @@ impl<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize
    #[hdl]
    pub fn connect_to_imm(expr: impl ToExpr<Type = Self>, imm: impl ToExpr<Type = SInt>) {
        let expr = expr.to_expr();
-        let src_reg_ty = Expr::ty(expr).src.element();
+        let src_reg_ty = expr.ty().src.element();
        let imm = imm.to_expr();
-        assert_eq!(Expr::ty(imm), Self::imm_ty());
+        assert_eq!(imm.ty(), Self::imm_ty());
        let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty());
        let mut src = [Some(0_hdl_u0.cast_to(src_reg_ty)); COMMON_MOP_SRC_LEN];
        for i in 0..SrcCount::VALUE {
@ -489,7 +515,7 @@ macro_rules! mop_enum {
            fn dest_reg(input: impl ToExpr<Type = Self>) -> Expr<Self::DestReg> {
                let input = input.to_expr();
                #[hdl]
-                let dest_reg = wire(Expr::ty(input).dest_reg_ty());
+                let dest_reg = wire(input.ty().dest_reg_ty());
                #[hdl]
                match input {
                    Self::$FirstVariant(v) => connect(dest_reg, <$first_ty as MOpTrait>::dest_reg(v)),
@ -530,7 +556,7 @@ macro_rules! mop_enum {
            ) -> Expr<Self::Mapped<NewDestReg, NewSrcRegWidth>> {
                let input = input.to_expr();
                let new_dest = new_dest.to_expr();
-                let mapped_ty = Expr::ty(input).mapped_ty(Expr::ty(new_dest), new_src_reg_width);
+                let mapped_ty = input.ty().mapped_ty(new_dest.ty(), new_src_reg_width);
                #[hdl]
                let mapped_regs = wire(mapped_ty);
                #[hdl]
@ -577,7 +603,7 @@ macro_rules! mop_enum {
                MOpInto::mop_into_ty($MOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]$([$sizes_get_size(self)])*)
            }
            fn mop_into(this: Expr<Self>) -> Expr<Target> {
-                MOpInto::mop_into(MOpInto::<$MOp<$DestReg, $SrcRegWidth, $($Sizes,)*>>::mop_into_ty(Expr::ty(this)).$Variant(this))
+                MOpInto::mop_into(MOpInto::<$MOp<$DestReg, $SrcRegWidth, $($Sizes,)*>>::mop_into_ty(this.ty()).$Variant(this))
            }
        }
    };
@ -826,22 +852,19 @@ impl<Width: Size> UnitNum<Width> {
    }
    pub fn is_index(expr: impl ToExpr<Type = Self>, index: usize) -> Expr<Bool> {
        let expr = expr.to_expr();
-        Expr::ty(expr)
-            .from_index(index)
-            .adj_value
-            .cmp_eq(expr.adj_value)
+        expr.ty().from_index(index).adj_value.cmp_eq(expr.adj_value)
    }
    #[hdl]
    pub fn as_index(expr: impl ToExpr<Type = Self>) -> Expr<HdlOption<UIntType<Width>>> {
        let expr = expr.to_expr();
        #[hdl]
-        let unit_index = wire(HdlOption[Expr::ty(expr).adj_value]);
-        connect(unit_index, Expr::ty(unit_index).HdlNone());
+        let unit_index = wire(HdlOption[expr.ty().adj_value]);
+        connect(unit_index, unit_index.ty().HdlNone());
        #[hdl]
        if expr.adj_value.cmp_ne(0u8) {
            connect(
                unit_index,
-                HdlSome((expr.adj_value - 1u8).cast_to(Expr::ty(expr).adj_value)),
+                HdlSome((expr.adj_value - 1u8).cast_to(expr.ty().adj_value)),
            );
        }
        unit_index
@ -893,7 +916,7 @@ impl MOpRegNum {
    pub fn const_zero() -> Expr<Self> {
        #[hdl]
        MOpRegNum {
-            value: Self::CONST_ZERO_REG_NUM.cast_to_static(),
+            value: Self::CONST_ZERO_REG_NUM.cast_to_static::<UInt<_>>(),
        }
    }
    /// a lot of instructions write to flag registers that we want
@ -926,6 +949,87 @@ pub struct MOpDestReg {
    pub flag_regs: Array<HdlOption<()>, { range_u32_len(&MOpRegNum::FLAG_REG_NUMS) }>,
 }

+impl MOpDestReg {
+    #[hdl]
+    #[track_caller]
+    pub fn new_sim(normal_regs: &[u32], flag_regs: &[u32]) -> SimValue<Self> {
+        let zero_reg = MOpRegNum::const_zero().to_sim_value();
+        let mut normal_regs_sim = std::array::from_fn(|_| zero_reg.clone());
+        for (i, reg) in normal_regs.iter().copied().enumerate() {
+            let Some(normal_reg_sim) = normal_regs_sim.get_mut(i) else {
+                panic!("too many normal regs");
+            };
+            if reg >= 1 << MOpRegNum::WIDTH {
+                panic!("normal reg number out of range");
+            }
+            *normal_reg_sim.value = reg.cast_to_static::<UInt<_>>();
+        }
+        let mut flag_regs_sim = std::array::from_fn(|_| {
+            #[hdl(sim)]
+            HdlNone()
+        });
+        for &flag_reg in flag_regs {
+            let Some(index) = { MOpRegNum::FLAG_REG_NUMS }.position(|v| flag_reg == v) else {
+                panic!(
+                    "flag reg number {flag_reg} is out of range, supported range is: {:?}",
+                    MOpRegNum::FLAG_REG_NUMS
+                );
+            };
+            flag_regs_sim[index] = #[hdl(sim)]
+            HdlSome(());
+        }
+        #[hdl(sim)]
+        Self {
+            normal_regs: normal_regs_sim,
+            flag_regs: flag_regs_sim,
+        }
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn new(
+        normal_regs: impl IntoIterator<Item = Expr<MOpRegNum>>,
+        flag_regs: impl IntoIterator<Item = (u32, Expr<Bool>)>,
+    ) -> Expr<Self> {
+        let mut normal_regs_array = [MOpRegNum::const_zero(); Self::NORMAL_REG_COUNT];
+        const FLAG_REG_COUNT: usize = range_u32_len(&MOpRegNum::FLAG_REG_NUMS);
+        let mut used_flag_regs = [false; FLAG_REG_COUNT];
+        let mut flag_regs_array = [HdlNone(); FLAG_REG_COUNT];
+        for (i, normal_reg) in normal_regs.into_iter().enumerate() {
+            assert!(i < Self::NORMAL_REG_COUNT, "too many normal regs");
+            normal_regs_array[i] = normal_reg;
+        }
+        for (flag_reg_num, flag_reg_enabled) in flag_regs {
+            let Some(index) = { MOpRegNum::FLAG_REG_NUMS }.position(|v| flag_reg_num == v) else {
+                panic!(
+                    "flag reg number {flag_reg_num} is out of range, supported range is: {:?}",
+                    MOpRegNum::FLAG_REG_NUMS
+                );
+            };
+            assert!(
+                !used_flag_regs[index],
+                "duplicate flag reg number {flag_reg_num}"
+            );
+            used_flag_regs[index] = true;
+            let wire = wire_with_loc(
+                &format!("flag_reg_{index}"),
+                SourceLocation::caller(),
+                StaticType::TYPE,
+            );
+            connect(wire, HdlNone());
+            #[hdl]
+            if flag_reg_enabled {
+                connect(wire, HdlSome(()));
+            }
+            flag_regs_array[index] = wire;
+        }
+        #[hdl]
+        Self {
+            normal_regs: normal_regs_array,
+            flag_regs: flag_regs_array,
+        }
+    }
+}
+
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug)]
 pub enum RenameTableName {
    /// the large rename table for normal registers (has less read/write ports)
@ -1070,7 +1174,7 @@ impl MOpDestReg {
                        flag_reg,
                        #[hdl]
                        MOpRegNum {
-                            value: reg_num.cast_to_static(),
+                            value: reg_num.cast_to_static::<UInt<_>>(),
                        },
                    );
                }
--- a/crates/cpu/src/instruction/power_isa.rs
+++ b/crates/cpu/src/instruction/power_isa.rs
@ -29,24 +29,150 @@ impl MOpRegNum {
    pub const POWER_ISA_LR_REG_NUM: u32 = 1;
    pub const POWER_ISA_CTR_REG_NUM: u32 = 2;
    pub const POWER_ISA_TAR_REG_NUM: u32 = 3;
-    /// XER bits are stored in [`PRegValue.flags`], bits that don't exist in [`PRegValue.flags`] are stored in [`PRegValue.int_fp`]
+
+    /// SO, OV, and OV32 XER bits -- in [`PRegValue.flags`]
    ///
    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
-    /// [`PRegValue.int_fp`]: struct@crate::register::PRegValue
-    pub const POWER_ISA_XER_REG_NUM: u32 = 4;
+    pub const POWER_ISA_XER_SO_OV_OV32_REG_NUM: u32 =
+        range_u32_nth_or_panic(&Self::FLAG_REG_NUMS, 0);
+    /// CA and CA32 XER bits -- in [`PRegValue.flags`]
+    ///
+    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
+    pub const POWER_ISA_XER_CA_CA32_REG_NUM: u32 = 4;
+    /// only the XER bits that don't exist in [`PRegValue.flags`]
+    ///
+    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
+    pub const POWER_ISA_XER_OTHER_REG_NUM: u32 = 5;

-    pub const POWER_ISA_CR_REG_NUMS: Range<u32> = 8..16;
+    /// SO, OV, and OV32 XER bits -- in [`PRegValue.flags`]
+    ///
+    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
+    #[hdl]
+    pub fn power_isa_xer_so_ov_ov32_reg() -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::POWER_ISA_XER_SO_OV_OV32_REG_NUM.cast_to_static::<UInt<_>>(),
+        }
+    }
+    /// CA and CA32 XER bits -- in [`PRegValue.flags`]
+    ///
+    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
+    #[hdl]
+    pub fn power_isa_xer_ca_ca32_reg() -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::POWER_ISA_XER_CA_CA32_REG_NUM.cast_to_static::<UInt<_>>(),
+        }
+    }
+    /// only the XER bits that don't exist in [`PRegValue.flags`]
+    ///
+    /// [`PRegValue.flags`]: struct@crate::register::PRegValue
+    #[hdl]
+    pub fn power_isa_xer_other_reg() -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: Self::POWER_ISA_XER_OTHER_REG_NUM.cast_to_static::<UInt<_>>(),
+        }
+    }
+
+    pub const POWER_ISA_CR_0_REG_NUM: u32 = range_u32_nth_or_panic(&Self::FLAG_REG_NUMS, 1);
+    pub const POWER_ISA_CR_1_THRU_7_REG_NUMS: Range<u32> = 9..16;
    pub const fn power_isa_cr_reg_num(index: usize) -> u32 {
-        range_u32_nth_or_panic(&Self::POWER_ISA_CR_REG_NUMS, index)
+        if index == 0 {
+            Self::POWER_ISA_CR_0_REG_NUM
+        } else {
+            range_u32_nth_or_panic(&Self::POWER_ISA_CR_1_THRU_7_REG_NUMS, index - 1)
+        }
+    }
+    #[hdl]
+    pub fn power_isa_cr_reg(field_num: Expr<UInt<3>>) -> Expr<Self> {
+        #[hdl]
+        let power_isa_cr_reg: Self = wire();
+        #[hdl]
+        if field_num.cmp_eq(0u8) {
+            connect_any(power_isa_cr_reg.value, Self::POWER_ISA_CR_0_REG_NUM);
+        } else {
+            connect_any(
+                power_isa_cr_reg.value,
+                Self::POWER_ISA_CR_1_THRU_7_REG_NUMS.start + field_num,
+            );
+        }
+        power_isa_cr_reg
+    }
+    #[hdl]
+    pub fn power_isa_cr_reg_sim(field_num: &SimValue<UInt<3>>) -> SimValue<Self> {
+        #[hdl(sim)]
+        Self {
+            value: Self::power_isa_cr_reg_num(
+                field_num.cast_to_static::<UInt<8>>().as_int() as usize
+            )
+            .cast_to_static::<UInt<_>>(),
+        }
    }

    pub const POWER_ISA_GPR_REG_NUMS: Range<u32> = 32..64;
    pub const fn power_isa_gpr_reg_num(index: usize) -> u32 {
        range_u32_nth_or_panic(&Self::POWER_ISA_GPR_REG_NUMS, index)
    }
+    #[hdl]
+    pub fn power_isa_gpr_reg(reg_num: Expr<UInt<5>>) -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: (Self::POWER_ISA_GPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
+        }
+    }
+    #[hdl]
+    pub fn power_isa_gpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
+        #[hdl(sim)]
+        Self {
+            value: (Self::POWER_ISA_GPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
+        }
+    }
+    pub const fn power_isa_gpr_or_zero_reg_num(index: usize) -> u32 {
+        if index == 0 {
+            Self::CONST_ZERO_REG_NUM
+        } else {
+            Self::power_isa_gpr_reg_num(index)
+        }
+    }
+    #[hdl]
+    pub fn power_isa_gpr_or_zero_reg(reg_num: Expr<UInt<5>>) -> Expr<Self> {
+        #[hdl]
+        let power_isa_gpr_or_zero_reg: Self = wire();
+        connect(power_isa_gpr_or_zero_reg, Self::power_isa_gpr_reg(reg_num));
+        #[hdl]
+        if reg_num.cmp_eq(0u8) {
+            connect(power_isa_gpr_or_zero_reg, Self::const_zero());
+        }
+        power_isa_gpr_or_zero_reg
+    }
+    #[hdl]
+    pub fn power_isa_gpr_or_zero_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
+        #[hdl(sim)]
+        Self {
+            value: Self::power_isa_gpr_or_zero_reg_num(
+                reg_num.cast_to_static::<UInt<8>>().as_int() as usize,
+            )
+            .cast_to_static::<UInt<_>>(),
+        }
+    }

    pub const POWER_ISA_FPR_REG_NUMS: Range<u32> = 64..96;
    pub const fn power_isa_fpr_reg_num(index: usize) -> u32 {
        range_u32_nth_or_panic(&Self::POWER_ISA_FPR_REG_NUMS, index)
    }
+    #[hdl]
+    pub fn power_isa_fpr_reg(reg_num: Expr<UInt<5>>) -> Expr<Self> {
+        #[hdl]
+        Self {
+            value: (Self::POWER_ISA_FPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
+        }
+    }
+    #[hdl]
+    pub fn power_isa_fpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
+        #[hdl(sim)]
+        Self {
+            value: (Self::POWER_ISA_FPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
+        }
+    }
 }
--- a/crates/cpu/src/lib.rs
+++ b/crates/cpu/src/lib.rs
@ -1,7 +1,10 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 pub mod config;
+pub mod decoder;
 pub mod instruction;
+pub mod next_pc;
+pub mod powerisa_instructions_xml;
 pub mod reg_alloc;
 pub mod register;
 pub mod unit;
--- a/crates/cpu/src/next_pc.rs
+++ b/crates/cpu/src/next_pc.rs
--- a/crates/cpu/src/next_pc/next_pc.mermaid
+++ b/crates/cpu/src/next_pc/next_pc.mermaid
@ -0,0 +1,24 @@
+%% SPDX-License-Identifier: LGPL-3.0-or-later
+%% See Notices.txt for copyright information
+stateDiagram-v2
+    direction LR
+
+    state "Next PC" as next_pc
+    [*] --> next_pc
+
+    state "Fetch/Decode" as fetch_decode
+    next_pc --> fetch_decode
+
+    state "Branch Predictor" as br_pred
+    next_pc --> br_pred
+    br_pred --> next_pc: cancel following
+
+    state "Post-decode" as post_decode
+    fetch_decode --> post_decode
+    br_pred --> post_decode
+    post_decode --> next_pc: cancel following
+
+    state "Execute/Retire" as execute_retire
+    post_decode --> execute_retire
+    execute_retire --> [*]
+    execute_retire --> next_pc: cancel following
--- a/crates/cpu/src/powerisa_instructions_xml.rs
+++ b/crates/cpu/src/powerisa_instructions_xml.rs
--- a/crates/cpu/src/reg_alloc.rs
+++ b/crates/cpu/src/reg_alloc.rs
@ -241,7 +241,7 @@ pub fn reg_alloc(config: &CpuConfig) {
        // TODO: finish
        connect(
            rob.renamed_insns_in[fetch_index].data,
-            Expr::ty(rob).renamed_insns_in.element().data.HdlNone(),
+            rob.ty().renamed_insns_in.element().data.HdlNone(),
        );
        // TODO: finish
        connect(
@ -263,7 +263,7 @@ pub fn reg_alloc(config: &CpuConfig) {
        );
        connect(
            renamed_mops[fetch_index],
-            Expr::ty(renamed_mops).element().HdlNone(),
+            renamed_mops.ty().element().HdlNone(),
        );
        #[hdl]
        struct RenameTableReadPort<T> {
@ -332,7 +332,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                let write_port = wire_with_loc(
                    &format!("{table_name}_{fetch_index}_{}", reg_kind.reg_name()),
                    SourceLocation::caller(),
-                    Expr::ty(write_port_),
+                    write_port_.ty(),
                );
                connect(write_port_, write_port);
                write_ports.push_back(write_port);
@ -343,7 +343,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                        addr: 0_hdl_u0,
                        en: false,
                        clk: cd.clk,
-                        data: Expr::ty(write_port.data).uninit(),
+                        data: write_port.data.ty().uninit(),
                        mask: splat_mask(config.p_reg_num(), true.to_expr()),
                    },
                );
@ -375,7 +375,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                    config.renamed_mop_in_unit().TransformedMove,
                    |renamed_mop, renamed_move_op: Expr<MoveRegMOp<_, _>>| {
                        // TODO: finish handling MoveRegMOp
-                        connect(renamed_mop, Expr::ty(renamed_mop).HdlNone());
+                        connect(renamed_mop, renamed_mop.ty().HdlNone());
                    },
                );
                connect(
@ -429,7 +429,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                    );
                    connect(
                        selected_unit_index_leaf,
-                        Expr::ty(selected_unit_index_leaf).HdlNone(),
+                        selected_unit_index_leaf.ty().HdlNone(),
                    );
                    let unit_index_wire = wire_with_loc(
                        &format!("unit_index_{fetch_index}_{unit_index}"),
@ -447,7 +447,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                    let selected_unit_index_node = wire_with_loc(
                        &format!("selected_unit_index_node_{fetch_index}_{state}"),
                        SourceLocation::caller(),
-                        Expr::ty(l),
+                        l.ty(),
                    );
                    *state += 1;
                    connect(selected_unit_index_node, l);
@ -516,7 +516,7 @@ pub fn reg_alloc(config: &CpuConfig) {
        connect(unit_free_regs_tracker.alloc_out[0].ready, false);
        connect(
            unit_to_reg_alloc.input.data,
-            Expr::ty(unit_to_reg_alloc.input).data.HdlNone(),
+            unit_to_reg_alloc.input.ty().data.HdlNone(),
        );
        for fetch_index in 0..config.fetch_width.get() {
            #[hdl]
@ -550,7 +550,7 @@ pub fn reg_alloc(config: &CpuConfig) {
                    } else {
                        connect(
                            unit_to_reg_alloc.input.data,
-                            HdlSome(Expr::ty(unit_to_reg_alloc.input).data.HdlSome.uninit()),
+                            HdlSome(unit_to_reg_alloc.input.ty().data.HdlSome.uninit()),
                        );
                        // FIXME: add hdl_assert(cd.clk, false.to_expr(), "");
                    }
@ -578,7 +578,8 @@ pub fn reg_alloc(config: &CpuConfig) {
        connect(unit_to_reg_alloc.unit_forwarding_info, unit_forwarding_info);
        connect(
            unit_forwarding_info.unit_output_writes[unit_index],
-            Expr::ty(unit_forwarding_info)
+            unit_forwarding_info
+                .ty()
                .unit_output_writes
                .element()
                .HdlNone(),
--- a/crates/cpu/src/reg_alloc/unit_free_regs_tracker.rs
+++ b/crates/cpu/src/reg_alloc/unit_free_regs_tracker.rs
@ -73,7 +73,7 @@ pub fn unit_free_regs_tracker(
            let reduced_alloc_nums = wire_with_loc(
                &format!("reduced_alloc_nums_{}_{}", range.start, range.end),
                SourceLocation::caller(),
-                Array[UInt[Expr::ty(l.alloc_nums).element().width() + 1]][alloc_at_once.get()],
+                Array[UInt[l.alloc_nums.ty().element().width() + 1]][alloc_at_once.get()],
            );
            for alloc_index in 0..alloc_at_once.get() {
                #[hdl]
@ -120,10 +120,7 @@ pub fn unit_free_regs_tracker(
 #[cfg(test)]
 mod tests {
    use super::*;
-    use fayalite::{
-        cli::FormalMode, firrtl::ExportOptions,
-        module::transform::simplify_enums::SimplifyEnumsKind, testing::assert_formal,
-    };
+    use fayalite::{firrtl::ExportOptions, module::transform::simplify_enums::SimplifyEnumsKind};
    use std::num::NonZero;

    fn test_unit_free_regs_tracker(
@ -198,7 +195,7 @@ mod tests {
                }
            }
            #[hdl]
-            let free_before_alloc_array = wire(Array[Expr::ty(free_reg)][alloc_at_once.get() + 1]);
+            let free_before_alloc_array = wire(Array[free_reg.ty()][alloc_at_once.get() + 1]);
            connect(free_before_alloc_array[0], free_reg);
            #[hdl]
            let expected_alloc = wire(Array[HdlOption[reg_num_ty]][alloc_at_once.get()]);
--- a/crates/cpu/src/unit.rs
+++ b/crates/cpu/src/unit.rs
@ -15,6 +15,7 @@ use fayalite::{
    intern::{Intern, Interned},
    prelude::*,
 };
+use serde::{Deserialize, Serialize};

 pub mod alu_branch;
 pub mod unit_base;
@ -36,7 +37,7 @@ macro_rules! all_units {
        }
    ) => {
        $(#[$enum_meta])*
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug, Serialize, Deserialize)]
        $vis enum $UnitKind {
            $(
                $(#[$variant_meta])*
@ -52,9 +53,16 @@ macro_rules! all_units {
            }
        }

-        impl ToExpr for $UnitKind {
+        impl ValueType for $UnitKind {
            type Type = $HdlUnitKind;
+            type ValueCategory = fayalite::expr::value_category::ValueCategoryExpr;

+            fn ty(&self) -> Self::Type {
+                $HdlUnitKind
+            }
+        }
+
+        impl ToExpr for $UnitKind {
            fn to_expr(&self) -> Expr<Self::Type> {
                match self {
                    $($UnitKind::$Unit => $HdlUnitKind.$Unit(),)*
@ -98,7 +106,7 @@ macro_rules! all_units {
                #[hdl]
                $vis fn $extract(expr: impl ToExpr<Type = Self>) -> Expr<HdlOption<$Op>> {
                    let expr = expr.to_expr();
-                    let ty = Expr::ty(expr);
+                    let ty = expr.ty();
                    #[hdl]
                    let $extract = wire(HdlOption[ty.$Unit]);
                    connect($extract, HdlOption[ty.$Unit].HdlNone());
@ -164,10 +172,10 @@ macro_rules! all_units {
                $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
            {
                let this = this.to_expr();
-                let new_ty = Expr::ty(this).with_transformed_move_op_ty(new_transformed_move_op_ty);
+                let new_ty = this.ty().with_transformed_move_op_ty(new_transformed_move_op_ty);
                #[hdl]
                let with_transformed_move_op = wire(HdlOption[new_ty]);
-                connect(with_transformed_move_op, Expr::ty(with_transformed_move_op).HdlNone());
+                connect(with_transformed_move_op, with_transformed_move_op.ty().HdlNone());
                // workaround #[hdl] match expanding to a loop, so you can't move variables in it
                let mut connect_transformed_move_op = Some(connect_transformed_move_op);
                #[hdl]
@ -209,7 +217,7 @@ macro_rules! all_units {
                RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]
            }
            fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> {
-                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(Expr::ty(this)).$BeforeUnit(this)
+                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$BeforeUnit(this)
            }
        })*

@ -218,7 +226,7 @@ macro_rules! all_units {
                RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]
            }
            fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> {
-                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(Expr::ty(this)).$AfterUnit(this)
+                MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$AfterUnit(this)
            }
        })*
    };
--- a/crates/cpu/src/unit/alu_branch.rs
+++ b/crates/cpu/src/unit/alu_branch.rs
@ -266,16 +266,13 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) {
    let unit_base = instance(unit_base(
        config,
        unit_index,
-        Expr::ty(unit_to_reg_alloc).input.data.HdlSome.mop,
+        unit_to_reg_alloc.ty().input.data.HdlSome.mop,
        (),
    ));
    connect(unit_to_reg_alloc, unit_base.unit_to_reg_alloc);
    connect(unit_base.cd, cd);
    connect(unit_base.execute_start.ready, true);
-    connect(
-        unit_base.execute_end,
-        Expr::ty(unit_base.execute_end).HdlNone(),
-    );
+    connect(unit_base.execute_end, unit_base.execute_end.ty().HdlNone());
    #[hdl]
    if let HdlSome(execute_start) = ReadyValid::firing_data(unit_base.execute_start) {
        #[hdl]
--- a/crates/cpu/src/unit/unit_base.rs
+++ b/crates/cpu/src/unit/unit_base.rs
@ -227,7 +227,7 @@ impl InFlightOpsSummary<DynSize> {
        in_flight_ops: impl ToExpr<Type = ArrayType<HdlOption<InFlightOp<MOp>>, MaxInFlight>>,
    ) -> Expr<Self> {
        let in_flight_ops = in_flight_ops.to_expr();
-        let max_in_flight = Expr::ty(in_flight_ops).len();
+        let max_in_flight = in_flight_ops.ty().len();
        let index_range = 0..max_in_flight;
        let index_ty = UInt::range(index_range.clone());
        tree_reduce(
@ -259,7 +259,7 @@ pub fn unit_base<
    let execute_end: HdlOption<ExecuteEnd<DynSize, ExtraOut>> =
        m.input(HdlOption[ExecuteEnd[config.out_reg_num_width][extra_out_ty]]);

-    connect(execute_start.data, Expr::ty(execute_start).data.HdlNone());
+    connect(execute_start.data, execute_start.ty().data.HdlNone());

    let max_in_flight = config.unit_max_in_flight(unit_index).get();
    let in_flight_op_ty = InFlightOp[mop_ty];
@ -270,7 +270,7 @@ pub fn unit_base<

    let in_flight_ops_summary_value = InFlightOpsSummary::summarize(in_flight_ops);
    #[hdl]
-    let in_flight_ops_summary = wire(Expr::ty(in_flight_ops_summary_value));
+    let in_flight_ops_summary = wire(in_flight_ops_summary_value.ty());
    connect(in_flight_ops_summary, in_flight_ops_summary_value);

    connect(
@ -302,7 +302,7 @@ pub fn unit_base<
    #[hdl]
    let input_src_regs_valid = wire();
    connect(input_src_regs_valid, [true; COMMON_MOP_SRC_LEN]);
-    let mut unit_output_regs_valid: Vec<MemBuilder<Bool>> = (0..Expr::ty(unit_output_writes).len())
+    let mut unit_output_regs_valid: Vec<MemBuilder<Bool>> = (0..unit_output_writes.ty().len())
        .map(|unit_index| {
            let mut mem = memory_with_loc(
                &format!("unit_{unit_index}_output_regs_valid"),
@ -313,7 +313,7 @@ pub fn unit_base<
            mem
        })
        .collect();
-    for unit_index in 0..Expr::ty(unit_output_writes).len() {
+    for unit_index in 0..unit_output_writes.ty().len() {
        let mut unit_output_regs = memory_with_loc(
            &format!("unit_{unit_index}_output_regs"),
            PRegValue,
@ -411,7 +411,7 @@ pub fn unit_base<

    connect(
        unit_to_reg_alloc.output,
-        Expr::ty(unit_to_reg_alloc.output).HdlNone(),
+        unit_to_reg_alloc.output.ty().HdlNone(),
    );

    #[hdl]
@ -503,7 +503,7 @@ pub fn unit_base<

            #[hdl]
            if in_flight_ops_summary.ready_op_index.cmp_eq(HdlSome(
-                in_flight_op_index.cast_to(Expr::ty(in_flight_ops_summary).ready_op_index.HdlSome),
+                in_flight_op_index.cast_to(in_flight_ops_summary.ty().ready_op_index.HdlSome),
            )) {
                connect(read_src_regs, src_regs);
            }
@ -512,7 +512,7 @@ pub fn unit_base<
                in_flight_op_next_src_ready_flags[in_flight_op_index],
                src_ready_flags,
            );
-            for unit_index in 0..Expr::ty(unit_output_writes).len() {
+            for unit_index in 0..unit_output_writes.ty().len() {
                #[hdl]
                if let HdlSome(unit_output_write) = unit_output_writes[unit_index] {
                    #[hdl]
--- a/crates/cpu/src/util/array_vec.rs
+++ b/crates/cpu/src/util/array_vec.rs
@ -1,147 +1,10 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information

-use fayalite::{
-    expr::ops::{ExprCastTo, ExprIndex, ExprPartialEq, ExprPartialOrd},
-    int::SizeType,
-    intern::{Intern, Interned},
-    prelude::*,
-    ty::{MatchVariantWithoutScope, StaticType, TypeProperties},
-};
-use std::{marker::PhantomData, ops::Index};
+use fayalite::{expr::ops::ExprIndex, int::UIntInRangeInclusiveType, prelude::*};

-#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
-pub struct Length<Max: Size> {
-    ty: UInt,
-    _phantom: PhantomData<Max>,
-}
-
-impl<Max: Size> Length<Max> {
-    pub fn new(max: Max::SizeType) -> Self {
-        Self {
-            ty: UInt::range_inclusive(0..=Max::as_usize(max)),
-            _phantom: PhantomData,
-        }
-    }
-    pub fn ty(self) -> UInt {
-        self.ty
-    }
-    pub fn zero(self) -> Expr<Self> {
-        Self::from_uint_unchecked(self.ty.zero())
-    }
-    pub fn from_uint_unchecked(v: impl ToExpr<Type = UInt>) -> Expr<Self> {
-        Expr::from_canonical(Expr::canonical(v.to_expr()))
-    }
-    pub fn cast_from_uint_unchecked<SrcWidth: Size>(
-        self,
-        v: impl ToExpr<Type = UIntType<SrcWidth>>,
-    ) -> Expr<Self> {
-        Self::from_uint_unchecked(v.to_expr().cast_to(self.ty))
-    }
-    pub fn as_uint(this: impl ToExpr<Type = Self>) -> Expr<UInt> {
-        let this = this.to_expr();
-        this.cast_to(Expr::ty(this).ty)
-    }
-}
-
-impl<Max: Size, DestWidth: Size> ExprCastTo<UIntType<DestWidth>> for Length<Max> {
-    fn cast_to(src: Expr<Self>, to_type: UIntType<DestWidth>) -> Expr<UIntType<DestWidth>> {
-        Expr::<UInt>::from_canonical(Expr::canonical(src)).cast_to(to_type)
-    }
-}
-
-#[allow(non_upper_case_globals)]
-pub const Length: __LengthWithoutGenerics = __LengthWithoutGenerics {};
-
-#[non_exhaustive]
-pub struct __LengthWithoutGenerics {}
-
-impl<M: SizeType> Index<M> for __LengthWithoutGenerics {
-    type Output = Length<M::Size>;
-
-    fn index(&self, max: M) -> &Self::Output {
-        Interned::into_inner(Length::new(max).intern_sized())
-    }
-}
-
-impl<Max: Size> Type for Length<Max> {
-    type BaseType = UInt;
-    type MaskType = Bool;
-    type MatchVariant = Expr<Self>;
-    type MatchActiveScope = ();
-    type MatchVariantAndInactiveScope = MatchVariantWithoutScope<Self::MatchVariant>;
-    type MatchVariantsIter = std::iter::Once<Self::MatchVariantAndInactiveScope>;
-    fn match_variants(
-        this: Expr<Self>,
-        source_location: SourceLocation,
-    ) -> Self::MatchVariantsIter {
-        let _ = source_location;
-        std::iter::once(MatchVariantWithoutScope(this))
-    }
-
-    fn mask_type(&self) -> Self::MaskType {
-        Bool
-    }
-
-    fn canonical(&self) -> CanonicalType {
-        self.ty.canonical()
-    }
-
-    fn from_canonical(canonical_type: CanonicalType) -> Self {
-        let ty = <UInt>::from_canonical(canonical_type);
-        if let Some(known_max) = Max::KNOWN_VALUE {
-            assert_eq!(ty, UInt::range_inclusive(0..=known_max));
-        }
-        Self {
-            ty,
-            _phantom: PhantomData,
-        }
-    }
-
-    fn source_location() -> SourceLocation {
-        SourceLocation::caller()
-    }
-}
-
-impl<Max: KnownSize> StaticType for Length<Max> {
-    const TYPE: Self = Self {
-        ty: UInt {
-            width: Max::VALUE.next_power_of_two().ilog2() as usize,
-        },
-        _phantom: PhantomData,
-    };
-    const MASK_TYPE: Self::MaskType = Bool;
-    const TYPE_PROPERTIES: TypeProperties = {
-        let mut p = <UInt<1>>::TYPE_PROPERTIES;
-        p.bit_width = Self::TYPE.ty.width;
-        p
-    };
-    const MASK_TYPE_PROPERTIES: TypeProperties = Bool::TYPE_PROPERTIES;
-}
-
-impl<Max: Size> ExprPartialEq<Self> for Length<Max> {
-    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_eq(Self::as_uint(rhs))
-    }
-    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_ne(Self::as_uint(rhs))
-    }
-}
-
-impl<Max: Size> ExprPartialOrd<Self> for Length<Max> {
-    fn cmp_lt(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_lt(Self::as_uint(rhs))
-    }
-    fn cmp_le(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_le(Self::as_uint(rhs))
-    }
-    fn cmp_gt(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_gt(Self::as_uint(rhs))
-    }
-    fn cmp_ge(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        Self::as_uint(lhs).cmp_ge(Self::as_uint(rhs))
-    }
-}
+#[hdl]
+pub type Length<Max: Size> = UIntInRangeInclusiveType<ConstUsize<0>, Max>;

 /// like [`std::vec::Vec`], except with a [`Expr`] for [`len()`][`Self::len()`] and a fixed capacity
 #[hdl]
@ -156,7 +19,31 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
        #[hdl]
        ArrayVec {
            elements: self.elements.uninit(),
-            len: self.len.zero(),
+            len: 0u8.cast_to(self.len),
+        }
+    }
+    #[hdl]
+    pub fn new_sim(self, uninit_element: impl ToSimValueWithType<T>) -> SimValue<Self> {
+        let uninit_element = uninit_element.into_sim_value_with_type(self.element());
+        #[hdl(sim)]
+        ArrayVec::<_, _> {
+            elements: SimValue::from_array_elements(
+                self.elements,
+                (0..self.elements.len()).map(|_| uninit_element.clone()),
+            ),
+            len: 0u8.cast_to(self.len),
+        }
+    }
+    #[hdl]
+    pub fn new_full_sim(
+        self,
+        elements: impl ToSimValueWithType<ArrayType<T, N>>,
+    ) -> SimValue<Self> {
+        let elements = elements.to_sim_value_with_type(self.elements);
+        #[hdl(sim)]
+        Self {
+            elements,
+            len: self.elements.len().to_sim_value_with_type(self.len),
        }
    }
    pub fn element(self) -> T {
@ -176,8 +63,8 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
        let elements = elements.to_expr();
        let len = len.to_expr();
        assert_eq!(
-            Length::new(N::from_usize(Expr::ty(elements).len())),
-            Expr::ty(len),
+            Length[N::from_usize(elements.ty().len())],
+            len.ty(),
            "len type mismatch",
        );
        #[hdl]
@ -189,9 +76,12 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
    pub fn len(this: impl ToExpr<Type = Self>) -> Expr<Length<N>> {
        this.to_expr().len
    }
+    pub fn len_sim(this: &SimValue<Self>) -> &SimValue<Length<N>> {
+        &this.len
+    }
    pub fn is_empty(this: impl ToExpr<Type = Self>) -> Expr<Bool> {
        let len = Self::len(this);
-        len.cmp_eq(Expr::ty(len).zero())
+        len.cmp_eq(0u8)
    }
    pub fn capacity(self) -> usize {
        self.elements.len()
@ -207,11 +97,77 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
        let this = this.to_expr();
        for (index, element) in this.elements.into_iter().enumerate() {
            #[hdl]
-            if index.cmp_lt(Length::as_uint(this.len)) {
+            if index.cmp_lt(this.len) {
                f(index, element);
            }
        }
    }
+    pub fn elements_sim_ref(this: &SimValue<Self>) -> &[SimValue<T>] {
+        &this.elements[..*this.len]
+    }
+    pub fn elements_sim_mut(this: &mut SimValue<Self>) -> &mut [SimValue<T>] {
+        let len = *this.len;
+        &mut this.elements[..len]
+    }
+    #[hdl]
+    pub async fn async_for_each_sim(
+        this: impl ToSimValue<Type = Self>,
+        mut f: impl AsyncFnMut(usize, SimValue<T>),
+    ) {
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this.into_sim_value();
+        for (index, element) in elements.into_iter().enumerate() {
+            if index.cmp_lt(*len) {
+                f(index, element).await;
+            }
+        }
+    }
+    #[hdl]
+    pub async fn async_for_each_sim_ref<'a>(
+        this: &'a SimValue<Self>,
+        mut f: impl AsyncFnMut(usize, &'a SimValue<T>),
+    ) {
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this;
+        for (index, element) in elements.iter().enumerate() {
+            if index.cmp_lt(**len) {
+                f(index, element).await;
+            }
+        }
+    }
+    #[hdl]
+    pub async fn async_for_each_sim_mut<'a>(
+        this: &'a mut SimValue<Self>,
+        mut f: impl AsyncFnMut(usize, &'a mut SimValue<T>),
+    ) {
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this;
+        for (index, element) in elements.iter_mut().enumerate() {
+            if index.cmp_lt(**len) {
+                f(index, element).await;
+            }
+        }
+    }
+    #[hdl]
+    pub fn try_push_sim(
+        this: &mut SimValue<Self>,
+        value: impl ToSimValueWithType<T>,
+    ) -> Result<(), SimValue<T>> {
+        let value = value.into_sim_value_with_type(this.ty().element());
+        let capacity = this.ty().capacity();
+        #[hdl(sim)]
+        let ArrayVec::<_, _> { elements, len } = this;
+        if **len < capacity {
+            elements[**len] = value;
+            **len += 1;
+            Ok(())
+        } else {
+            Err(value)
+        }
+    }
+    pub fn truncate_sim(this: &mut SimValue<Self>, len: usize) {
+        *this.len = len.min(*this.len);
+    }
    pub fn mapped_ty<U: Type>(self, new_element_ty: U) -> ArrayVec<U, N> {
        ArrayVec {
            elements: ArrayType[new_element_ty][N::from_usize(self.elements.len())],
@ -226,7 +182,7 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
    ) -> Expr<ArrayVec<U, N>> {
        let this = this.to_expr();
        #[hdl]
-        let mapped_array_vec = wire(Expr::ty(this).mapped_ty(new_element_ty));
+        let mapped_array_vec = wire(this.ty().mapped_ty(new_element_ty));
        connect(mapped_array_vec.len, this.len);
        Self::for_each(this, |index, element| {
            connect(mapped_array_vec[index], f(index, element));
@ -234,15 +190,42 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
        mapped_array_vec
    }
    #[hdl]
+    pub fn map_sim<U: Type>(
+        this: impl ToSimValue<Type = Self>,
+        uninit_element: impl ToSimValue<Type = U>,
+        mut f: impl FnMut(usize, SimValue<T>) -> SimValue<U>,
+    ) -> SimValue<ArrayVec<U, N>> {
+        let this = this.into_sim_value();
+        let uninit_element = uninit_element.into_sim_value();
+        let ty = this.ty().mapped_ty(uninit_element.ty());
+        #[hdl(sim)]
+        let Self { elements, len } = this;
+        #[hdl(sim)]
+        ArrayVec::<_, _> {
+            elements: SimValue::from_array_elements(
+                ty.elements,
+                SimValue::into_value(elements)
+                    .into_iter()
+                    .enumerate()
+                    .map(|(index, element)| {
+                        if index < *len {
+                            f(index, element)
+                        } else {
+                            uninit_element.clone()
+                        }
+                    }),
+            ),
+            len,
+        }
+    }
+    #[hdl]
    pub fn as_array_of_options(this: impl ToExpr<Type = Self>) -> Expr<ArrayType<HdlOption<T>, N>> {
        let this = this.to_expr();
        #[hdl]
-        let array_vec_as_array_of_options = wire(
-            ArrayType[HdlOption[Expr::ty(this).element()]]
-                [N::from_usize(Expr::ty(this).capacity())],
-        );
+        let array_vec_as_array_of_options =
+            wire(ArrayType[HdlOption[this.ty().element()]][N::from_usize(this.ty().capacity())]);
        for element in array_vec_as_array_of_options {
-            connect(element, Expr::ty(element).HdlNone());
+            connect(element, element.ty().HdlNone());
        }
        Self::for_each(this, |index, element| {
            connect(array_vec_as_array_of_options[index], HdlSome(element))
@ -263,3 +246,34 @@ where
        <ArrayType<T, N> as ExprIndex<Idx>>::expr_index(&this.elements, index)
    }
 }
+
+impl<T: Type> ArrayVec<T, ConstUsize<1>> {
+    #[hdl]
+    pub fn from_opt_sim(
+        opt: impl ToSimValue<Type = HdlOption<T>>,
+        uninit_element: impl ToSimValueWithType<T>,
+    ) -> SimValue<Self> {
+        let opt = opt.into_sim_value();
+        let ty = ArrayVec[opt.ty().HdlSome][ConstUsize];
+        #[hdl(sim)]
+        match opt {
+            HdlSome(v) => ty.new_full_sim([v]),
+            HdlNone => ty.new_sim(uninit_element),
+        }
+    }
+    #[hdl]
+    pub fn into_opt_sim(this: impl ToSimValue<Type = Self>) -> SimValue<HdlOption<T>> {
+        let this = this.into_sim_value();
+        #[hdl(sim)]
+        let Self { elements, len } = this;
+        let [element] = SimValue::into_value(elements);
+        let ty = HdlOption[element.ty()];
+        if *len == 0 {
+            #[hdl(sim)]
+            ty.HdlNone()
+        } else {
+            #[hdl(sim)]
+            ty.HdlSome(element)
+        }
+    }
+}
--- a/crates/cpu/tests/expected/decode_one_insn.vcd
+++ b/crates/cpu/tests/expected/decode_one_insn.vcd
--- a/crates/cpu/tests/expected/next_pc.vcd
+++ b/crates/cpu/tests/expected/next_pc.vcd
--- a/crates/cpu/tests/expected/reg_alloc.vcd
+++ b/crates/cpu/tests/expected/reg_alloc.vcd
--- a/crates/cpu/tests/next_pc.rs
+++ b/crates/cpu/tests/next_pc.rs
--- a/crates/cpu/tests/reg_alloc.rs
+++ b/crates/cpu/tests/reg_alloc.rs
@ -9,8 +9,6 @@ use cpu::{
    unit::{GlobalState, UnitKind},
 };
 use fayalite::{
-    assert_export_firrtl,
-    firrtl::ExportOptions,
    prelude::*,
    sim::{Simulation, time::SimDuration, vcd::VcdWriterDecls},
    util::RcWriter,
@ -61,7 +59,7 @@ fn test_reg_alloc() {
                [HdlSome(()), HdlNone()],
            },
            [0u8; 2],
-            0x12345678u32.cast_to_static(),
+            0x12345678u32.cast_to_static::<SInt<_>>(),
            OutputIntegerMode.DupLow32(),
            false,
            false,
@ -83,7 +81,7 @@ fn test_reg_alloc() {
                [HdlSome(()), HdlNone()],
            },
            [1u8, 0, 0],
-            1.cast_to_static(),
+            1.cast_to_static::<SInt<_>>(),
            OutputIntegerMode.Full64(),
            false,
            false,
@ -101,7 +99,7 @@ fn test_reg_alloc() {
                flag_regs: [HdlNone(), HdlSome(())],
            },
            [2u8, 4u8],
-            0.cast_to_static(),
+            0.cast_to_static::<SInt<_>>(),
            OutputIntegerMode.Full64(),
            0b0110_hdl_u4,
        ),
--- a/crates/cpu/tests/simple_power_isa_decoder.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder.rs
@ -0,0 +1,366 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use cpu::{
+    decoder::simple_power_isa::decode_one_insn,
+    instruction::{AddSubMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode},
+    util::array_vec::ArrayVec,
+};
+use fayalite::{prelude::*, sim::vcd::VcdWriterDecls, util::RcWriter};
+use std::{
+    fmt::{self, Write as _},
+    io::Write,
+    process::Command,
+};
+
+struct TestCase {
+    mnemonic: &'static str,
+    first_input: u32,
+    second_input: Option<u32>,
+    output: SimValue<ArrayVec<MOp, ConstUsize<2>>>,
+    loc: &'static std::panic::Location<'static>,
+}
+
+impl fmt::Debug for TestCase {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            mnemonic,
+            first_input,
+            second_input,
+            output,
+            loc,
+        } = self;
+        let mut debug_struct = f.debug_struct("TestCase");
+        debug_struct
+            .field("mnemonic", mnemonic)
+            .field("first_input", &format_args!("0x{first_input:08x}"));
+        if let Some(second_input) = second_input {
+            debug_struct.field("second_input", &format_args!("0x{second_input:08x}"));
+        } else {
+            debug_struct.field("second_input", &format_args!("None"));
+        }
+        debug_struct
+            .field("output", &ArrayVec::elements_sim_ref(output))
+            .field("loc", &format_args!("{loc}"))
+            .finish()
+    }
+}
+
+#[hdl]
+fn test_cases() -> Vec<TestCase> {
+    let mut retval = Vec::new();
+    #[track_caller]
+    fn insn_single(
+        mnemonic: &'static str,
+        first_input: u32,
+        second_input: Option<u32>,
+        output: impl ToSimValue<Type = MOp>,
+    ) -> TestCase {
+        let zero_mop = UInt::new_dyn(MOp.canonical().bit_width())
+            .zero()
+            .cast_bits_to(MOp);
+        let mut single_storage = ArrayVec::new_sim(ArrayVec[MOp][ConstUsize], &zero_mop);
+        ArrayVec::try_push_sim(&mut single_storage, zero_mop).expect("known to have space");
+        ArrayVec::elements_sim_mut(&mut single_storage)[0] = output.to_sim_value();
+        TestCase {
+            mnemonic,
+            first_input,
+            second_input,
+            output: single_storage.clone(),
+            loc: std::panic::Location::caller(),
+        }
+    }
+    retval.push(insn_single(
+        "addi 3, 4, 0x1234",
+        0x38641234,
+        None,
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0x1234.cast_to_static::<SInt<_>>(),
+            #[hdl(sim)]
+            OutputIntegerMode::Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "addis 3, 4, 0x1234",
+        0x3C641234,
+        None,
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [
+                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0x12340000.cast_to_static::<SInt<_>>(),
+            #[hdl(sim)]
+            OutputIntegerMode::Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "addpcis 3, 0x1234",
+        0x4c7a1204,
+        None,
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value; _],
+            0x12340004.cast_to_static::<SInt<_>>(),
+            #[hdl(sim)]
+            OutputIntegerMode::Full64(),
+            false,
+            false,
+            false,
+            true,
+        ),
+    ));
+    retval.push(insn_single(
+        "add. 3, 4, 5",
+        0x7c642a15,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[MOpRegNum::power_isa_gpr_reg_num(3)],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            #[hdl(sim)]
+            OutputIntegerMode::Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "addic. 3, 4, 0x1234",
+        0x34641234,
+        None,
+        AddSubMOp::add_sub_i(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0x1234.cast_to_static::<SInt<_>>(),
+            #[hdl(sim)]
+            OutputIntegerMode::Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval.push(insn_single(
+        "addc. 3, 4, 5",
+        0x7c642815,
+        None,
+        AddSubMOp::add_sub(
+            MOpDestReg::new_sim(
+                &[
+                    MOpRegNum::power_isa_gpr_reg_num(3),
+                    MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                ],
+                &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+            ),
+            [
+                MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value,
+                MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value,
+                MOpRegNum::const_zero().value,
+            ],
+            0.cast_to_static::<SInt<_>>(),
+            #[hdl(sim)]
+            OutputIntegerMode::Full64(),
+            false,
+            false,
+            false,
+            false,
+        ),
+    ));
+    retval
+}
+
+#[test]
+fn test_test_cases_assembly() -> std::io::Result<()> {
+    let llvm_mc_regex = regex::Regex::new(r"llvm-mc(-\d+)?$").expect("known to be a valid regex");
+    let llvm_mc = which::which_re(llvm_mc_regex)
+        .expect("can't find llvm-mc or llvm-mc-<num> in path")
+        .next()
+        .expect("can't find llvm-mc or llvm-mc-<num> in path");
+    let test_cases = test_cases();
+    let mut assembly = String::new();
+    for TestCase {
+        mnemonic,
+        first_input: _,
+        second_input: _,
+        output: _,
+        loc: _,
+    } in &test_cases
+    {
+        writeln!(assembly, "{mnemonic}").unwrap();
+    }
+    let (reader, mut writer) = std::io::pipe()?;
+    let thread = std::thread::spawn(move || writer.write_all(assembly.as_bytes()));
+    let std::process::Output {
+        status,
+        stdout,
+        stderr,
+    } = Command::new(&llvm_mc)
+        .arg("--triple=powerpc64le-linux-gnu")
+        .arg("--assemble")
+        .arg("--filetype=asm")
+        .arg("--show-encoding")
+        .arg("-")
+        .stdin(reader)
+        .output()?;
+    let _ = thread.join();
+    let stderr = String::from_utf8_lossy(&stderr);
+    eprint!("{stderr}");
+    if !status.success() {
+        panic!("{} failed: {status}", llvm_mc.display());
+    }
+    let stdout = String::from_utf8_lossy(&stdout);
+    print!("{stdout}");
+    let mut lines = stdout.lines();
+    let text_line = lines.next();
+    assert_eq!(text_line, Some("\t.text"));
+    for test_case @ TestCase {
+        mnemonic: _,
+        first_input,
+        second_input,
+        output: _,
+        loc: _,
+    } in test_cases
+    {
+        let Some(line) = lines.next() else {
+            panic!("output missing line for: {test_case:?}");
+        };
+        let Some((_, comment)) = line.split_once('#') else {
+            panic!("output line missing comment. test_case={test_case:?}\nline:\n{line}");
+        };
+        let [b0, b1, b2, b3] = first_input.to_le_bytes();
+        let expected_comment = if let Some(second_input) = second_input {
+            let [b4, b5, b6, b7] = second_input.to_le_bytes();
+            format!(
+                " encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x},0x{b4:02x},0x{b5:02x},0x{b6:02x},0x{b7:02x}]"
+            )
+        } else {
+            format!(" encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x}]")
+        };
+        assert_eq!(
+            comment, expected_comment,
+            "test_case={test_case:?}\nline:\n{line}"
+        );
+    }
+    for line in lines {
+        assert!(line.trim().is_empty(), "bad trailing output line: {line:?}");
+    }
+    Ok(())
+}
+
+#[hdl]
+#[test]
+fn test_decode_insn() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = decode_one_insn();
+    let mut sim = Simulation::new(m);
+    let writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    struct DumpVcdOnDrop {
+        writer: Option<RcWriter>,
+    }
+    impl Drop for DumpVcdOnDrop {
+        fn drop(&mut self) {
+            if let Some(mut writer) = self.writer.take() {
+                let vcd = String::from_utf8(writer.take()).unwrap();
+                println!("####### VCD:\n{vcd}\n#######");
+            }
+        }
+    }
+    let mut writer = DumpVcdOnDrop {
+        writer: Some(writer),
+    };
+    for test_case @ TestCase {
+        mnemonic: _,
+        first_input,
+        second_input,
+        output: _,
+        loc: _,
+    } in test_cases()
+    {
+        sim.write(sim.io().first_input, first_input);
+        sim.write(
+            sim.io().second_input,
+            if let Some(v) = second_input {
+                #[hdl(sim)]
+                HdlSome(v)
+            } else {
+                #[hdl(sim)]
+                HdlNone()
+            },
+        );
+        sim.advance_time(SimDuration::from_micros(1));
+        let second_input_used = sim.read_bool(sim.io().second_input_used);
+        let is_illegal = sim.read_bool(sim.io().is_illegal);
+        let output = sim.read(sim.io().output);
+        #[derive(Debug)]
+        #[expect(dead_code, reason = "used only for Debug formatting")]
+        struct FormattedOutput<'a> {
+            insns: &'a [SimValue<MOp>],
+            second_input_used: bool,
+            is_illegal: bool,
+        }
+        let expected = format!(
+            "{:#?}",
+            FormattedOutput {
+                insns: ArrayVec::elements_sim_ref(&test_case.output),
+                second_input_used: second_input.is_some(),
+                is_illegal: false,
+            },
+        );
+        let output = format!(
+            "{:#?}",
+            FormattedOutput {
+                insns: ArrayVec::elements_sim_ref(&output),
+                second_input_used,
+                is_illegal,
+            },
+        );
+        assert!(
+            expected == output,
+            "test_case={test_case:#?}\noutput={output}"
+        );
+    }
+    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("expected/decode_one_insn.vcd") {
+        panic!();
+    }
+}
+
+#[hdl]
+#[test]
+fn test_simple_power_isa_decoder() {
+    // TODO
+}
--- a/scripts/check-copyright.sh
+++ b/scripts/check-copyright.sh
@ -31,6 +31,7 @@ function check_file()
 POUND_HEADER=('^"# SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"# See Notices.txt for copyright information"$')
 SLASH_HEADER=('^"// SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"// See Notices.txt for copyright information"$')
 MD_HEADER=('^"<!--"$' '^"SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"See Notices.txt for copyright information"$')
+MERMAID_HEADER=('^"%% SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"%% See Notices.txt for copyright information"$')

 function main()
 {
@ -51,6 +52,9 @@ function main()
        /.forgejo/workflows/*.yml|*/.gitignore|*.toml)
            check_file "$file" "${POUND_HEADER[@]}"
            ;;
+        *.mermaid)
+            check_file "$file" "${MERMAID_HEADER[@]}"
+            ;;
        *.md)
            check_file "$file" "${MD_HEADER[@]}"
            ;;
Author	SHA1	Message	Date
Jacob Lifshay	62512960c3	decode some more add instructions	2026-01-15 16:10:03 -08:00
Jacob Lifshay	b7b6a02777	decodes an addi instruction	2026-01-14 21:41:25 -08:00
Jacob Lifshay	6d40eaadb3	WIP adding simple power isa decoder	2026-01-12 07:10:58 -08:00
Jacob Lifshay	305d7b0ae6	rename src/powerisa.rs -> src/powerisa_instructions_xml.rs	2026-01-12 03:31:06 -08:00
Jacob Lifshay	781dbc6bcb	add copyright header to build.rs	2026-01-09 02:05:08 -08:00
Jacob Lifshay	5faf0899a8	fully parse powerisa-instructions.xml	2026-01-09 02:03:59 -08:00
Jacob Lifshay	8c02483b65	wip parsing the xml	2026-01-08 00:09:20 -08:00
Jacob Lifshay	e4a7d9f59c	add build script that parses the PowerISA v3.1C pdf and produces an xml file	2026-01-07 14:19:46 -08:00
Jacob Lifshay	3b5104c8fa	fix vcd to match test output	2025-12-16 23:25:54 -08:00
Jacob Lifshay	2de4a67360	add link to other NLnet task and note lack of optimization	2025-12-16 23:10:07 -08:00
Jacob Lifshay	d5a7d9dd9e	next_pc works afaict	2025-12-16 23:06:32 -08:00
Jacob Lifshay	59da0aec06	WIP fixing bugs	2025-12-16 02:32:19 -08:00
Jacob Lifshay	5e1238b5c7	replace tests/next_pc's demo program with a simple expression parser as a better demo	2025-12-15 21:40:11 -08:00
Jacob Lifshay	bc9a3a5ce7	add missing copyright header and check-copyright.sh support for .mermaid	2025-12-15 03:00:37 -08:00
Jacob Lifshay	d42f010cda	WIP fixing bugs	2025-12-15 02:48:40 -08:00
Jacob Lifshay	84e4fde512	fix queueing errors	2025-12-15 00:47:53 -08:00
Jacob Lifshay	8ab63f3c6a	update fayalite	2025-12-14 21:05:59 -08:00
Jacob Lifshay	f39f40ce1f	fix next_pc::Queue and add test	2025-12-14 20:39:15 -08:00
Jacob Lifshay	cbd52c60a8	WIP: next_pc test fails	2025-12-14 01:26:18 -08:00
Jacob Lifshay	c87a1b8e1e	wrote out all of next_pc and tests/next_pc	2025-12-13 22:42:34 -08:00
Jacob Lifshay	cfd04469ce	WIP linking next_pc stages together	2025-12-10 20:31:04 -08:00
Jacob Lifshay	231f5e72ec	WIP: completed stages of next-pc logic, still need to combine them into a pipeline	2025-12-10 20:31:04 -08:00
Jacob Lifshay	033d5d4f34	WIP adding next_pc: add call stack	2025-12-10 20:31:04 -08:00
Jacob Lifshay	7a77c02cda	WIP adding next_pc: added mock_fetch_decode_pipe	2025-12-10 20:31:04 -08:00
Jacob Lifshay	61d52bd028	add Serialize/Deserialize impls for CpuConfig	2025-12-10 20:31:04 -08:00
Jacob Lifshay	554238c544	update for new fayalite	2025-12-10 20:31:04 -08:00
Jacob Lifshay	24d6537ffe	update Fayalite to get new features and bug fixes	2025-12-10 20:31:04 -08:00
Jacob Lifshay	c30bd0737f	add readme	2025-10-24 16:36:31 -07:00
Jacob Lifshay	291ad59b02	update CI to use new fayalite-deps container	2025-10-24 02:54:03 -07:00
Jacob Lifshay	5e8bc3e580	upgrade to Fayalite edcc5927a5f9ebca6 as part of this I switched to using Fayalite's UIntInRangeInclusive instead of using a custom Length struct	2025-10-24 02:53:35 -07:00
Jacob Lifshay	0e7a518bd0	switch to use server's new actions org	2025-10-10 00:03:53 -07:00