Eddie Hung 4ae7f3a8ed Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor ... opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs		2020-04-01 14:17:01 -07:00
..
aiger	tests/aiger: Add missing .gitignore	2020-02-15 19:52:21 +01:00
arch	Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor	2020-04-01 14:17:01 -07:00
asicworld
bram
errors
fsm
hana
liberty
lut
memfile	Added 'set -e' into tests/memfile/run-test.sh	2020-02-06 10:45:40 -03:00
memories
opt	Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor	2020-04-01 14:17:01 -07:00
opt_share
proc
realmath
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat
select	Do not warn on empty selection with prefixed arg_memb.	2020-03-23 17:50:11 +00:00
share
simple	Add dynamic slicing Verilog testcase	2020-03-31 11:51:31 -07:00
simple_abc9	Update simple_abc9 tests	2020-02-27 10:17:29 -08:00
smv
sva
svinterfaces
svtypes	Support module/package/interface/block scope for typedef names.	2020-03-23 20:07:22 +00:00
techmap	techmap: Fix cell names with _TECHMAP_REPLACE_.*	2020-03-23 11:17:07 +01:00
tools
unit
various	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
vloghtb