Emil J 86448c0001 Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef ... Undefine set&reset behavior of $dffsr		2026-04-08 14:22:34 +00:00
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aiger	yosys: use newcelltypes for yosys_celltypes users	2026-03-04 12:39:44 +01:00
aiger2
ast	genrtlil: even faster removeSignalFromCaseTree	2026-03-18 23:33:35 +01:00
blif	blifparse: add bounds check	2026-02-11 12:16:02 +01:00
json	Support param. default values in JSON FE and SV BE	2026-02-11 08:10:55 -08:00
liberty	fixup! read_liberty: model clear_preset_variable correctly	2026-03-06 14:24:18 +01:00
rpc
rtlil	Work around std::reverse miscompilation with empty range	2026-03-06 02:03:21 +00:00
verific	Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.	2026-02-02 15:26:03 -08:00
verilog	support automatic lifetime qualifier on procedural variables	2026-02-27 20:42:52 +03:00