3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 10:55:51 +00:00
yosys/tests/liberty/semicolextra.lib.verilogsim.ok

11 lines
165 B
Text

module DFF (D, CK, Q);
reg IQ, IQN;
input D;
input CK;
output Q;
always @(posedge CK) begin
// "D"
IQ <= D;
IQN <= ~(D);
end
endmodule