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Fix existing tests/liberty tests, and add them to Makefile.

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This commit is contained in:
Sean Luchen 2025-04-03 09:56:24 -07:00
parent 4610889d27
commit bdcbbf2db6
10 changed files with 68 additions and 66 deletions
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1
Makefile
View file

@ -889,6 +889,7 @@ SH_TEST_DIRS += tests/rpc
SH_TEST_DIRS += tests/memfile
SH_TEST_DIRS += tests/fmt
SH_TEST_DIRS += tests/cxxrtl
SH_TEST_DIRS += tests/liberty
ifeq ($(ENABLE_FUNCTIONAL_TESTS),1)
SH_TEST_DIRS += tests/functional
endif

2
tests/liberty/XNOR2X1.lib.filtered.ok
View file

@ -9,7 +9,7 @@ library(ls05_stdcells) {
}
pin(Y) {
direction : output ;
function : !(B&!A|!B&A) ;
function : "!(B&!A|!B&A)" ;
}
}
}

2
tests/liberty/XNOR2X1.lib.verilogsim.ok
View file

@ -2,5 +2,5 @@ module XNOR2X1 (B, A, Y);
input B;
input A;
output Y;
assign Y = !(B&!A|!B&A); // !(B&!A|!B&A)
assign Y = !(B&!A|!B&A); // "!(B&!A|!B&A)"
endmodule

50
tests/liberty/normal.lib.filtered.ok
View file

@ -6,7 +6,7 @@ library(supergate) {
}
pin(Y) {
direction : output ;
function : A' ;
function : "A'" ;
}
}
cell(tri_inv) {
@ -19,7 +19,7 @@ library(supergate) {
}
pin(Z) {
direction : output ;
function : A' ;
function : "A'" ;
}
}
cell(buffer) {
@ -29,7 +29,7 @@ library(supergate) {
}
pin(Y) {
direction : output ;
function : A ;
function : "A" ;
}
}
cell(nand2) {
@ -42,7 +42,7 @@ library(supergate) {
}
pin(Y) {
direction : output ;
function : (A * B)' ;
function : "(A * B)'" ;
}
}
cell(nor2) {
@ -55,7 +55,7 @@ library(supergate) {
}
pin(Y) {
direction : output ;
function : (A + B)' ;
function : "(A + B)'" ;
}
}
cell(xor2) {
@ -68,7 +68,7 @@ library(supergate) {
}
pin(Y) {
direction : output ;
function : (A *B') + (A' * B) ;
function : "(A *B') + (A' * B)" ;
}
}
cell(imux2) {
@ -84,16 +84,16 @@ library(supergate) {
}
pin(Y) {
direction : output ;
function : ( (A * S) + (B * S') )' ;
function : "( (A * S) + (B * S') )'" ;
}
}
cell(dff) {
area : 6 ;
ff(IQ, IQN) {
next_state : D ;
clocked_on : CLK ;
clear : RESET ;
preset : PRESET ;
ff("IQ", "IQN") {
next_state : "D" ;
clocked_on : "CLK" ;
clear : "RESET" ;
preset : "PRESET" ;
clear_preset_var1 : L ;
clear_preset_var2 : L ;
}
@ -111,18 +111,18 @@ library(supergate) {
}
pin(Q) {
direction : output ;
function : IQ ;
function : "IQ" ;
}
pin(QN) {
direction : output ;
function : IQN ;
function : "IQN" ;
}
}
cell(latch) {
area : 5 ;
latch(IQ, IQN) {
enable : G ;
data_in : D ;
latch("IQ", "IQN") {
enable : "G" ;
data_in : "D" ;
}
pin(D) {
direction : input ;
@ -132,11 +132,11 @@ library(supergate) {
}
pin(Q) {
direction : output ;
function : IQ ;
function : "IQ" ;
}
pin(QN) {
direction : output ;
function : IQN ;
function : "IQN" ;
}
}
cell(aoi211) {
@ -152,7 +152,7 @@ library(supergate) {
}
pin(Y) {
direction : output ;
function : ((A * B) + C)' ;
function : "((A * B) + C)'" ;
}
}
cell(oai211) {
@ -168,7 +168,7 @@ library(supergate) {
}
pin(Y) {
direction : output ;
function : ((A + B) * C)' ;
function : "((A + B) * C)'" ;
}
}
cell(halfadder) {
@ -181,11 +181,11 @@ library(supergate) {
}
pin(C) {
direction : output ;
function : (A * B) ;
function : "(A * B)" ;
}
pin(Y) {
direction : output ;
function : (A *B') + (A' * B) ;
function : "(A *B') + (A' * B)" ;
}
}
cell(fulladder) {
@ -201,11 +201,11 @@ library(supergate) {
}
pin(CO) {
direction : output ;
function : (((A * B)+(B * CI))+(CI * A)) ;
function : "(((A * B)+(B * CI))+(CI * A))" ;
}
pin(Y) {
direction : output ;
function : ((A^B)^CI) ;
function : "((A^B)^CI)" ;
}
}
}

60
tests/liberty/normal.lib.verilogsim.ok
View file

@ -1,86 +1,86 @@
module inv (A, Y);
input A;
output Y;
assign Y = ~A; // A'
assign Y = ~A; // "A'"
endmodule
module tri_inv (A, S, Z);
input A;
input S;
output Z;
assign Z = ~A; // A'
assign Z = ~A; // "A'"
endmodule
module buffer (A, Y);
input A;
output Y;
assign Y = A; // A
assign Y = A; // "A"
endmodule
module nand2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A&B); // (A * B)'
assign Y = ~(A&B); // "(A * B)'"
endmodule
module nor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A|B); // (A + B)'
assign Y = ~(A|B); // "(A + B)'"
endmodule
module xor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
assign Y = (A&~B)|(~A&B); // "(A *B') + (A' * B)"
endmodule
module imux2 (A, B, S, Y);
input A;
input B;
input S;
output Y;
assign Y = ~(&(A&S)|(B&~S)&); // ( (A * S) + (B * S') )'
assign Y = ~(&(A&S)|(B&~S)&); // "( (A * S) + (B * S') )'"
endmodule
module dff (D, CLK, RESET, PRESET, Q, QN);
reg IQ, IQN;
reg "IQ", "IQN";
input D;
input CLK;
input RESET;
input PRESET;
output Q;
assign Q = IQ; // IQ
assign Q = IQ; // "IQ"
output QN;
assign QN = IQN; // IQN
assign QN = IQN; // "IQN"
always @(posedge CLK, posedge RESET, posedge PRESET) begin
if ((RESET) && (PRESET)) begin
IQ <= 0;
IQN <= 0;
"IQ" <= 0;
"IQN" <= 0;
end
else if (RESET) begin
IQ <= 0;
IQN <= 1;
"IQ" <= 0;
"IQN" <= 1;
end
else if (PRESET) begin
IQ <= 1;
IQN <= 0;
"IQ" <= 1;
"IQN" <= 0;
end
else begin
// D
IQ <= D;
IQN <= ~(D);
// "D"
"IQ" <= D;
"IQN" <= ~(D);
end
end
endmodule
module latch (D, G, Q, QN);
reg IQ, IQN;
reg "IQ", "IQN";
input D;
input G;
output Q;
assign Q = IQ; // IQ
assign Q = IQ; // "IQ"
output QN;
assign QN = IQN; // IQN
assign QN = IQN; // "IQN"
always @* begin
if (G) begin
IQ <= D;
IQN <= ~(D);
"IQ" <= D;
"IQN" <= ~(D);
end
end
endmodule
@ -89,29 +89,29 @@ module aoi211 (A, B, C, Y);
input B;
input C;
output Y;
assign Y = ~((A&B)|C); // ((A * B) + C)'
assign Y = ~((A&B)|C); // "((A * B) + C)'"
endmodule
module oai211 (A, B, C, Y);
input A;
input B;
input C;
output Y;
assign Y = ~((A|B)&C); // ((A + B) * C)'
assign Y = ~((A|B)&C); // "((A + B) * C)'"
endmodule
module halfadder (A, B, C, Y);
input A;
input B;
output C;
assign C = (A&B); // (A * B)
assign C = (A&B); // "(A * B)"
output Y;
assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
assign Y = (A&~B)|(~A&B); // "(A *B') + (A' * B)"
endmodule
module fulladder (A, B, CI, CO, Y);
input A;
input B;
input CI;
output CO;
assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
assign CO = (((A&B)|(B&CI))|(CI&A)); // "(((A * B)+(B * CI))+(CI * A))"
output Y;
assign Y = ((A^B)^CI); // ((A^B)^CI)
assign Y = ((A^B)^CI); // "((A^B)^CI)"
endmodule

5
tests/liberty/run-test.sh
View file

@ -7,9 +7,10 @@ for x in *.lib; do
../../yosys-filterlib - $x 2>/dev/null > $x.filtered
../../yosys-filterlib -verilogsim $x > $x.verilogsim
diff $x.filtered $x.filtered.ok && diff $x.verilogsim $x.verilogsim.ok
done
done || exit 1
for x in *.ys; do
echo "Running $x.."
../../yosys -q -s $x -l ${x%.ys}.log
done
done || exit 1

4
tests/liberty/semicolextra.lib.filtered.ok
View file

@ -10,8 +10,8 @@ library(supergate) {
clock : true ;
}
ff(IQ, IQN) {
clocked_on : CK ;
next_state : D ;
clocked_on : "CK" ;
next_state : "D" ;
}
pin(Q) {
direction : output ;

2
tests/liberty/semicolextra.lib.verilogsim.ok
View file

@ -4,7 +4,7 @@ module DFF (D, CK, Q);
input CK;
output Q;
always @(posedge CK) begin
// D
// "D"
IQ <= D;
IQN <= ~(D);
end

4
tests/liberty/semicolmissing.lib.filtered.ok
View file

@ -12,11 +12,11 @@ library(supergate) {
}
pin(CO) {
direction : output ;
function : (((A * B)+(B * CI))+(CI * A)) ;
function : "(((A * B)+(B * CI))+(CI * A))" ;
}
pin(Y) {
direction : output ;
function : ((A^B)^CI) ;
function : "((A^B)^CI)" ;
}
}
}

4
tests/liberty/semicolmissing.lib.verilogsim.ok
View file

@ -3,7 +3,7 @@ module fulladder (A, B, CI, CO, Y);
input B;
input CI;
output CO;
assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
assign CO = (((A&B)|(B&CI))|(CI&A)); // "(((A * B)+(B * CI))+(CI * A))"
output Y;
assign Y = ((A^B)^CI); // ((A^B)^CI)
assign Y = ((A^B)^CI); // "((A^B)^CI)"
endmodule