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Code Activity
yosys/techlibs/intel_le/common
History
Artur Swiderski f7dc93c652 some refactoring
2020-11-01 16:09:03 +01:00
..
abc9_map.v start implementing support for intel le based logic devices 2020-10-10 19:08:54 +02:00
abc9_model.v start implementing support for intel le based logic devices 2020-10-10 19:08:54 +02:00
abc9_unmap.v start implementing support for intel le based logic devices 2020-10-10 19:08:54 +02:00
arith_le_map.v some refactoring 2020-11-01 16:09:03 +01:00
bram_m9k.txt minor cleanup and fixes 2020-10-24 00:02:05 +02:00
dff_map.v start implementing support for intel le based logic devices 2020-10-10 19:08:54 +02:00
dff_sim.v some refactoring 2020-11-01 16:09:03 +01:00
le_map.v before some refactoring 2020-10-31 00:59:48 +01:00
le_sim.v some refactoring 2020-11-01 16:09:03 +01:00
megafunction_bb.v before some refactoring 2020-10-31 00:59:48 +01:00
mem_sim.v some refactoring 2020-11-01 16:09:03 +01:00
quartus_rename.v some refactoring 2020-11-01 16:09:03 +01:00