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yosys/tests/simple
2016-07-08 14:31:06 +02:00
..
.gitignore
aes_kexp128.v
always01.v
always02.v
always03.v
arraycells.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
arrays01.v
carryadd.v
constmuldivmod.v Added opt_expr support for div/mod by power-of-two 2016-05-29 12:17:36 +02:00
constpower.v
dff_different_styles.v Another block of spelling fixes 2015-08-14 23:27:05 +02:00
fiedler-cooley.v
forgen01.v
forgen02.v
fsm.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
generate.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
graphtest.v Added tests/simple/graphtest.v 2015-11-30 11:41:12 +01:00
hierarchy.v Another block of spelling fixes 2015-08-14 23:27:05 +02:00
i2c_master_tests.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
loops.v Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
macros.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
mem2reg.v Fixed init issue in mem2reg_test2 test case 2016-06-17 20:15:11 +02:00
mem_arst.v
memory.v Fixed mem assignment in left-hand-side concatenation 2016-07-08 14:31:06 +02:00
multiplier.v
muxtree.v improvements in muxtree/select_leaves test 2015-01-18 13:24:01 +01:00
omsp_dbg_uart.v Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
operators.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
paramods.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
partsel.v Added support for "upto" wires to Verilog front- and back-end 2014-07-28 14:25:03 +02:00
process.v
realexpr.v Fixed handling of mixed real/int ternary expressions 2014-06-25 10:05:36 +02:00
repwhile.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
rotate.v Another block of spelling fixes 2015-08-14 23:27:05 +02:00
run-test.sh Added "make -j{N}" support to "make test" 2014-07-30 19:23:26 +02:00
scopes.v Improved scope resolution of local regs in Verilog+AST frontend 2014-08-05 12:15:53 +02:00
signedexpr.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
sincos.v
subbytes.v
task_func.v More bugfixes in handling of parameters in tasks and functions 2015-11-12 13:02:36 +01:00
undef_eqx_nex.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
usb_phy_tests.v Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
values.v
vloghammer.v Another block of spelling fixes 2015-08-14 23:27:05 +02:00
wreduce.v Improvements in wreduce 2015-10-31 13:39:30 +01:00