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Code Activity
yosys/frontends/ast
History
Udi Finkelstein f6fe73b31f Fixed remaining cases where we check fo wire reg/wire incorrect assignments 
on Yosys-generated assignments.
In this case, offending code was:

module top(input in, output out);
function func;
  input arg;
  func = arg;
endfunction
assign out = func(in);
endmodule
2018-09-18 01:23:40 +03:00
..
ast.cc Modified errors into warnings 2018-06-05 18:03:22 +03:00
ast.h Modified errors into warnings 2018-06-05 18:03:22 +03:00
dpicall.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
genrtlil.cc Add $allconst and $allseq cell types 2018-02-23 13:14:47 +01:00
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
simplify.cc Fixed remaining cases where we check fo wire reg/wire incorrect assignments 2018-09-18 01:23:40 +03:00