Udi Finkelstein f6fe73b31f Fixed remaining cases where we check fo wire reg/wire incorrect assignments ... on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule		2018-09-18 01:23:40 +03:00
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ast	Fixed remaining cases where we check fo wire reg/wire incorrect assignments	2018-09-18 01:23:40 +03:00
blif	Increase maximum LUT size in blifparse to 12 bits	2017-09-27 15:27:42 +02:00
ilang	Added avail params to ilang format, check module params in 'hierarchy -check'	2016-10-22 11:05:49 +02:00
json	Parse reals as string in JSON front-end	2017-09-26 14:37:03 +02:00
liberty	Improve handling of "bus" pins in liberty front-end (some files use bus.pin.direction)	2018-02-15 17:36:08 +01:00
verific	Fix SVA handling of NON_CONSECUTIVE_REPEAT and GOTO_REPEAT	2018-03-10 16:24:01 +01:00
verilog	Modified errors into warnings	2018-06-05 18:03:22 +03:00