mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
7608985d2c
I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
32 lines
562 B
Systemverilog
32 lines
562 B
Systemverilog
module top(
|
|
output logic [5:0] out
|
|
);
|
|
always_comb begin
|
|
out = '0;
|
|
case ($bits (out)) 6:
|
|
case ($size (out)) 6:
|
|
case ($high (out)) 5:
|
|
case ($low (out)) 0:
|
|
case ($left (out)) 5:
|
|
case ($right(out)) 0:
|
|
case (6) $bits (out):
|
|
case (6) $size (out):
|
|
case (5) $high (out):
|
|
case (0) $low (out):
|
|
case (5) $left (out):
|
|
case (0) $right(out):
|
|
out = '1;
|
|
endcase
|
|
endcase
|
|
endcase
|
|
endcase
|
|
endcase
|
|
endcase
|
|
endcase
|
|
endcase
|
|
endcase
|
|
endcase
|
|
endcase
|
|
endcase
|
|
end
|
|
endmodule
|