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yosys/tests/arch
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Emil J. Tywoniak 36e91fc48f tests: exclude signorm marker cells from two more cell-count assertions 
Same as eb32507cb, for two `t:*` counts it missed. They only differ once
a design can still be in signorm mode when the assertion runs; the
subtraction is a no-op otherwise.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
2026-07-21 16:52:45 +02:00
..
analogdevices WIP 2026-07-17 23:48:54 +02:00
anlogic Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
common Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
ecp5 ecp5: loosen tests 2026-07-17 23:38:01 +02:00
efinix Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
fabulous Cleanup 2026-07-08 08:34:01 +02:00
gatemate tests/gatemate: update fsm LUT counts for new proc src mapping 2026-07-20 15:01:30 +02:00
gowin gowin: loosen tests 2026-07-17 23:38:01 +02:00
ice40 tests: exclude signorm marker cells from two more cell-count assertions 2026-07-21 16:52:45 +02:00
intel_alm intel_alm: loosen tests 2026-07-17 23:38:01 +02:00
machxo2 Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
microchip Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
nanoxplore Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
nexus nexus: loosen tests 2026-07-17 23:38:01 +02:00
quicklogic Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 2026-07-09 08:46:46 +00:00
xilinx WIP 2026-07-17 23:48:54 +02:00
generate_mk.py Move output redirect to one place 2026-04-16 11:00:44 +02:00