Robert O'Callahan f25f8fe7c4 In the Verilog backend, only sort modules that we're going to emit. ... If you have a large design with a lot of modules and you use the Verilog backend to emit modules one at a time to separate files, performance is very low. The problem is that the Verilog backend calls `design->sort()` every time, which sorts the contents of all modules, and this is slow even when everything is already sorted. We can easily fix this by only sorting the contents of modules that we're actually going to emit.		2025-07-21 05:32:31 +00:00
..
Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
verilog_backend.cc	In the Verilog backend, only sort modules that we're going to emit.	2025-07-21 05:32:31 +00:00
verilog_backend.h	rename: add -unescape	2025-06-24 12:33:33 +02:00