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The implementation for the implication operator in cover mode actually implements the followed-by operator, so we can re-use it unchanged. It is not always the correct behavior for the implication operator in cover mode, but a) it will only cause false positives not miss anything so if the behavior is unexpected it will be visible in the produced traces, b) it is unlikely to make a difference for most properties one would practically use in cover mode, c) at least one other widely used SVA implementations behaves the same way and d) it's not clear whether we can fix this without rewriting most of verificsva.cc |
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| .. | ||
| example.sby | ||
| example.sv | ||
| Makefile.inc | ||
| README | ||
| verific.cc | ||
| verific.h | ||
| verificsva.cc | ||
This directory contains Verific bindings for Yosys. Use Tabby CAD Suite from YosysHQ if you need Yosys+Verific. https://www.yosyshq.com/ Contact YosysHQ at contact@yosyshq.com for free evaluation binaries of Tabby CAD Suite. Verific Features that should be enabled in your Verific library =============================================================== database/DBCompileFlags.h: DB_PRESERVE_INITIAL_VALUE Testing Verific+Yosys+SymbiYosys for formal verification ======================================================== Install Yosys+Verific, SymbiYosys, and Yices2. Install instructions: http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing Then run in the following command in this directory: sby -f example.sby This will generate approximately one page of text output. The last lines should be something like this: SBY [example] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:00 (0) SBY [example] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:00 (0) SBY [example] summary: engine_0 (smtbmc yices) returned PASS for basecase SBY [example] summary: engine_0 (smtbmc yices) returned PASS for induction SBY [example] summary: successful proof by k-induction. SBY [example] DONE (PASS, rc=0)